jankae/LibreVNA
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1055 commits 11 branches 20 tags 314 MiB
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19 commits

Author SHA1 Message Date
Jan Käberich 733d0ffbf4 fix order of LO1 and source unlock LEDs 2025-01-05 18:15:30 +01:00
Jan Käberich a4faeb28b0 Working dwell time feature 
- Bugfixes:
	- improve SPI timing in FPGA
	- fix markers and reduce CPU load when using markers with fast traces
- New features:
	- dwell time configurable in acquisition toolbar
	- PLL settling delay in device configuration
	- device configuration persistent across power cycles
 2025-01-03 14:36:10 +01:00
Jan Käberich 24314e2361 WIP: rework 2.LO + add dwell time 2025-01-02 19:16:53 +01:00
Jan Käberich 21eb612601 improve MCP33131 sample timing 2024-02-26 15:37:07 +01:00
Jan Käberich 1a1c9fd345 disable source if not used in active stage 2022-11-07 00:46:54 +01:00
Jan Käberich 73e26a25c4 WIP: synchronization 2022-08-08 18:08:40 +02:00
Jan Käberich 58918f81c1 WIP: device synchronization 2022-08-07 03:01:22 +02:00
Jan Käberich 43b588c2f6 Fix generator output spikes 
- Add manual overwrite in FPGA for hardware that is usually handled by sweep control
- Use static hardware configuration for generator (no sweep active anymore)
 2022-06-23 17:51:15 +02:00
Jan Käberich 37d8474260 Added stages to FPGA protocol 2022-04-01 23:01:22 +02:00
Jan Käberich 914468dbb2 rename clk160 -> clk_pll 2021-11-19 21:18:54 +01:00
Jan Käberich 8b9b8265b9 Use full multiplier bitwidth for windowing + increased number of DFT bins 2020-11-08 14:38:31 +01:00
Jan Käberich ce475fa042 Basic DFT spectrum analysis working 2020-11-08 14:38:31 +01:00
Jan Käberich f889ec854b Test of DFT implementation in FPGA 2020-11-08 14:38:31 +01:00
Jan Käberich 926392e5b9 Bugfixes and speed improvements 2020-09-26 23:34:31 +02:00
Jan Käberich fc3ce7a828 Improved spectrum analyzer mode 
- Faster sweeps by changing 2.LO only when necessary and using 400kHz I2C frequency
- Added FPGA settings for selectable ADC samplerate
- Additional measurement with different ADC samplerate when signal ID is on to remove ADC images
 2020-09-17 19:54:03 +02:00
Jan Käberich d9d00b8c71 Windowing option added to sampling 2020-09-16 16:13:06 +02:00
Jan Käberich 4cbd60e62d Bugfixes and improvements for new hardware 2020-09-14 23:13:32 +02:00
Jan Käberich 7d9d5e27eb different settling time/samples per point in sweep 2020-09-14 11:03:37 +02:00
Jan Käberich 16f050a11e FPGA project adapted to new pinout 2020-08-30 16:19:18 +02:00