jankae/LibreVNA
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1055 commits 11 branches 20 tags 314 MiB
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15 commits

Author SHA1 Message Date
Jan Käberich 24314e2361 WIP: rework 2.LO + add dwell time 2025-01-02 19:16:53 +01:00
Jan Käberich 1a1c9fd345 disable source if not used in active stage 2022-11-07 00:46:54 +01:00
Jan Käberich c05d248f83 interrupt safe USB send function 2022-08-21 22:20:59 +02:00
Jan Käberich 73e26a25c4 WIP: synchronization 2022-08-08 18:08:40 +02:00
Jan Käberich 7b3aa6e158 WIP: synchronization 2022-08-07 13:28:31 +02:00
Jan Käberich 58918f81c1 WIP: device synchronization 2022-08-07 03:01:22 +02:00
Jan Käberich 37d8474260 Added stages to FPGA protocol 2022-04-01 23:01:22 +02:00
Jan Käberich 7bc18881a5 Allow different source PLL power per sweep point, add power range to sweep 2021-07-09 22:25:54 +02:00
Jan Käberich ce475fa042 Basic DFT spectrum analysis working 2020-11-08 14:38:31 +01:00
Jan Käberich f889ec854b Test of DFT implementation in FPGA 2020-11-08 14:38:31 +01:00
Jan Käberich 2157b3f3c4 Improved USB throughput, stimulus power up to 0dbm, fine tuning of dynamic range 2020-09-29 23:03:20 +02:00
Jan Käberich 926392e5b9 Bugfixes and speed improvements 2020-09-26 23:34:31 +02:00
Jan Käberich de8761545d Experimental feature: only excite one port when other traces are paused 2020-09-15 23:22:08 +02:00
Jan Käberich 7d9d5e27eb different settling time/samples per point in sweep 2020-09-14 11:03:37 +02:00
Jan Käberich 16f050a11e FPGA project adapted to new pinout 2020-08-30 16:19:18 +02:00