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1088 commits 11 branches 20 tags 313 MiB
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67 commits

Author SHA1 Message Date
Jan Käberich 38b4a6ba39 Bugfix: correct PLL configuration at the band switch frequency (25 MHz) 2025-08-09 19:11:32 +02:00
Jan Käberich abe2aefcf9 use PLL A to generate lowband source 2025-08-09 19:10:53 +02:00
Jan Käberich 199bb7bbd7 improve GUI synchronization for compound device 2025-05-04 13:01:00 +02:00
Jan Käberich 4f63a28b61 force PLL turn on when assembling device status in VNA mode 2025-04-23 16:18:26 +02:00
Jan Käberich 1fb1c85208 Increase USB buffer timeout in VNA sweep 2025-03-13 10:02:36 +01:00
Jan Käberich a39b9465a6 fix intermittent source generation problem 2025-03-05 09:34:41 +01:00
Jan Käberich b133728f1d switch PLL reference to avoid integer spurs 2025-03-03 15:42:14 +01:00
Jan Käberich 72e2a331da WIP: detect integer spurs 2025-02-26 08:55:31 +01:00
Jan Käberich a4faeb28b0 Working dwell time feature 
- Bugfixes:
	- improve SPI timing in FPGA
	- fix markers and reduce CPU load when using markers with fast traces
- New features:
	- dwell time configurable in acquisition toolbar
	- PLL settling delay in device configuration
	- device configuration persistent across power cycles
 2025-01-03 14:36:10 +01:00
Jan Käberich 24314e2361 WIP: rework 2.LO + add dwell time 2025-01-02 19:16:53 +01:00
Jan Käberich 5136418e26 use frequency calibration when shifting 2.LO 2024-02-09 17:20:18 +01:00
Jan Käberich 1c09b8e1cb Clear old VNA data when starting new sweep 2023-07-30 13:08:27 +02:00
Jan Käberich 9b4865dceb Renaming packet types, implementing different packet contents per hardware version 2023-02-20 13:08:31 +01:00
Andre Dunford cc8256b4cc commit missed changes to VNA.cpp 2022-12-20 11:42:11 -08:00
Andre Dunford 5bb6fdf686 Revert "evaluate AUX3 in standby state" 
This reverts commit ec5e0e208c.
 2022-12-20 09:11:13 -08:00
Andre Dunford ec5e0e208c evaluate AUX3 in standby state 2022-12-20 01:16:22 -08:00
Andre Dunford 08fa3fa0a0 implement sweep standby configuration 2022-12-16 23:41:59 -08:00
Andre Dunford 9b38a1fc3d implement optional device status updates 2022-12-05 22:29:33 -08:00
Jan Käberich ec6fae5822 Remove IFTable limitation, calculate 2.LO shift on the fly 2022-11-20 01:19:42 +01:00
Jan Käberich df8fa25935 Increase settling time for PLLs 2022-11-19 16:26:38 +01:00
Jan Käberich a4b1978098 wait for lock on Si5351C 2022-11-17 12:05:52 +01:00
Jan Käberich 73e26a25c4 WIP: synchronization 2022-08-08 18:08:40 +02:00
Jan Käberich 58918f81c1 WIP: device synchronization 2022-08-07 03:01:22 +02:00
Jan Käberich 047f6ce981 more flexible USB protocol for VNA settings/measurements 2022-08-06 16:22:12 +02:00
Jan Käberich 947a6b9d83 Fix further sweep timeout issues 2022-06-26 18:47:34 +02:00
Jan Käberich 6393ae7fc3 WIP: preparation for zero span mode 2022-06-20 01:02:09 +02:00
Jan Käberich 0cecaf72e5 Prevent higher frequency output spike when sweep starts at DC 2022-06-06 17:28:03 +02:00
Jan Käberich c6ef075f4f split device info and status protocol messages 2022-04-03 20:26:30 +02:00
Jan Käberich 37d8474260 Added stages to FPGA protocol 2022-04-01 23:01:22 +02:00
Jan Käberich c85d8e8e1f Update to STM32CubeIDE + longer settling time for point 0 2022-03-07 22:51:17 +01:00
Jan Käberich 5d8efd4336 user selectable IF frequencies 2022-01-15 16:11:33 +01:00
Jan Käberich 48d00ec172 increase frequency calculation for log sweep 2022-01-05 21:40:51 +01:00
Jan Käberich 6fd2598ae8 Log option for frequency sweep 2022-01-05 16:01:51 +01:00
Jan Käberich e0c9f4dcee Fix fractional calculation for frequencies close to integer multiples 2021-11-13 19:32:58 +01:00
Jan Käberich 0452d2472c Improve behaviour on full USB buffer 2021-09-24 22:21:38 +02:00
Jan Käberich 220fa208e9 output amplitude unlevel check in VNA mode 2021-08-13 21:44:12 +02:00
Jan Käberich 67489084e9 basic working power sweep 2021-07-09 22:26:44 +02:00
Jan Käberich 7bc18881a5 Allow different source PLL power per sweep point, add power range to sweep 2021-07-09 22:25:54 +02:00
Jan Käberich 938f444c73 TCXO offset calibration 2021-05-01 18:34:53 +02:00
Jan Käberich 51806b936c Halt sweep when USB buffer full 2021-01-09 21:21:47 +01:00
Jan Käberich 49e0b901fd Optional harmonic mixing 2020-12-18 15:03:01 +01:00
Jan Käberich 00f0de43f2 Timeout handling in FPGA communication (better recovery from missing reference) 2020-12-15 18:03:29 +01:00
Jan Käberich d63640d437 Cleanup of not needed code 2020-11-24 18:06:57 +01:00
Jan Käberich ef97d54913 detect missing points + minor USB speedup 2020-11-24 16:28:57 +01:00
Jan Käberich 5b771e2a86 Tracking generator with offset + incomplete automatic source/receiver calibration 2020-11-18 19:19:29 +01:00
Jan Käberich 3055564a27 signal ID improved 2020-11-14 23:53:55 +01:00
Jan Käberich a2389fca13 Protocol adjustment + exposing settings for DFT 2020-11-08 14:38:31 +01:00
Jan Käberich ce475fa042 Basic DFT spectrum analysis working 2020-11-08 14:38:31 +01:00
Jan Käberich f889ec854b Test of DFT implementation in FPGA 2020-11-08 14:38:31 +01:00
Jan Käberich d0640e0e42 Change ADC samplerate for points at which LO feedthrough would alias 2020-10-30 19:23:34 +01:00