jankae/LibreVNA
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1013 commits 11 branches 21 tags 314 MiB
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9 commits

Author SHA1 Message Date
Jan Käberich
705661e322 padding always adds resolution 2025-02-21 15:59:26 +01:00
Jan Käberich
a4faeb28b0 Working dwell time feature 
- Bugfixes:
	- improve SPI timing in FPGA
	- fix markers and reduce CPU load when using markers with fast traces
- New features:
	- dwell time configurable in acquisition toolbar
	- PLL settling delay in device configuration
	- device configuration persistent across power cycles
 2025-01-03 14:36:10 +01:00
Jan Käberich
70ac53aa75 add mutex for trace data (fixes DFT/TDR thread crashes) 2024-12-17 10:48:52 +01:00
Jan Käberich
acb79fa3bc WIP: TDR/DFT improvements 2024-12-16 22:21:33 +01:00
Jan Käberich
f2df7ad3f0 Shift TDR output from positive times only to centered around zero 2024-07-10 10:05:25 +02:00
Jan Käberich
2ba954537b Add SCPI command to read/write the preferences 2024-06-20 14:40:06 +02:00
Jan Käberich
792a6a4974 continuous updates for TDR/DFT with optional rate limit 2024-05-08 20:00:15 +02:00
Jan Käberich
b9b501bd00 Improve display of eye diagram 2022-10-21 19:50:06 +02:00
Jan Käberich
8d66770acf Move project, add simple test 2022-10-01 17:10:44 +02:00