Move CDS phase computation from per-point config storage to FPGA logic.
The FPGA now computes the 180° phase shift internally (M/2) and loops
twice per point when CDS is enabled. This keeps config memory at 96 bits
instead of 112, avoiding BRAM overflow on the Spartan 6.
FPGA changes:
- Add CDS_ENABLED input to Sweep module (controlled via SPI register 6)
- Compute source_phase = M/2 for 180° shift when cds_phase=1
- State machine loops through all stages twice per point when CDS enabled
- RESULT_INDEX now includes cds_phase bit: stage[2:0] & point[11:0] & cds_phase
Firmware changes:
- Add FPGA::SetCDSEnabled() to control CDS via register 6 bit 11
- Update SamplingResult to include cdsPhase field (1 bit)
- Simplify VNA.cpp: FPGA handles phase switching, MCU combines results
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
Adds ability to set phase adjustment on Source PLL for each sweep point.
When sourcePhase != 0, the FPGA executes a CDM toggle sequence after
normal PLL register load to apply the specified phase offset.
Changes:
- MAX2871.vhd: add PHASE_ADJUST input and CDM toggle state machine
- Sweep.vhd: extract phase from config, generate phase adjust signal
- SPIConfig.vhd: handle 112-bit config data (was 96-bit)
- top.vhd: wire phase adjustment signals, widen data buses
- SweepConfigMem.xco: update BRAM width to 112 bits
- FPGA.cpp/hpp: add sourcePhase parameter to WriteSweepConfig
Phase formula: phase_degrees = (sourcePhase / M) * 360
For 180° shift: sourcePhase = M/2
Note: SweepConfigMem IP core must be regenerated before FPGA build.
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
- Bugfixes:
- improve SPI timing in FPGA
- fix markers and reduce CPU load when using markers with fast traces
- New features:
- dwell time configurable in acquisition toolbar
- PLL settling delay in device configuration
- device configuration persistent across power cycles
- Add manual overwrite in FPGA for hardware that is usually handled by sweep control
- Use static hardware configuration for generator (no sweep active anymore)
- Faster sweeps by changing 2.LO only when necessary and using 400kHz I2C frequency
- Added FPGA settings for selectable ADC samplerate
- Additional measurement with different ADC samplerate when signal ID is on to remove ADC images
