142 commits

Author	SHA1	Message	Date
Roger Henderson	1ea012aa57	implement FPGA-based CDS to avoid BRAM overflow ... Move CDS phase computation from per-point config storage to FPGA logic. The FPGA now computes the 180° phase shift internally (M/2) and loops twice per point when CDS is enabled. This keeps config memory at 96 bits instead of 112, avoiding BRAM overflow on the Spartan 6. FPGA changes: - Add CDS_ENABLED input to Sweep module (controlled via SPI register 6) - Compute source_phase = M/2 for 180° shift when cds_phase=1 - State machine loops through all stages twice per point when CDS enabled - RESULT_INDEX now includes cds_phase bit: stage[2:0] & point[11:0] & cds_phase Firmware changes: - Add FPGA::SetCDSEnabled() to control CDS via register 6 bit 11 - Update SamplingResult to include cdsPhase field (1 bit) - Simplify VNA.cpp: FPGA handles phase switching, MCU combines results Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>	2026-02-01 21:19:57 +13:00
Roger Henderson	0b571688a9	add Correlated Double Sampling (CDS) support ... Implements CDS to reduce noise by taking multiple measurements at different source PLL phase offsets and combining with cosine weighting. Firmware changes (VNA.cpp, Protocol.hpp): - Add cdsPhases field to SweepSettings (0=disabled, 2-7=phase count) - Configure N internal sweep points per user point with phase offsets - Accumulate weighted samples: result = Σ(sample[k] × cos(2π×k/N)) - Per-stage accumulators for multi-stage measurements PC application changes: - Add "CDS" checkbox to VNA acquisition toolbar - When enabled, sets cdsPhases=2 for 180° differential measurement - Tooltip explains the feature With 180° CDS (2 samples): - Sample at 0°: weight = cos(0°) = 1 - Sample at 180°: weight = cos(180°) = -1 - Combined result = Sample₀ - Sample₁₈₀ Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>	2026-01-31 23:47:02 +13:00
Roger Henderson	6c06293179	add per-point source PLL phase adjustment support ... Adds ability to set phase adjustment on Source PLL for each sweep point. When sourcePhase != 0, the FPGA executes a CDM toggle sequence after normal PLL register load to apply the specified phase offset. Changes: - MAX2871.vhd: add PHASE_ADJUST input and CDM toggle state machine - Sweep.vhd: extract phase from config, generate phase adjust signal - SPIConfig.vhd: handle 112-bit config data (was 96-bit) - top.vhd: wire phase adjustment signals, widen data buses - SweepConfigMem.xco: update BRAM width to 112 bits - FPGA.cpp/hpp: add sourcePhase parameter to WriteSweepConfig Phase formula: phase_degrees = (sourcePhase / M) * 360 For 180° shift: sourcePhase = M/2 Note: SweepConfigMem IP core must be regenerated before FPGA build. Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>	2026-01-31 16:57:10 +13:00
Jan Käberich	64791e6d4e	option to restore default values of device configuration	2025-11-15 19:22:15 +01:00
Jan Käberich	be123420db	Configuration for hardware version 0xD0	2025-10-28 12:08:13 +01:00
Jan Käberich	273dfa8037	add support for hardware version 0xD0 device status	2025-10-24 12:55:09 +02:00
Jan Käberich	6e2079fcfb	menu entry to run internal alignment if supported by hardware version	2025-10-23 12:57:49 +02:00
Jan Käberich	ed699cfd6a	hide device specific actions based on the hardware version	2025-10-23 10:16:33 +02:00
Jan Käberich	f51c6a0bce	Manual control dialog for prototype 0xD0	2025-10-15 10:23:08 +02:00
Jan Käberich	5947584e63	manual control dialog for experimental hardware version 0xE0	2025-08-31 18:49:38 +02:00
Jan Käberich	f0c7f289cb	Bugfix: remove not used optional parameter	2025-08-17 20:18:38 +02:00
Jan Käberich	8b44421ea3	improve PLL fractional divider algorithm	2025-08-17 19:37:10 +02:00
Jan Käberich	38b4a6ba39	Bugfix: correct PLL configuration at the band switch frequency (25 MHz)	2025-08-09 19:11:32 +02:00
Jan Käberich	abe2aefcf9	use PLL A to generate lowband source	2025-08-09 19:10:53 +02:00
Jan Käberich	162309e54a	1us delay after CS high on SPI flash	2025-05-31 14:59:14 +02:00
Jan Käberich	199bb7bbd7	improve GUI synchronization for compound device	2025-05-04 13:01:00 +02:00
Jan Käberich	4f63a28b61	force PLL turn on when assembling device status in VNA mode	2025-04-23 16:18:26 +02:00
Jan Käberich	1fb1c85208	Increase USB buffer timeout in VNA sweep	2025-03-13 10:02:36 +01:00
Jan Käberich	a39b9465a6	fix intermittent source generation problem	2025-03-05 09:34:41 +01:00
Jan Käberich	b133728f1d	switch PLL reference to avoid integer spurs	2025-03-03 15:42:14 +01:00
Jan Käberich	72e2a331da	WIP: detect integer spurs	2025-02-26 08:55:31 +01:00
Jan Käberich	ca25969574	Startup and communication bugfixes ... - reduce amount of mode switched when starting and loading setups - improve logging for errors during HIL tests - fix small USB communication bugs	2025-01-06 17:34:46 +01:00
Jan Käberich	b77ba278de	Improve spectrum analyzer ... - revert LO2 shift mechanism (restores previous SA speed) - allow tracking generator to reach all(?) frequencies with sufficient accuracy	2025-01-04 16:52:32 +01:00
Jan Käberich	a4faeb28b0	Working dwell time feature ... - Bugfixes: - improve SPI timing in FPGA - fix markers and reduce CPU load when using markers with fast traces - New features: - dwell time configurable in acquisition toolbar - PLL settling delay in device configuration - device configuration persistent across power cycles	2025-01-03 14:36:10 +01:00
Jan Käberich	24314e2361	WIP: rework 2.LO + add dwell time	2025-01-02 19:16:53 +01:00
Jan Käberich	0fc6c912fc	Stop sweep after reset, fix failing tests	2024-04-22 15:08:10 +02:00
Jan Käberich	5136418e26	use frequency calibration when shifting 2.LO	2024-02-09 17:20:18 +01:00
Jan Käberich	11612e44d5	added dialogs for hardware version 0xFE	2023-11-07 14:26:31 +01:00
Jan Käberich	5a78091f2b	Merge branch 'master' of github.com:jankae/LibreVNA	2023-09-05 11:13:13 +02:00
Jan Käberich	70a0079f92	Fix missing device log if USB connection is not established at power up	2023-09-05 11:13:05 +02:00
Jan Käberich	1c09b8e1cb	Clear old VNA data when starting new sweep	2023-07-30 13:08:27 +02:00
Jan Käberich	727040c132	Update to new VID/PID from pidcodes	2023-04-17 23:38:24 +02:00
Jan Käberich	99c6d77ad8	Device protocol update: support device with up to 4 ports	2023-02-23 23:04:50 +01:00
Jan Käberich	a0c45d3c56	VFF device config update	2023-02-23 15:14:49 +01:00
Jan Käberich	9b4865dceb	Renaming packet types, implementing different packet contents per hardware version	2023-02-20 13:08:31 +01:00
Andre Dunford	cc8256b4cc	commit missed changes to VNA.cpp	2022-12-20 11:42:11 -08:00
Andre Dunford	916d6e3e38	refactor evaluation of standby waiting state	2022-12-20 11:14:02 -08:00
Andre Dunford	5bb6fdf686	Revert "evaluate AUX3 in standby state" ... This reverts commit ec5e0e208c.	2022-12-20 09:11:13 -08:00
Andre Dunford	ec5e0e208c	evaluate AUX3 in standby state	2022-12-20 01:16:22 -08:00
Andre Dunford	fc8eee58e7	relocate standby condition	2022-12-18 16:54:47 -08:00
Andre Dunford	795b1eb3fa	respond to InitiateSweep with nack when misconfigured	2022-12-17 01:19:46 -08:00
Andre Dunford	08fa3fa0a0	implement sweep standby configuration	2022-12-16 23:41:59 -08:00
Andre Dunford	9b38a1fc3d	implement optional device status updates	2022-12-05 22:29:33 -08:00
Andre Dunford	5bf824220e	replace USB protocol literals with named constants	2022-11-29 00:44:27 -08:00
Jan Käberich	0c17288ece	SA/GEN integration tests + bugfixes	2022-11-20 20:48:36 +01:00
Jan Käberich	ec6fae5822	Remove IFTable limitation, calculate 2.LO shift on the fly	2022-11-20 01:19:42 +01:00
Jan Käberich	df8fa25935	Increase settling time for PLLs	2022-11-19 16:26:38 +01:00
Jan Käberich	6e5f2635d1	Hardfault handler + FPGA abort/interrupt collision fix	2022-11-19 15:46:17 +01:00
Jan Käberich	a4b1978098	wait for lock on Si5351C	2022-11-17 12:05:52 +01:00
Jan Käberich	22542a81b6	attempt to restart USB communication	2022-10-31 22:14:59 +01:00