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simplified modulation with lookup table, updated documentation

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Jan Käberich 2022-06-10 23:10:53 +02:00
parent 0394b52da0
commit f9049056e2
12 changed files with 25861 additions and 434 deletions
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Documentation/DeveloperInfo/FPGA_protocol_Generator.pdf
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163
Documentation/DeveloperInfo/FPGA_protocol_Generator.tex
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@ -121,28 +121,60 @@ Writing a register requires the transfer of two words: First the control word se
\rwbits{0}{16}{Register Value} \rwbits{0}{16}{Register Value}
\end{tikzpicture} \end{tikzpicture}
\end{center} \end{center}
\subsection{Writing the VCO lookup table}
The MAX2871 contains 64 individual VCOs. The correct VCO has to be selected for each frequency. During modulation, the FPGA performs the VCO selection and needs to know the frequency limits for each VCO. It contains a lookup table with a 16-bit entry for each VCO. This table has to be filled before enabling the modulation, as each MAX2871 sample has slightly different VCO limits (see MAX2871 datasheet for algorithm to determine the limits). \subsection{Writing to the modulation lookup table}
Updating a table entry is done by sending two SPI words: The source registers and the attenuator setting are taken from a lookup table while the modulation is active. There is one entry for every possible value of the sample (256 entries). All used entries must have been written to before the modulation is started.
Initiate the write by sending the command word:
\begin{center} \begin{center}
\begin{tikzpicture} \begin{tikzpicture}
\bitrect{16}{16-\bit} \bitrect{16}{16-\bit}
\rwbits{0}{1}{0} \rwbits{0}{1}{0}
\rwbits{1}{1}{0} \rwbits{1}{1}{0}
\rwbits{2}{1}{0} \rwbits{2}{1}{0}
\robits{3}{7}{reserved} \robits{3}{5}{reserved}
\rwbits{10}{6}{VCO index} \rwbits{8}{8}{Table index}
\end{tikzpicture}
\end{center}
While keeping NSS low, send the lookup table data after the control word. The data is only written to the table, when all 9 words have been received. The data is transmitted MSB first.
\begin{center}
\begin{tikzpicture}
\bitrect{16}{144-\bit}
\robits{0}{9}{reserved}
\rwbits{9}{7}{Attenuator}
\end{tikzpicture}
\begin{tikzpicture}
\bitrect{16}{128-\bit}
\rwbits{0}{16}{MAX2871 Register 4[31:16]}
\end{tikzpicture}
\begin{tikzpicture}
\bitrect{16}{112-\bit}
\rwbits{0}{16}{MAX2871 Register 4[15:0]}
\end{tikzpicture}
\begin{tikzpicture}
\bitrect{16}{96-\bit}
\rwbits{0}{16}{MAX2871 Register 3[31:16]}
\end{tikzpicture}
\begin{tikzpicture}
\bitrect{16}{80-\bit}
\rwbits{0}{16}{MAX2871 Register 3[15:0]}
\end{tikzpicture}
\begin{tikzpicture}
\bitrect{16}{64-\bit}
\rwbits{0}{16}{MAX2871 Register 1[31:16]}
\end{tikzpicture}
\begin{tikzpicture}
\bitrect{16}{48-\bit}
\rwbits{0}{16}{MAX2871 Register 1[15:0]}
\end{tikzpicture}
\begin{tikzpicture}
\bitrect{16}{32-\bit}
\rwbits{0}{16}{MAX2871 Register 0[31:16]}
\end{tikzpicture} \end{tikzpicture}
\begin{tikzpicture} \begin{tikzpicture}
\bitrect{16}{16-\bit} \bitrect{16}{16-\bit}
\rwbits{0}{16}{Maximum VCO frequency[15:0]} \rwbits{0}{16}{MAX2871 Register 0[15:0]}
\end{tikzpicture} \end{tikzpicture}
\end{center} \end{center}
The maximum VCO frequency is given in terms of the MAX2871 reference frequency. It is a Q10 fixed point integer.
$$
Maximum VCO frequency[15:0] = \frac{f_{max} * 1024}{f_{reference}}
$$
Example: With a reference frequency $f_{reference} = 104 MHz$ and a maximum usable frequency of the VCO of $f_{max} = 3718 MHz$, set the maximum VCO frequency value to 36608.
\subsection{Modulation FIFO handling} \subsection{Modulation FIFO handling}
\label{mod:fifo} \label{mod:fifo}
@ -196,12 +228,13 @@ FIFO sample 1 is added to the FIFO first, followed by FIFO sample 2.
\item \textbf{SUIE:} Source unlocked interrupt enable \item \textbf{SUIE:} Source unlocked interrupt enable
\end{itemize} \end{itemize}
\subsection{Source Control Register: 0x01} \subsection{Control Register: 0x01}
\begin{center} \begin{center}
\begin{tikzpicture} \begin{tikzpicture}
\bitrect{16}{16-\bit} \bitrect{16}{16-\bit}
\rwbits{0}{2}{SourceFilter} \rwbits{0}{2}{SourceFilter}
\rwbits{2}{2}{PWR} \robits{2}{1}{res}
\rwbits{3}{1}{EN}
\rwbits{4}{7}{Attenuation} \rwbits{4}{7}{Attenuation}
\rwbits{11}{1}{BS} \rwbits{11}{1}{BS}
\rwbits{12}{1}{PS} \rwbits{12}{1}{PS}
@ -222,18 +255,8 @@ Setting & Selected Band\\
11 & \SIrange{3500}{6000}{\mega\hertz}\\ 11 & \SIrange{3500}{6000}{\mega\hertz}\\
\end{tabular} \end{tabular}
\end{center} \end{center}
\item \textbf{PWR:} Power setting of source PLL. Will be written to register 4, bits [4:3] of the source PLL, controlling the output power of output A. \item \textbf{EN: Enable modulation.} Set to 1 to enable the modulation. For the modulation to actually start, AUX3 also has to be pulled low. Set to 0 to disable the modulation (when changing settings or to clear the modulation FIFO).
\begin{center} \item \textbf{Attenuator:} Attenuation of source signal in \SI{0.25}{\decibel} (when modulation is disabled).
\begin{tabular}{ c|c }
Setting & Selected Power\\
\hline
00 & \SI{-4}{\dBm}\\
01 & \SI{-1}{\dBm}\\
10 & \SI{2}{\dBm}\\
11 & \SI{5}{\dBm}\\
\end{tabular}
\end{center}
\item \textbf{Attenuator:} Attenuation of source signal in \SI{0.25}{\decibel}.
\item \textbf{BS: Band select.} Set to 0 for highband, set to 1 for lowband. \item \textbf{BS: Band select.} Set to 0 for highband, set to 1 for lowband.
\item \textbf{PS: Port select.} Set to 0 for Port 1, set to 1 for Port 2. \item \textbf{PS: Port select.} Set to 0 for Port 1, set to 1 for Port 2.
\item \textbf{CE: Source chip enable.} \item \textbf{CE: Source chip enable.}
@ -241,14 +264,13 @@ Setting & Selected Power\\
\item \textbf{ASHD: Amplifier disable.} \item \textbf{ASHD: Amplifier disable.}
\end{itemize} \end{itemize}
\subsection{Modulation control register: 0x02} \subsection{LED control register: 0x02}
\begin{center} \begin{center}
\begin{tikzpicture} \begin{tikzpicture}
\bitrect{16}{16-\bit} \bitrect{16}{16-\bit}
\rwbits{0}{3}{LEDS[2:0]} \rwbits{0}{3}{LEDS[2:0]}
\robits{3}{5}{reserved} \robits{3}{13}{reserved}
\rwbits{8}{7}{MOD\_AM\_DEPTH[6:0]}
\rwbits{15}{1}{EN}
\end{tikzpicture} \end{tikzpicture}
\end{center} \end{center}
\begin{itemize} \begin{itemize}
@ -262,8 +284,6 @@ LED num & Function\\
2 & Ext. reference\\ 2 & Ext. reference\\
\end{tabular} \end{tabular}
\end{center} \end{center}
\item \textbf{MOD\_AM\_DEPTH:} Depth of amplitude modulation. Higher values of the modulation sample result in deeper modulation. This setting determines the maximum depth. 127 is equivalent to 100\% modulation.
\item \textbf{EN: Enable modulation.} Set to 1 to enable the modulation. For the modulation to actually start, AUX3 also has to be pulled low. Set to 0 to disable the modulation (when changing settings or to clear the modulation FIFO).
\end{itemize} \end{itemize}
\subsection{Modulation phase increment register: 0x03} \subsection{Modulation phase increment register: 0x03}
@ -280,86 +300,7 @@ f_{sample} = \frac{102.4 MHz * MOD\_PHASE\_INC}{2^{27}}
$$ $$
Example: set to 26214 for a sample rate of approximately 20 kHz. Example: set to 26214 for a sample rate of approximately 20 kHz.
\subsection{Modulation center frequency LSB register: 0x04} \subsection{Modulation FIFO threshold register: 0x04}
\label{reg:mod:center:lsb}
\begin{center}
\begin{tikzpicture}
\bitrect{16}{16-\bit}
\rwbits{0}{16}{MOD\_CENTER\_FREQ[15:0]}
\end{tikzpicture}
\end{center}
\begin{itemize}
\item \textbf{MOD\_CENTER\_FREQ[32:0]:} See also other registers for remaining bits (sections~\ref{reg:mod:center:msb} and \ref{reg:mod:dev:msb}). Sets the center frequency of the frequency modulation. It is given in terms of the MAX2871 reference frequency. It is a Q27 fixed point integer.
$$
MOD\_CENTER\_FREQ[32:0] = \frac{f_{center} * 2^{27}}{f_{reference}}
$$
\end{itemize}
\subsection{Modulation center frequency MSB register: 0x05}
\label{reg:mod:center:msb}
\begin{center}
\begin{tikzpicture}
\bitrect{16}{16-\bit}
\rwbits{0}{16}{MOD\_CENTER\_FREQ[31:16]}
\end{tikzpicture}
\end{center}
\subsection{Modulation deviation frequency LSB register: 0x06}
\label{reg:mod:dev:lsb}
\begin{center}
\begin{tikzpicture}
\bitrect{16}{16-\bit}
\rwbits{0}{16}{MOD\_DEVIATION\_FREQ[15:0]}
\end{tikzpicture}
\end{center}
\begin{itemize}
\item \textbf{MOD\_DEVIATION\_FREQ[25:0]:} See also other register for remaining bits (section~\ref{reg:mod:dev:msb}). Sets the maximum deviation from the center frequency during frequency modulation. It is given in terms of the MAX2871 reference frequency. It is a Q27 fixed point integer. As it only has 26 bits, the maximum deviation is half the reference frequency.
$$
MOD\_DEVIATION\_FREQ[25:0] = \frac{f_{max_deviation} * 2^{27}}{f_{reference}}
$$
\end{itemize}
\subsection{Modulation deviation frequency MSB register: 0x07}
\label{reg:mod:dev:msb}
\begin{center}
\begin{tikzpicture}
\bitrect{16}{16-\bit}
\rwbits{0}{1}{CF32}
\robits{1}{5}{reserved}
\rwbits{6}{10}{MOD\_DEVIATION\_FREQ[25:16]}
\end{tikzpicture}
\end{center}
\begin{itemize}
\item \textbf{CF32:} Most significant bit of MOD\_CENTER\_FREQ.
\end{itemize}
\subsection{Minimum VCO frequency LSB register: 0x08}
\label{reg:mod:minvco:lsb}
\begin{center}
\begin{tikzpicture}
\bitrect{16}{16-\bit}
\rwbits{0}{16}{MOD\_VCO\_MIN[15:0]}
\end{tikzpicture}
\end{center}
\begin{itemize}
\item \textbf{MOD\_VCO\_MIN[31:0]:} See also other register for remaining bits (section~\ref{reg:mod:minvco:msb}). Sets the minimal allowed undivided VCO frequency. Used to determine the VCO divider when changing frequencies. It is given in terms of the MAX2871 reference frequency. It is a Q27 fixed point integer. Always set this for a minimal undivided VCO frequency of 3 GHz.
$$
MOD\_VCO\_MIN[31:0] = \frac{f_{min_vco} * 2^{27}}{f_{reference}}
$$
\end{itemize}
For the default reference frequency of 104 MHz, set this value to 3871665231.
\subsection{Minimum VCO frequency MSB register: 0x05}
\label{reg:mod:minvco:msb}
\begin{center}
\begin{tikzpicture}
\bitrect{16}{16-\bit}
\rwbits{0}{16}{MOD\_VCO\_MIN[31:16]}
\end{tikzpicture}
\end{center}
\subsection{Modulation FIFO threshold register: 0x0A}
\label{reg:mod:fifo:thresh} \label{reg:mod:fifo:thresh}
\begin{center} \begin{center}
\begin{tikzpicture} \begin{tikzpicture}

33
FPGA/Generator/Generator.gise
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@ -183,6 +183,8 @@
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<outfile xil_pn:name="ipcore_dir/AMMult.vhd"/> <outfile xil_pn:name="ipcore_dir/AMMult.vhd"/>
<outfile xil_pn:name="ipcore_dir/PLL.vhd"/> <outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
@ -231,6 +233,7 @@
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>
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<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="Test_Generator_beh.prj"/> <outfile xil_pn:name="Test_Generator_beh.prj"/>
@ -258,11 +261,13 @@
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<outfile xil_pn:name="ipcore_dir/AMMult.vhd"/> <outfile xil_pn:name="ipcore_dir/AMMult.vhd"/>
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<outfile xil_pn:name="ipcore_dir/SampleMemory.ngc"/> <outfile xil_pn:name="ipcore_dir/SampleMemory.ngc"/>
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@ -287,13 +292,11 @@
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@ -311,23 +314,19 @@
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@ -338,11 +337,10 @@
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@ -354,11 +352,9 @@
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@ -373,7 +369,6 @@
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@ -384,7 +379,6 @@
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@ -396,7 +390,6 @@
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<status xil_pn:value="InputRemoved"/> <status xil_pn:value="InputRemoved"/>
</transform> </transform>
<transform xil_pn:end_ts="1654687656" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1654687654"> <transform xil_pn:end_ts="1654778429" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1654778427">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="top.twr"/> <outfile xil_pn:name="top.twr"/>
<outfile xil_pn:name="top.twx"/> <outfile xil_pn:name="top.twx"/>

35
FPGA/Generator/Generator.xise
View file

@ -17,26 +17,26 @@
<files> <files>
<file xil_pn:name="top.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/> <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file> </file>
<file xil_pn:name="top.ucf" xil_pn:type="FILE_UCF"> <file xil_pn:name="top.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="MAX2871.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="MAX2871.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/> <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file> </file>
<file xil_pn:name="spi_slave.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="spi_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file> </file>
<file xil_pn:name="SPIConfig.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="SPIConfig.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/> <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file> </file>
<file xil_pn:name="ipcore_dir/PLL.xco" xil_pn:type="FILE_COREGEN"> <file xil_pn:name="ipcore_dir/PLL.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/> <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file> </file>
<file xil_pn:name="Test_MAX2871.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="Test_MAX2871.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@ -58,7 +58,7 @@
</file> </file>
<file xil_pn:name="ResetDelay.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="ResetDelay.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/> <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file> </file>
<file xil_pn:name="Test_SinCos.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="Test_SinCos.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@ -74,7 +74,7 @@
</file> </file>
<file xil_pn:name="Synchronizer.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="Synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file> </file>
<file xil_pn:name="Test_Window.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="Test_Window.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@ -84,11 +84,11 @@
</file> </file>
<file xil_pn:name="RationalApproximation.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="RationalApproximation.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="ipcore_dir/wide_mult.xco" xil_pn:type="FILE_COREGEN"> <file xil_pn:name="ipcore_dir/wide_mult.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="Test_RationalApproximation.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="Test_RationalApproximation.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@ -98,23 +98,23 @@
</file> </file>
<file xil_pn:name="MAX2871_Calc.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="MAX2871_Calc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="ipcore_dir/VCO_Mem.xco" xil_pn:type="FILE_COREGEN"> <file xil_pn:name="ipcore_dir/VCO_Mem.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/> <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file> </file>
<file xil_pn:name="Modulator.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="Modulator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/> <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file> </file>
<file xil_pn:name="ipcore_dir/SampleMemory.xco" xil_pn:type="FILE_COREGEN"> <file xil_pn:name="ipcore_dir/SampleMemory.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file> </file>
<file xil_pn:name="ipcore_dir/AMMult.xco" xil_pn:type="FILE_COREGEN"> <file xil_pn:name="ipcore_dir/AMMult.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="test_modulator.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="test_modulator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@ -128,6 +128,10 @@
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="166"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="166"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="166"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="166"/>
</file> </file>
<file xil_pn:name="ipcore_dir/ModulationMemory.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="171"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="ipcore_dir/PLL.xise" xil_pn:type="FILE_COREGENISE"> <file xil_pn:name="ipcore_dir/PLL.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
@ -143,6 +147,9 @@
<file xil_pn:name="ipcore_dir/AMMult.xise" xil_pn:type="FILE_COREGENISE"> <file xil_pn:name="ipcore_dir/AMMult.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="ipcore_dir/ModulationMemory.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files> </files>
<properties> <properties>

116
FPGA/Generator/Modulator.vhd
View file

@ -48,19 +48,8 @@ entity Modulator is
THRESHOLD_LEVEL : in STD_LOGIC_VECTOR (10 downto 0); THRESHOLD_LEVEL : in STD_LOGIC_VECTOR (10 downto 0);
-- high when the FIFO contains at least THRESHOLD_LEVEL number of samples -- high when the FIFO contains at least THRESHOLD_LEVEL number of samples
THRESHOLD_CROSSED : out STD_LOGIC; THRESHOLD_CROSSED : out STD_LOGIC;
-- center frequency of the FM (in terms of PLL reference frequency, fixed point with 27 digits after decimal point)
FREQ_CENTER : in STD_LOGIC_VECTOR (32 downto 0); OUTPUT_SAMPLE : out STD_LOGIC_VECTOR (7 downto 0);
-- frequency deviation from center at maximum modulation
-- (in terms of PLL reference frequency, fixed point with 27 digits after decimal point -> maximum value ~0.5)
FREQ_DEVIATION : in STD_LOGIC_VECTOR (25 downto 0);
-- attenuator setting for "no modulation"
MIN_ATTENUATION : in STD_LOGIC_VECTOR (6 downto 0);
-- AM depth in percent
AMPLITUDE_DEPTH : in STD_LOGIC_VECTOR (6 downto 0);
-- modulated frequency (in terms of PLL reference frequency, fixed point with 27 digits after decimal point)
FREQUENCY : out STD_LOGIC_VECTOR (32 downto 0);
-- modulated attenuator setting
ATTENUATOR : out STD_LOGIC_VECTOR (6 downto 0);
-- signals that a new output has been generated -- signals that a new output has been generated
NEW_OUTPUT : out STD_LOGIC); NEW_OUTPUT : out STD_LOGIC);
end Modulator; end Modulator;
@ -78,38 +67,6 @@ architecture Behavioral of Modulator is
); );
END COMPONENT; END COMPONENT;
COMPONENT wide_mult
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(26 DOWNTO 0);
ce : IN STD_LOGIC;
p : OUT STD_LOGIC_VECTOR(39 DOWNTO 0)
);
END COMPONENT;
COMPONENT AMMult
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
ce : IN STD_LOGIC;
p : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT;
signal fm_mult_a : STD_LOGIC_VECTOR(12 DOWNTO 0);
signal fm_mult_b : STD_LOGIC_VECTOR(26 DOWNTO 0);
signal fm_mult_p : STD_LOGIC_VECTOR(39 DOWNTO 0);
signal am_mult_a : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal am_mult_b : STD_LOGIC_VECTOR(6 DOWNTO 0);
signal am_mult_p : STD_LOGIC_VECTOR(14 DOWNTO 0);
signal mult_ce : STD_LOGIC;
signal mult_pipe : integer range 0 to 9;
signal write_pos : unsigned(10 downto 0); signal write_pos : unsigned(10 downto 0);
signal read_pos : unsigned(10 downto 0); signal read_pos : unsigned(10 downto 0);
@ -117,24 +74,6 @@ architecture Behavioral of Modulator is
signal clk_sample_cnt : unsigned(26 downto 0); signal clk_sample_cnt : unsigned(26 downto 0);
type AMdepthTable is array(0 to 127) of std_logic_vector(6 downto 0);
impure function InitWindowDataFromFile (RomFileName : in string) return AMdepthTable is
FILE romfile : text is in RomFileName;
variable RomFileLine : line;
variable rom : AMdepthTable;
begin
for i in AMdepthTable'range loop
readline(romfile, RomFileLine);
read(RomFileLine, rom(i));
end loop;
return rom;
end function;
constant AMdepth : AMdepthTable := InitWindowDataFromFile("AMdepth.dat");
signal am_attenuation : unsigned(6 downto 0);
begin begin
Mem : SampleMemory Mem : SampleMemory
PORT MAP ( PORT MAP (
@ -146,27 +85,6 @@ begin
addrb => std_logic_vector(read_pos), addrb => std_logic_vector(read_pos),
doutb => sample doutb => sample
); );
fm_mult_b <= "0" & FREQ_DEVIATION;
am_mult_b <= AMPLITUDE_DEPTH;
FM_Mult: wide_mult
PORT MAP (
clk => CLK,
a => fm_mult_a,
b => fm_mult_b,
ce => mult_ce,
p => fm_mult_p
);
AM_Mult : AMMult
PORT MAP (
clk => CLK,
a => am_mult_a,
b => am_mult_b,
ce => mult_ce,
p => am_mult_p
);
process(CLK, RESET) process(CLK, RESET)
begin begin
@ -178,7 +96,7 @@ begin
UNDERFLOW <= '0'; UNDERFLOW <= '0';
THRESHOLD_CROSSED <= '0'; THRESHOLD_CROSSED <= '0';
clk_sample_cnt <= (others => '0'); clk_sample_cnt <= (others => '0');
mult_pipe <= 0; OUTPUT_SAMPLE <= (others => '0');
else else
-- update threshold -- update threshold
if write_pos - read_pos >= unsigned(THRESHOLD_LEVEL) then if write_pos - read_pos >= unsigned(THRESHOLD_LEVEL) then
@ -206,33 +124,9 @@ begin
else else
read_pos <= read_pos + 1; read_pos <= read_pos + 1;
end if; end if;
mult_pipe <= 9; OUTPUT_SAMPLE <= sample;
mult_ce <= '1';
fm_mult_a <= "00000" & sample;
am_mult_a <= sample;
end if;
if mult_pipe > 0 then
mult_pipe <= mult_pipe - 1;
end if;
if mult_pipe = 4 then
-- multiplier result is ready
mult_ce <= '0';
FREQUENCY <= std_logic_vector(unsigned(FREQ_CENTER) + unsigned(fm_mult_p(33 downto 8)));
am_attenuation <= unsigned(AMdepth(to_integer(unsigned(am_mult_p(14 downto 8)))));
end if;
if mult_pipe = 3 then
am_attenuation <= unsigned(MIN_ATTENUATION) + am_attenuation;
end if;
if mult_pipe = 2 then
if am_attenuation < unsigned(MIN_ATTENUATION) then
-- attenuator overflowed, use maximum values instead
ATTENUATOR <= (others => '1');
else
ATTENUATOR <= std_logic_vector(am_attenuation);
end if;
NEW_OUTPUT <= '1'; NEW_OUTPUT <= '1';
end if; else
if mult_pipe = 1 then
NEW_OUTPUT <= '0'; NEW_OUTPUT <= '0';
end if; end if;
end if; end if;

72
FPGA/Generator/SPIConfig.vhd
View file

@ -37,16 +37,10 @@ entity SPICommands is
MISO : out STD_LOGIC; MISO : out STD_LOGIC;
NSS : in STD_LOGIC; NSS : in STD_LOGIC;
SOURCE_FILTER : out STD_LOGIC_VECTOR(1 downto 0); SOURCE_FILTER : out STD_LOGIC_VECTOR(1 downto 0);
SOURCE_POWER : out STD_LOGIC_VECTOR(1 downto 0);
SOURCE_ATTENUATION : out STD_LOGIC_VECTOR(6 downto 0); SOURCE_ATTENUATION : out STD_LOGIC_VECTOR(6 downto 0);
SOURCE_BANDSELECT : out STD_LOGIC; -- 0: highband, 1: lowband SOURCE_BANDSELECT : out STD_LOGIC; -- 0: highband, 1: lowband
SOURCE_PORTSELECT : out STD_LOGIC; -- 0: Port 1, 1: Port 2 SOURCE_PORTSELECT : out STD_LOGIC; -- 0: Port 1, 1: Port 2
SOURCE_UNLOCKED : in STD_LOGIC; SOURCE_UNLOCKED : in STD_LOGIC;
-- SOURCE VCO lookup table
SOURCE_VCO_INDEX : out STD_LOGIC_VECTOR (5 downto 0);
SOURCE_VCO_MAXFREQ : out STD_LOGIC_VECTOR (15 downto 0);
SOURCE_VCO_WRITE : out STD_LOGIC;
-- Modulation FIFO signals -- Modulation FIFO signals
MOD_FIFO_DATA : out STD_LOGIC_VECTOR (7 downto 0); MOD_FIFO_DATA : out STD_LOGIC_VECTOR (7 downto 0);
@ -56,13 +50,14 @@ entity SPICommands is
MOD_FIFO_THRESHOLD_CROSSED : in STD_LOGIC; MOD_FIFO_THRESHOLD_CROSSED : in STD_LOGIC;
MOD_FIFO_THRESHOLD : out STD_LOGIC_VECTOR (10 downto 0); MOD_FIFO_THRESHOLD : out STD_LOGIC_VECTOR (10 downto 0);
-- Modulation lookup table
MOD_LOOKUP_INDEX : out STD_LOGIC_VECTOR (7 downto 0);
MOD_LOOKUP_DATA : out STD_LOGIC_VECTOR (143 downto 0);
MOD_LOOKUP_WRITE : out STD_LOGIC;
-- Modulation control signals -- Modulation control signals
MOD_ENABLE : out STD_LOGIC; MOD_ENABLE : out STD_LOGIC;
MOD_PHASE_INC : out STD_LOGIC_VECTOR (15 downto 0); MOD_PHASE_INC : out STD_LOGIC_VECTOR (15 downto 0);
MOD_CENTER_FREQ : out STD_LOGIC_VECTOR (32 downto 0);
MOD_DEVIATION_FREQ : out STD_LOGIC_VECTOR (25 downto 0);
MOD_AM_DEPTH : out STD_LOGIC_VECTOR (6 downto 0);
MOD_VCO_MIN : out STD_LOGIC_VECTOR (31 downto 0);
AMP_SHDN : out STD_LOGIC; AMP_SHDN : out STD_LOGIC;
SOURCE_RF_EN : out STD_LOGIC; SOURCE_RF_EN : out STD_LOGIC;
@ -92,13 +87,13 @@ architecture Behavioral of SPICommands is
signal spi_buf_in : std_logic_vector(15 downto 0); signal spi_buf_in : std_logic_vector(15 downto 0);
signal spi_complete : std_logic; signal spi_complete : std_logic;
signal word_cnt : integer range 0 to 19; signal word_cnt : integer range 0 to 19;
type SPI_states is (FirstWord, WriteVCOTable, WriteModulationData, WriteRegister); type SPI_states is (FirstWord, WriteModTable, WriteModulationData, WriteRegister);
signal state : SPI_states; signal state : SPI_states;
signal selected_register : integer range 0 to 31; signal selected_register : integer range 0 to 31;
signal last_NSS : std_logic; signal last_NSS : std_logic;
signal VCO_table_write : std_logic; signal mod_table_write : std_logic;
signal mod_first_byte : std_logic; signal mod_first_byte : std_logic;
signal mod_second_byte : std_logic; signal mod_second_byte : std_logic;
signal mod_data_LSB : std_logic_vector(7 downto 0); signal mod_data_LSB : std_logic_vector(7 downto 0);
@ -107,6 +102,8 @@ architecture Behavioral of SPICommands is
signal interrupt_mask : std_logic_vector(15 downto 0); signal interrupt_mask : std_logic_vector(15 downto 0);
signal interrupt_status : std_logic_vector(15 downto 0); signal interrupt_status : std_logic_vector(15 downto 0);
signal mod_lookup_buffer : std_logic_vector(127 downto 0);
begin begin
SPI: spi_slave SPI: spi_slave
GENERIC MAP(w => 16) GENERIC MAP(w => 16)
@ -122,7 +119,7 @@ begin
); );
MOD_FIFO_WRITE <= mod_first_byte or mod_second_byte; MOD_FIFO_WRITE <= mod_first_byte or mod_second_byte;
SOURCE_VCO_WRITE <= VCO_table_write; MOD_LOOKUP_WRITE <= mod_table_write;
process(CLK, RESET) process(CLK, RESET)
begin begin
@ -138,6 +135,9 @@ begin
INTERRUPT_ASSERTED <= '0'; INTERRUPT_ASSERTED <= '0';
last_NSS <= '1'; last_NSS <= '1';
MOD_ENABLE <= '0'; MOD_ENABLE <= '0';
mod_first_byte <= '0';
mod_second_byte <= '0';
mod_table_write <= '0';
else else
interrupt_status <= "00000000000" & MOD_FIFO_THRESHOLD_CROSSED & MOD_FIFO_UNDERFLOW & MOD_FIFO_OVERFLOW & SOURCE_UNLOCKED & "0"; interrupt_status <= "00000000000" & MOD_FIFO_THRESHOLD_CROSSED & MOD_FIFO_UNDERFLOW & MOD_FIFO_OVERFLOW & SOURCE_UNLOCKED & "0";
if (interrupt_status and interrupt_mask) = "0000000000000000" then if (interrupt_status and interrupt_mask) = "0000000000000000" then
@ -153,8 +153,8 @@ begin
if mod_second_byte = '1' then if mod_second_byte = '1' then
mod_second_byte <= '0'; mod_second_byte <= '0';
end if; end if;
if VCO_table_write = '1' then if mod_table_write = '1' then
VCO_table_write <= '0'; mod_table_write <= '0';
end if; end if;
last_NSS <= NSS; last_NSS <= NSS;
if NSS = '0' and last_NSS = '1' then if NSS = '0' and last_NSS = '1' then
@ -167,9 +167,9 @@ begin
when FirstWord => when FirstWord =>
-- initial word determines action -- initial word determines action
case spi_buf_out(15 downto 13) is case spi_buf_out(15 downto 13) is
when "000" => state <= WriteVCOTable; when "000" => state <= WriteModTable;
-- also extract the point number -- also extract the index
SOURCE_VCO_INDEX <= spi_buf_out(5 downto 0); MOD_LOOKUP_INDEX <= spi_buf_out(7 downto 0);
when "010" => state <= FirstWord; when "010" => state <= FirstWord;
spi_buf_in <= "1111000010100101"; spi_buf_in <= "1111000010100101";
when "100" => state <= WriteRegister; when "100" => state <= WriteRegister;
@ -181,32 +181,28 @@ begin
-- write received data into previously selected register -- write received data into previously selected register
case selected_register is case selected_register is
when 0 => interrupt_mask <= spi_buf_out; when 0 => interrupt_mask <= spi_buf_out;
when 1 => SOURCE_FILTER <= spi_buf_out(1 downto 0); when 1 => SOURCE_FILTER <= spi_buf_out(15 downto 14);
SOURCE_POWER <= spi_buf_out(3 downto 2); MOD_ENABLE <= spi_buf_out(12);
SOURCE_ATTENUATION <= spi_buf_out(10 downto 4); SOURCE_ATTENUATION <= spi_buf_out(11 downto 5);
SOURCE_BANDSELECT <= spi_buf_out(11); SOURCE_BANDSELECT <= spi_buf_out(4);
SOURCE_PORTSELECT <= spi_buf_out(12); SOURCE_PORTSELECT <= spi_buf_out(3);
SOURCE_CE_EN <= spi_buf_out(13); SOURCE_CE_EN <= spi_buf_out(2);
SOURCE_RF_EN <= spi_buf_out(14); SOURCE_RF_EN <= spi_buf_out(1);
AMP_SHDN <= spi_buf_out(15); AMP_SHDN <= spi_buf_out(0);
when 2 => MOD_ENABLE <= spi_buf_out(0); when 2 => MOD_ENABLE <= spi_buf_out(0);
MOD_AM_DEPTH <= spi_buf_out(7 downto 1);
LEDS <= not spi_buf_out(15 downto 13); LEDS <= not spi_buf_out(15 downto 13);
when 3 => MOD_PHASE_INC <= spi_buf_out; when 3 => MOD_PHASE_INC <= spi_buf_out;
when 4 => MOD_CENTER_FREQ(15 downto 0) <= spi_buf_out; when 4 => MOD_FIFO_THRESHOLD <= spi_buf_out(10 downto 0);
when 5 => MOD_CENTER_FREQ(31 downto 16) <= spi_buf_out;
when 6 => MOD_DEVIATION_FREQ(15 downto 0) <= spi_buf_out;
when 7 => MOD_CENTER_FREQ(32) <= spi_buf_out(15);
MOD_DEVIATION_FREQ(25 downto 16) <= spi_buf_out(9 downto 0);
when 8 => MOD_VCO_MIN(15 downto 0) <= spi_buf_out;
when 9 => MOD_VCO_MIN(31 downto 16) <= spi_buf_out;
when 10 => MOD_FIFO_THRESHOLD <= spi_buf_out(10 downto 0);
when others => when others =>
end case; end case;
selected_register <= selected_register + 1; selected_register <= selected_register + 1;
when WriteVCOTable => when WriteModTable =>
SOURCE_VCO_MAXFREQ <= spi_buf_out; if word_cnt = 9 then
VCO_table_write <= '1'; MOD_LOOKUP_DATA <= mod_lookup_buffer & spi_buf_out;
mod_table_write <= '1';
else
mod_lookup_buffer <= mod_lookup_buffer(111 downto 0) & spi_buf_out;
end if;
when WriteModulationData => when WriteModulationData =>
-- add two new bytes to the modulation data -- add two new bytes to the modulation data
MOD_FIFO_DATA <= spi_buf_out(15 downto 8); MOD_FIFO_DATA <= spi_buf_out(15 downto 8);

71
FPGA/Generator/Test_Generator.vhd
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@ -380,11 +380,11 @@ BEGIN
SPI("1111000110000110"); SPI("1111000110000110");
MCU_NSS <= '1'; MCU_NSS <= '1';
-- set AM depth, enable modulation -- enable modulation
wait for CLK_period*10; wait for CLK_period*10;
MCU_NSS <= '0'; MCU_NSS <= '0';
SPI("1000000000000010"); SPI("1000000000000010");
SPI("0000000011111111"); SPI("0000000000000001");
MCU_NSS <= '1'; MCU_NSS <= '1';
-- set 20kHz modulation rate -- set 20kHz modulation rate
@ -394,55 +394,48 @@ BEGIN
SPI(std_logic_vector(to_unsigned(26214, 16))); SPI(std_logic_vector(to_unsigned(26214, 16)));
MCU_NSS <= '1'; MCU_NSS <= '1';
-- set center frequency
wait for CLK_period*10;
MCU_NSS <= '0';
SPI("1000000000000100");
SPI(center_freq(15 downto 0));
MCU_NSS <= '1';
wait for CLK_period*10;
MCU_NSS <= '0';
SPI("1000000000000101");
SPI(center_freq(31 downto 16));
MCU_NSS <= '1';
-- set deviation frequency
wait for CLK_period*10;
MCU_NSS <= '0';
SPI("1000000000000110");
SPI(deviation_freq(15 downto 0));
MCU_NSS <= '1';
wait for CLK_period*10;
MCU_NSS <= '0';
SPI("1000000000000111");
SPI(center_freq(32) & "00000" & center_freq(25 downto 16));
MCU_NSS <= '1';
-- set minimum VCO frequency to 3GHz
wait for CLK_period*10;
MCU_NSS <= '0';
SPI("1000000000001000");
SPI(minimum_vco_freq(15 downto 0));
MCU_NSS <= '1';
wait for CLK_period*10;
MCU_NSS <= '0';
SPI("1000000000001001");
SPI(minimum_vco_freq(31 downto 16));
MCU_NSS <= '1';
-- set FIFO threshold to 100 -- set FIFO threshold to 100
wait for CLK_period*10; wait for CLK_period*10;
MCU_NSS <= '0'; MCU_NSS <= '0';
SPI("1000000000001010"); SPI("1000000000000100");
SPI(std_logic_vector(to_unsigned(100, 16))); SPI(std_logic_vector(to_unsigned(100, 16)));
MCU_NSS <= '1'; MCU_NSS <= '1';
-- setup modulation lookup-table
wait for CLK_period*10;
MCU_NSS <= '0';
SPI("0000000011110000");
SPI("1111000011110000");
SPI("1111000011110000");
SPI("1111000011110000");
SPI("1111000011110000");
SPI("1111000011110000");
SPI("1111000011110000");
SPI("1111000011110000");
SPI("1111000011110000");
SPI("1111000011110000");
MCU_NSS <= '1';
wait for CLK_period*10;
MCU_NSS <= '0';
SPI("0000000001010101");
SPI("0101010101010101");
SPI("0101010101010101");
SPI("0101010101010101");
SPI("0101010101010101");
SPI("0101010101010101");
SPI("0101010101010101");
SPI("0101010101010101");
SPI("0101010101010101");
SPI("0101010101010101");
MCU_NSS <= '1';
wait for CLK_period*10; wait for CLK_period*10;
MCU_NSS <= '0'; MCU_NSS <= '0';
SPI("0010000000000000"); SPI("0010000000000000");
for i in 0 to 63 loop for i in 0 to 63 loop
-- write sample FIFO -- write sample FIFO
wait for CLK_period*10; wait for CLK_period*10;
SPI(std_logic_vector(to_unsigned(i*4, 8)) & std_logic_vector(to_unsigned(i*4+2, 8))); SPI("1111000001010101");
end loop; end loop;
MCU_NSS <= '0'; MCU_NSS <= '0';

108
FPGA/Generator/ipcore_dir/ModulationMemory.xco Normal file
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@ -0,0 +1,108 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Thu Jun 9 11:26:36 2022
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:blk_mem_gen:7.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx9
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=ModulationMemory
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_32bit_address=false
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET interface_type=Native
CSET load_init_file=false
CSET mem_file=no_Mem_file_loaded
CSET memory_type=Simple_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=0
CSET primitive=8kx2
CSET read_width_a=144
CSET read_width_b=144
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_axi_id=false
CSET use_bram_block=Stand_Alone
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=256
CSET write_width_a=144
CSET write_width_b=144
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T16:22:25Z
# END Extra information
GENERATE
# CRC: 5cb737c2

73
FPGA/Generator/ipcore_dir/ModulationMemory.xise Normal file
View file

@ -0,0 +1,73 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="ModulationMemory.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ModulationMemory.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|ModulationMemory|ModulationMemory_a" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="ModulationMemory.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/ModulationMemory" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="ModulationMemory" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2022-06-09T13:27:02" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6041FFA1C63D65A5701CEF820A2F4789" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

25469
FPGA/Generator/netgen/map/top_map.vhd Normal file
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FPGA/Generator/top.bin
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155
FPGA/Generator/top.vhd
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@ -135,22 +135,17 @@ architecture Behavioral of top is
MOD_FIFO_THRESHOLD_CROSSED : IN std_logic; MOD_FIFO_THRESHOLD_CROSSED : IN std_logic;
MISO : OUT std_logic; MISO : OUT std_logic;
SOURCE_FILTER : OUT std_logic_vector(1 downto 0); SOURCE_FILTER : OUT std_logic_vector(1 downto 0);
SOURCE_POWER : out STD_LOGIC_VECTOR(1 downto 0);
SOURCE_ATTENUATION : OUT std_logic_vector(6 downto 0); SOURCE_ATTENUATION : OUT std_logic_vector(6 downto 0);
SOURCE_BANDSELECT : OUT std_logic; SOURCE_BANDSELECT : OUT std_logic;
SOURCE_PORTSELECT : OUT std_logic; SOURCE_PORTSELECT : OUT std_logic;
SOURCE_VCO_INDEX : OUT std_logic_vector(5 downto 0);
SOURCE_VCO_MAXFREQ : OUT std_logic_vector(15 downto 0);
SOURCE_VCO_WRITE : OUT std_logic;
MOD_FIFO_DATA : OUT std_logic_vector(7 downto 0); MOD_FIFO_DATA : OUT std_logic_vector(7 downto 0);
MOD_FIFO_WRITE : OUT std_logic; MOD_FIFO_WRITE : OUT std_logic;
MOD_FIFO_THRESHOLD : OUT std_logic_vector(10 downto 0); MOD_FIFO_THRESHOLD : OUT std_logic_vector(10 downto 0);
MOD_LOOKUP_INDEX : out STD_LOGIC_VECTOR (7 downto 0);
MOD_LOOKUP_DATA : out STD_LOGIC_VECTOR (143 downto 0);
MOD_LOOKUP_WRITE : out STD_LOGIC;
MOD_ENABLE : OUT std_logic; MOD_ENABLE : OUT std_logic;
MOD_PHASE_INC : OUT std_logic_vector(15 downto 0); MOD_PHASE_INC : out STD_LOGIC_VECTOR (15 downto 0);
MOD_CENTER_FREQ : OUT std_logic_vector(32 downto 0);
MOD_DEVIATION_FREQ : OUT std_logic_vector(25 downto 0);
MOD_AM_DEPTH : OUT std_logic_vector(6 downto 0);
MOD_VCO_MIN : out STD_LOGIC_VECTOR (31 downto 0);
AMP_SHDN : OUT std_logic; AMP_SHDN : OUT std_logic;
SOURCE_RF_EN : OUT std_logic; SOURCE_RF_EN : OUT std_logic;
SOURCE_CE_EN : OUT std_logic; SOURCE_CE_EN : OUT std_logic;
@ -169,15 +164,15 @@ architecture Behavioral of top is
); );
END COMPONENT; END COMPONENT;
COMPONENT VCO_Mem COMPONENT ModulationMemory
PORT ( PORT (
clka : IN STD_LOGIC; clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(143 DOWNTO 0);
clkb : IN STD_LOGIC; clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(5 DOWNTO 0); addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) doutb : OUT STD_LOGIC_VECTOR(143 DOWNTO 0)
); );
END COMPONENT; END COMPONENT;
@ -185,42 +180,19 @@ architecture Behavioral of top is
PORT( PORT(
CLK : IN std_logic; CLK : IN std_logic;
RESET : IN std_logic; RESET : IN std_logic;
ACTIVE : in STD_LOGIC; ACTIVE : IN std_logic;
SAMPLE_FREQ_WORD : IN std_logic_vector(15 downto 0); SAMPLE_FREQ_WORD : IN std_logic_vector(15 downto 0);
SAMPLE_DATA : IN std_logic_vector(7 downto 0); SAMPLE_DATA : IN std_logic_vector(7 downto 0);
SAMPLE_LATCH : IN std_logic; SAMPLE_LATCH : IN std_logic;
THRESHOLD_LEVEL : IN std_logic_vector(10 downto 0); THRESHOLD_LEVEL : IN std_logic_vector(10 downto 0);
FREQ_CENTER : IN std_logic_vector(32 downto 0);
FREQ_DEVIATION : IN std_logic_vector(25 downto 0);
MIN_ATTENUATION : IN std_logic_vector(6 downto 0);
AMPLITUDE_DEPTH : IN std_logic_vector(6 downto 0);
OVERFLOW : OUT std_logic; OVERFLOW : OUT std_logic;
UNDERFLOW : OUT std_logic; UNDERFLOW : OUT std_logic;
THRESHOLD_CROSSED : OUT std_logic; THRESHOLD_CROSSED : OUT std_logic;
FREQUENCY : OUT std_logic_vector(32 downto 0); OUTPUT_SAMPLE : OUT std_logic_vector(7 downto 0);
ATTENUATOR : OUT std_logic_vector(6 downto 0);
NEW_OUTPUT : OUT std_logic NEW_OUTPUT : OUT std_logic
); );
END COMPONENT; END COMPONENT;
COMPONENT MAX2871_Calc
PORT(
CLK : IN std_logic;
RESET : IN std_logic;
CALC : IN std_logic;
FREQ : IN std_logic_vector(32 downto 0);
VCO_MIN : IN std_logic_vector(31 downto 0);
POWER : IN std_logic_vector(1 downto 0);
VCO_MAX_FREQ : IN std_logic_vector(15 downto 0);
DONE : OUT std_logic;
REG0 : OUT std_logic_vector(31 downto 0);
REG1 : OUT std_logic_vector(31 downto 0);
REG3 : OUT std_logic_vector(31 downto 0);
REG4 : OUT std_logic_vector(31 downto 0);
VCO_SELECT : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
signal clk_pll : std_logic; signal clk_pll : std_logic;
signal clk_locked : std_logic; signal clk_locked : std_logic;
signal inv_clk_locked : std_logic; signal inv_clk_locked : std_logic;
@ -231,11 +203,11 @@ architecture Behavioral of top is
signal source_reg_3 : std_logic_vector(31 downto 0); signal source_reg_3 : std_logic_vector(31 downto 0);
signal source_reg_1 : std_logic_vector(31 downto 0); signal source_reg_1 : std_logic_vector(31 downto 0);
signal source_reg_0 : std_logic_vector(31 downto 0); signal source_reg_0 : std_logic_vector(31 downto 0);
signal reload_plls : std_logic;
signal source_reloaded : std_logic; signal source_reloaded : std_logic;
signal source_reloaded_last : std_logic;
signal source_unlocked : std_logic; signal source_unlocked : std_logic;
signal source_reload : std_logic;
signal source_power : std_logic_vector(1 downto 0);
signal source_filter : std_logic_vector(1 downto 0); signal source_filter : std_logic_vector(1 downto 0);
signal band_select : std_logic; signal band_select : std_logic;
signal attenuator : std_logic_vector(6 downto 0); signal attenuator : std_logic_vector(6 downto 0);
@ -264,13 +236,6 @@ architecture Behavioral of top is
signal source_ld_sync : std_logic; signal source_ld_sync : std_logic;
signal nss_sync : std_logic; signal nss_sync : std_logic;
-- VCO table signals
signal vco_write_index : std_logic_vector(5 downto 0);
signal vco_read_index : std_logic_vector(5 downto 0);
signal vco_write : std_logic;
signal vco_write_data : std_logic_vector(15 downto 0);
signal vco_read_data : std_logic_vector(15 downto 0);
-- modulation signals -- modulation signals
signal mod_enable : std_logic; signal mod_enable : std_logic;
signal mod_reset : std_logic; signal mod_reset : std_logic;
@ -279,19 +244,17 @@ architecture Behavioral of top is
signal mod_sample_data : std_logic_vector(7 downto 0); signal mod_sample_data : std_logic_vector(7 downto 0);
signal mod_sample_latch : std_logic; signal mod_sample_latch : std_logic;
signal mod_threshold_level : std_logic_vector(10 downto 0); signal mod_threshold_level : std_logic_vector(10 downto 0);
signal mod_center : std_logic_vector(32 downto 0);
signal mod_deviation : std_logic_vector(25 downto 0);
signal mod_depth : std_logic_vector(6 downto 0);
signal mod_vco_min : std_logic_vector(31 downto 0);
signal mod_fifo_overflow : std_logic; signal mod_fifo_overflow : std_logic;
signal mod_fifo_underflow : std_logic; signal mod_fifo_underflow : std_logic;
signal mod_fifo_threshold_crossed : std_logic; signal mod_fifo_threshold_crossed : std_logic;
signal mod_frequency : std_logic_vector(32 downto 0);
signal mod_attenuator : std_logic_vector(6 downto 0); signal mod_attenuator : std_logic_vector(6 downto 0);
signal mod_new_output : std_logic;
signal pll_calc_done : std_logic; signal mod_lookup_write_data : std_logic_vector(143 downto 0);
signal mod_lookup_read_data : std_logic_vector(143 downto 0);
signal mod_lookup_write_index : std_logic_vector(7 downto 0);
signal mod_lookup_read_index : std_logic_vector(7 downto 0);
signal mod_lookup_write : std_logic;
signal mod_new_output : std_logic;
signal intr : std_logic; signal intr : std_logic;
begin begin
@ -311,7 +274,7 @@ begin
BAND_SELECT_LOW <= band_select; BAND_SELECT_LOW <= band_select;
AMP_PWDN <= amp_shutdown; AMP_PWDN <= amp_shutdown;
ATTENUATION <= attenuator when mod_reset = '1' else mod_attenuator; ATTENUATION <= attenuator when (mod_reset = '1' or aux3_sync = '1') else mod_attenuator;
-- unused signals, ADCs not used -- unused signals, ADCs not used
PORT1_MIX2_EN <= '0'; PORT1_MIX2_EN <= '0';
@ -408,7 +371,7 @@ begin
REG3 => source_reg_3, REG3 => source_reg_3,
REG1 => source_reg_1, REG1 => source_reg_1,
REG0 => source_reg_0, REG0 => source_reg_0,
RELOAD => mod_new_output, RELOAD => source_reload,
CLK_OUT => fpga_source_SCK, CLK_OUT => fpga_source_SCK,
MOSI => fpga_source_MOSI, MOSI => fpga_source_MOSI,
LE => fpga_source_LE, LE => fpga_source_LE,
@ -440,17 +403,6 @@ begin
source_unlocked <= not source_ld_sync; source_unlocked <= not source_ld_sync;
VCOMap : VCO_Mem
PORT MAP (
clka => clk_pll,
wea(0) => vco_write,
addra => vco_write_index,
dina => vco_write_data,
clkb => clk_pll,
addrb => vco_read_index,
doutb => vco_read_data
);
SPI: SPICommands PORT MAP( SPI: SPICommands PORT MAP(
CLK => clk_pll, CLK => clk_pll,
RESET => int_reset, RESET => int_reset,
@ -459,26 +411,21 @@ begin
MISO => fpga_miso, MISO => fpga_miso,
NSS => fpga_select, NSS => fpga_select,
SOURCE_FILTER => source_filter, SOURCE_FILTER => source_filter,
SOURCE_POWER => source_power,
SOURCE_ATTENUATION => attenuator, SOURCE_ATTENUATION => attenuator,
SOURCE_BANDSELECT => band_select, SOURCE_BANDSELECT => band_select,
SOURCE_PORTSELECT => port_select, SOURCE_PORTSELECT => port_select,
SOURCE_UNLOCKED => source_unlocked, SOURCE_UNLOCKED => source_unlocked,
SOURCE_VCO_INDEX => vco_write_index,
SOURCE_VCO_MAXFREQ => vco_write_data,
SOURCE_VCO_WRITE => vco_write,
MOD_FIFO_DATA => mod_sample_data, MOD_FIFO_DATA => mod_sample_data,
MOD_FIFO_WRITE => mod_sample_latch, MOD_FIFO_WRITE => mod_sample_latch,
MOD_FIFO_UNDERFLOW => mod_fifo_underflow, MOD_FIFO_UNDERFLOW => mod_fifo_underflow,
MOD_FIFO_OVERFLOW => mod_fifo_overflow, MOD_FIFO_OVERFLOW => mod_fifo_overflow,
MOD_FIFO_THRESHOLD_CROSSED => mod_fifo_threshold_crossed, MOD_FIFO_THRESHOLD_CROSSED => mod_fifo_threshold_crossed,
MOD_FIFO_THRESHOLD => mod_threshold_level, MOD_FIFO_THRESHOLD => mod_threshold_level,
MOD_LOOKUP_INDEX => mod_lookup_write_index,
MOD_LOOKUP_DATA => mod_lookup_write_data,
MOD_LOOKUP_WRITE => mod_lookup_write,
MOD_ENABLE => mod_enable, MOD_ENABLE => mod_enable,
MOD_PHASE_INC => mod_sample_word, MOD_PHASE_INC => mod_sample_word,
MOD_CENTER_FREQ => mod_center,
MOD_DEVIATION_FREQ => mod_deviation,
MOD_AM_DEPTH => mod_depth,
MOD_VCO_MIN => mod_vco_min,
AMP_SHDN => amp_shutdown, AMP_SHDN => amp_shutdown,
SOURCE_RF_EN => SOURCE_RF_EN, SOURCE_RF_EN => SOURCE_RF_EN,
SOURCE_CE_EN => SOURCE_CE, SOURCE_CE_EN => SOURCE_CE,
@ -490,6 +437,35 @@ begin
mod_reset <= not mod_enable; mod_reset <= not mod_enable;
mod_active <= not aux3_sync; mod_active <= not aux3_sync;
source_reg_0 <= mod_lookup_read_data(31 downto 0);
source_reg_1 <= mod_lookup_read_data(63 downto 32);
source_reg_3 <= mod_lookup_read_data(95 downto 64);
source_reg_4 <= mod_lookup_read_data(127 downto 96);
process(clk_pll)
begin
if rising_edge(clk_pll) then
source_reload <= mod_new_output;
source_reloaded_last <= source_reloaded;
if source_reloaded = '1' and source_reloaded_last = '0' then
-- source has been reloaded, update attenuator
mod_attenuator <= mod_lookup_read_data(134 downto 128);
end if;
end if;
end process;
ModulationMem : ModulationMemory
PORT MAP (
clka => clk_pll,
wea(0) => mod_lookup_write,
addra => mod_lookup_write_index,
dina => mod_lookup_write_data,
clkb => clk_pll,
addrb => mod_lookup_read_index,
doutb => mod_lookup_read_data
);
Modulation: Modulator PORT MAP( Modulation: Modulator PORT MAP(
CLK => clk_pll, CLK => clk_pll,
RESET => mod_reset, RESET => mod_reset,
@ -501,30 +477,9 @@ begin
UNDERFLOW => mod_fifo_underflow, UNDERFLOW => mod_fifo_underflow,
THRESHOLD_LEVEL => mod_threshold_level, THRESHOLD_LEVEL => mod_threshold_level,
THRESHOLD_CROSSED => mod_fifo_threshold_crossed, THRESHOLD_CROSSED => mod_fifo_threshold_crossed,
FREQ_CENTER => mod_center, OUTPUT_SAMPLE => mod_lookup_read_index,
FREQ_DEVIATION => mod_deviation,
MIN_ATTENUATION => attenuator,
AMPLITUDE_DEPTH => mod_depth,
FREQUENCY => mod_frequency,
ATTENUATOR => mod_attenuator,
NEW_OUTPUT => mod_new_output NEW_OUTPUT => mod_new_output
); );
PLL_Calc: MAX2871_Calc PORT MAP(
CLK => clk_pll,
RESET => int_reset,
CALC => mod_new_output,
FREQ => mod_frequency,
VCO_MIN => mod_vco_min,
DONE => pll_calc_done,
REG0 => source_reg_0,
REG1 => source_reg_1,
REG3 => source_reg_3,
REG4 => source_reg_4,
POWER => source_power,
VCO_SELECT => vco_read_index,
VCO_MAX_FREQ => vco_read_data
);
end Behavioral; end Behavioral;