mirror of
https://github.com/jankae/LibreVNA.git
synced 2026-04-04 22:17:31 +00:00
Update to STM32CubeIDE + longer settling time for point 0
This commit is contained in:
Jan Käberich
parent
ffedd3028c
commit
c85d8e8e1f
195 changed files with 21987 additions and 27405 deletions
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@ -7,18 +7,17 @@
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* This file contains:
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* - Data structures and the address mapping for all peripherals
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* - Peripheral's registers declarations and bits definition
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* - Macros to access peripheral’s registers hardware
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* - Macros to access peripheral's registers hardware
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.</center></h2>
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* Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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@ -45,11 +44,11 @@
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/**
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* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
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*/
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#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
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#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */
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#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#define __FPU_PRESENT 1 /*!< FPU present */
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#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
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#define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
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#define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
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#define __FPU_PRESENT 1U /*!< FPU present */
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/**
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* @}
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@ -912,6 +911,10 @@ typedef struct
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} UCPD_TypeDef;
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/**
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* @}
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*/
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/** @addtogroup Peripheral_memory_map
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* @{
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*/
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@ -1189,6 +1192,15 @@ typedef struct
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* @{
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*/
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/** @addtogroup Hardware_Constant_Definition
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* @{
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*/
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#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
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/**
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* @}
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*/
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/** @addtogroup Peripheral_Registers_Bits_Definition
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* @{
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*/
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@ -1438,10 +1450,6 @@ typedef struct
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#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */
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#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */
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#define ADC_CFGR2_LFTRIG_Pos (29U)
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#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */
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#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */
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/******************** Bit definition for ADC_SMPR1 register *****************/
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#define ADC_SMPR1_SMP0_Pos (0U)
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#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
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@ -2196,10 +2204,6 @@ typedef struct
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#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */
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#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
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#define COMP_CSR_DEGLITCHEN_Pos (1U)
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#define COMP_CSR_DEGLITCHEN_Msk (0x1UL << COMP_CSR_DEGLITCHEN_Pos) /*!< 0x00000002 */
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#define COMP_CSR_DEGLITCHEN COMP_CSR_DEGLITCHEN_Msk /*!< Comparator deglitcher enable */
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#define COMP_CSR_INMSEL_Pos (4U)
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#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
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#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
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@ -2232,11 +2236,11 @@ typedef struct
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#define COMP_CSR_BRGEN_Pos (22U)
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#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
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#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */
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#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */
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#define COMP_CSR_SCALEN_Pos (23U)
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#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
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#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */
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#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */
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#define COMP_CSR_VALUE_Pos (30U)
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#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
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@ -2307,7 +2311,6 @@ typedef struct
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#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */
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#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */
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/******************************************************************************/
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/* */
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/* CRC calculation unit */
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@ -2456,9 +2459,9 @@ typedef struct
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/* */
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/******************************************************************************/
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/*
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* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
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* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
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*/
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#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
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#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
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/******************** Bit definition for DAC_CR register ********************/
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#define DAC_CR_EN1_Pos (0U)
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@ -2662,7 +2665,6 @@ typedef struct
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#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
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#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
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#define DAC_SR_DAC2RDY_Pos (27U)
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#define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos) /*!< 0x08000000 */
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#define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk /*!<DAC channel 2 ready status bit */
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@ -2878,7 +2880,6 @@ typedef struct
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#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
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#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
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/******************** Bit definition for DBGMCU_APB1FZR2 register **********/
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/******************** Bit definition for DBGMCU_APB2FZ register ************/
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#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
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@ -8851,19 +8852,19 @@ typedef struct
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#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
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/******************** Bits definition for TAMP_FLTCR register ***************/
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#define TAMP_FLTCR_TAMPFREQ_0 ((uint32_t)0x00000001)
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#define TAMP_FLTCR_TAMPFREQ_1 ((uint32_t)0x00000002)
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#define TAMP_FLTCR_TAMPFREQ_2 ((uint32_t)0x00000004)
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#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
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#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
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#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
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#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
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#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
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#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
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#define TAMP_FLTCR_TAMPFLT_0 ((uint32_t)0x00000008)
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#define TAMP_FLTCR_TAMPFLT_1 ((uint32_t)0x00000010)
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#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
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#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
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#define TAMP_FLTCR_TAMPFLT_Pos (3U)
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#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
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#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
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#define TAMP_FLTCR_TAMPPRCH_0 ((uint32_t)0x00000020)
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#define TAMP_FLTCR_TAMPPRCH_1 ((uint32_t)0x00000040)
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#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
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#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
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#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
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#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
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#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
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@ -9907,35 +9908,36 @@ typedef struct
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/****************** Bit definition for SYSCFG_SWPR register ****************/
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#define SYSCFG_SWPR_PAGE0_Pos (0U)
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#define SYSCFG_SWPR_PAGE0_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
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#define SYSCFG_SWPR_PAGE0 (uint32_t)(SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
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#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
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#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
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#define SYSCFG_SWPR_PAGE1_Pos (1U)
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#define SYSCFG_SWPR_PAGE1_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
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#define SYSCFG_SWPR_PAGE1 (uint32_t)(SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
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#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
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#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
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#define SYSCFG_SWPR_PAGE2_Pos (2U)
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#define SYSCFG_SWPR_PAGE2_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
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#define SYSCFG_SWPR_PAGE2 (uint32_t)(SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
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#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
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#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
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#define SYSCFG_SWPR_PAGE3_Pos (3U)
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#define SYSCFG_SWPR_PAGE3_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
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#define SYSCFG_SWPR_PAGE3 (uint32_t)(SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
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#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
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#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
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#define SYSCFG_SWPR_PAGE4_Pos (4U)
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#define SYSCFG_SWPR_PAGE4_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
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#define SYSCFG_SWPR_PAGE4 (uint32_t)(SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
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#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
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#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
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#define SYSCFG_SWPR_PAGE5_Pos (5U)
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#define SYSCFG_SWPR_PAGE5_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
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#define SYSCFG_SWPR_PAGE5 (uint32_t)(SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
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#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
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#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
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#define SYSCFG_SWPR_PAGE6_Pos (6U)
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#define SYSCFG_SWPR_PAGE6_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
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#define SYSCFG_SWPR_PAGE6 (uint32_t)(SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
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#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
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#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
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#define SYSCFG_SWPR_PAGE7_Pos (7U)
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#define SYSCFG_SWPR_PAGE7_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
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#define SYSCFG_SWPR_PAGE7 (uint32_t)(SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
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#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
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#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
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#define SYSCFG_SWPR_PAGE8_Pos (8U)
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#define SYSCFG_SWPR_PAGE8_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
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#define SYSCFG_SWPR_PAGE8 (uint32_t)(SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
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#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
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#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
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#define SYSCFG_SWPR_PAGE9_Pos (9U)
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#define SYSCFG_SWPR_PAGE9_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
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#define SYSCFG_SWPR_PAGE9 (uint32_t)(SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
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#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
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#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
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/****************** Bit definition for SYSCFG_SKR register ****************/
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#define SYSCFG_SKR_KEY_Pos (0U)
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#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
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@ -12542,7 +12544,6 @@ typedef struct
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*/
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/******************************* ADC Instances ********************************/
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#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
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((INSTANCE) == ADC2))
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@ -12622,7 +12623,6 @@ typedef struct
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((INSTANCE) == OPAMP2) || \
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((INSTANCE) == OPAMP3))
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/******************************** PCD Instances *******************************/
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#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
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@ -12949,7 +12949,6 @@ typedef struct
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((INSTANCE) == TIM15))
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/****************** TIM Instances : supporting OCxREF clear *******************/
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#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
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((INSTANCE) == TIM2) || \
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((INSTANCE) == TIM3) || \
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@ -12982,9 +12981,6 @@ typedef struct
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((INSTANCE) == TIM16) || \
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((INSTANCE) == TIM17))
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/****************** TIM Instances : supporting synchronization ****************/
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#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
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/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
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#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
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((INSTANCE) == TIM8))
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@ -13007,7 +13003,6 @@ typedef struct
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((INSTANCE) == TIM16) || \
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((INSTANCE) == TIM17))
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/****************** TIM Instances : Advanced timer instances *******************/
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#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
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((INSTANCE) == TIM8))
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@ -13142,4 +13137,3 @@ typedef struct
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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@ -16,13 +16,12 @@
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.</center></h2>
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* Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.
|
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*
|
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* This software component is licensed by ST under BSD 3-Clause license,
|
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* the "License"; You may not use this file except in compliance with the
|
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* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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@ -57,14 +56,18 @@
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application
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*/
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#if !defined (STM32G431xx) && !defined (STM32G441xx) && \
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!defined (STM32G471xx) && !defined (STM32G473xx) && !defined (STM32G474xx) && !defined (STM32G484xx) && !defined (STM32GBK1CB)
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#if !defined (STM32G431xx) && !defined (STM32G441xx) && !defined (STM32G471xx) && \
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!defined (STM32G473xx) && !defined (STM32G474xx) && !defined (STM32G484xx) && \
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!defined (STM32GBK1CB) && !defined (STM32G491xx) && !defined (STM32G4A1xx)
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/* #define STM32G431xx */ /*!< STM32G431xx Devices */
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/* #define STM32G441xx */ /*!< STM32G441xx Devices */
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/* #define STM32G471xx */ /*!< STM32G471xx Devices */
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/* #define STM32G473xx */ /*!< STM32G473xx Devices */
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/* #define STM32G483xx */ /*!< STM32G483xx Devices */
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/* #define STM32G474xx */ /*!< STM32G474xx Devices */
|
||||
/* #define STM32G484xx */ /*!< STM32G484xx Devices */
|
||||
/* #define STM32G491xx */ /*!< STM32G491xx Devices */
|
||||
/* #define STM32G4A1xx */ /*!< STM32G4A1xx Devices */
|
||||
/* #define STM32GBK1CB */ /*!< STM32GBK1CB Devices */
|
||||
#endif
|
||||
|
||||
|
|
@ -81,11 +84,11 @@
|
|||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number $VERSION$
|
||||
* @brief CMSIS Device version number V1.2.2
|
||||
*/
|
||||
#define __STM32G4_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
|
||||
#define __STM32G4_CMSIS_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
|
||||
#define __STM32G4_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
|
||||
#define __STM32G4_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
|
||||
#define __STM32G4_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
|
||||
#define __STM32G4_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||
#define __STM32G4_CMSIS_VERSION ((__STM32G4_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__STM32G4_CMSIS_VERSION_SUB1 << 16)\
|
||||
|
|
@ -108,10 +111,16 @@
|
|||
#include "stm32g471xx.h"
|
||||
#elif defined(STM32G473xx)
|
||||
#include "stm32g473xx.h"
|
||||
#elif defined(STM32G483xx)
|
||||
#include "stm32g483xx.h"
|
||||
#elif defined(STM32G474xx)
|
||||
#include "stm32g474xx.h"
|
||||
#elif defined(STM32G484xx)
|
||||
#include "stm32g484xx.h"
|
||||
#elif defined(STM32G491xx)
|
||||
#include "stm32g491xx.h"
|
||||
#elif defined(STM32G4A1xx)
|
||||
#include "stm32g4a1xx.h"
|
||||
#elif defined(STM32GBK1CB)
|
||||
#include "stm32gbk1cb.h"
|
||||
#else
|
||||
|
|
@ -168,6 +177,61 @@ typedef enum
|
|||
|
||||
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
|
||||
|
||||
/* Use of CMSIS compiler intrinsics for register exclusive access */
|
||||
/* Atomic 32-bit register access macro to set one or several bits */
|
||||
#define ATOMIC_SET_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint32_t val; \
|
||||
do { \
|
||||
val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
|
||||
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 32-bit register access macro to clear one or several bits */
|
||||
#define ATOMIC_CLEAR_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint32_t val; \
|
||||
do { \
|
||||
val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
|
||||
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 32-bit register access macro to clear and set one or several bits */
|
||||
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
|
||||
do { \
|
||||
uint32_t val; \
|
||||
do { \
|
||||
val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
|
||||
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 16-bit register access macro to set one or several bits */
|
||||
#define ATOMIC_SETH_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint16_t val; \
|
||||
do { \
|
||||
val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
|
||||
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 16-bit register access macro to clear one or several bits */
|
||||
#define ATOMIC_CLEARH_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint16_t val; \
|
||||
do { \
|
||||
val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
|
||||
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 16-bit register access macro to clear and set one or several bits */
|
||||
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
|
||||
do { \
|
||||
uint16_t val; \
|
||||
do { \
|
||||
val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
|
||||
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -193,4 +257,3 @@ typedef enum
|
|||
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -103,4 +102,3 @@ extern void SystemCoreClockUpdate(void);
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue