diff --git a/Software/VNA_embedded/.cproject b/Software/VNA_embedded/.cproject index 41f3bde..3cc9c10 100644 --- a/Software/VNA_embedded/.cproject +++ b/Software/VNA_embedded/.cproject @@ -1,812 +1,268 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Software/VNA_embedded/.mxproject b/Software/VNA_embedded/.mxproject index 728195e..d0e589b 100644 --- a/Software/VNA_embedded/.mxproject +++ b/Software/VNA_embedded/.mxproject @@ -1,14 +1,14 @@ [PreviousLibFiles] -LibFiles=Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h;Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cortex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.c;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_exti.h;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_exti.c;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crs.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_ucpd.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h;Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h;Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h;Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h;Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h;Middlewares/Third_Party/FreeRTOS/Source/include/list.h;Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h;Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h;Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h;Middlewares/Third_Party/FreeRTOS/Source/include/portable.h;Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h;Middlewares/Third_Party/FreeRTOS/Source/include/queue.h;Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h;Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h;Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h;Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h;Middlewares/Third_Party/FreeRTOS/Source/include/task.h;Middlewares/Third_Party/FreeRTOS/Source/include/timers.h;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h;Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_core.h;Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_def.h;Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_tcpm.h;Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_trace.h;Middlewares/ST/STM32_USBPD_Library/Core/lib/USBPDCORE_PD3_FULL_CM4_wc32.a;Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_cad_hw_if.h;Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_hw.h;Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_hw_if.h;Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_phy.h;Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_timersserver.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c;Dri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32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c;Middlewares/Third_Party/FreeRTOS/Source/croutine.c;Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;Middlewares/Third_Party/FreeRTOS/Source/list.c;Middlewares/Third_Party/FreeRTOS/Source/queue.c;Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;Middlewares/Third_Party/FreeRTOS/Source/tasks.c;Middlewares/Third_Party/FreeRTOS/Source/timers.c;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h;Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cortex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.c;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_exti.h;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_exti.c;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crs.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_ucpd.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h;Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h;Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h;Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h;Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h;Middlewares/Third_Party/FreeRTOS/Source/include/list.h;Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h;Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h;Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h;Middlewares/Third_Party/FreeRTOS/Source/include/portable.h;Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h;Middlewares/Third_Party/FreeRTOS/Source/include/queue.h;Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h;Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h;Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h;Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h;Middlewares/Third_Party/FreeRTOS/Source/include/task.h;Middlewares/Third_Party/FreeRTOS/Source/include/timers.h;Middlewares/Third_Party/FreeRTOS/Source/include/atomic.h;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h;Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h;Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h;Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h;Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/system_stm32g4xx.c;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/cmsis_armclang_ltm.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cm35p.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/core_armv81mml.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_version.h; -[PreviousUsedSW4STM32Files] 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\Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c;..\Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c;..\Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c;..\Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c;..\Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c;..\Middlewares/Third_Party/FreeRTOS/Source/croutine.c;..\Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;..\Middlewares/Third_Party/FreeRTOS/Source/list.c;..\Middlewares/Third_Party/FreeRTOS/Source/queue.c;..\Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;..\Middlewares/Third_Party/FreeRTOS/Source/tasks.c;..\Middlewares/Third_Party/FreeRTOS/Source/timers.c;..\Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c;..\Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c;..\Middlewares/ST/STM32_USBPD_Library/Core/src/usbpd_trace.c;..\Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_cad_hw_if.c;..\Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_hw.c;..\Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_hw_if_it.c;..\Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_phy.c;..\Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_phy_hw_if.c;..\Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_pwr_hw_if.c;..\Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_timersserver.c;..\Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_tim.c;..\\Src/system_stm32g4xx.c;..\Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/system_stm32g4xx.c;;..\Middlewares/Third_Party/FreeRTOS/Source/croutine.c;..\Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;..\Middlewares/Third_Party/FreeRTOS/Source/list.c;..\Middlewares/Third_Party/FreeRTOS/Source/queue.c;..\Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;..\Middlewares/Third_Party/FreeRTOS/Source/tasks.c;..\Middlewares/Third_Party/FreeRTOS/Source/timers.c;..\Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c;..\Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c;..\Middlewares/ST/STM32_USBPD_Library/Core/lib/USBPDCORE_PD3_FULL_CM4_wc32.a;..\Middlewares/ST/STM32_USBPD_Library/Core/src/usbpd_trace.c;..\Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_cad_hw_if.c;..\Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_hw.c;..\Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_hw_if_it.c;..\Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_phy.c;..\Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_phy_hw_if.c;..\Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_pwr_hw_if.c;..\Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_timersserver.c; -HeaderPath=..\Drivers\STM32G4xx_HAL_Driver\Inc;..\Drivers\STM32G4xx_HAL_Driver\Inc\Legacy;..\Middlewares\Third_Party\FreeRTOS\Source\include;..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS;..\Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F;..\Middlewares\ST\STM32_USBPD_Library\Core\inc;..\Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\inc;..\Drivers\CMSIS\Device\ST\STM32G4xx\Include;..\Drivers\CMSIS\Include;..\Inc; -CDefines=USE_FULL_LL_DRIVER;USBPD_PORT_COUNT:1;USBPDCORE_LIB_PD3_FULL;_RTOS;_SNK;USE_FULL_LL_DRIVER;USE_HAL_DRIVER;STM32G431xx;USE_FULL_LL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; +[PreviousUsedCubeIDEFiles] +SourceFiles=Src/main.c;Src/app_freertos.c;Src/stm32g4xx_it.c;Src/stm32g4xx_hal_msp.c;Src/stm32g4xx_hal_timebase_tim.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_exti.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_ucpd.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_gpio.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_dma.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c;Middlewares/Third_Party/FreeRTOS/Source/croutine.c;Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;Middlewares/Third_Party/FreeRTOS/Source/list.c;Middlewares/Third_Party/FreeRTOS/Source/queue.c;Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;Middlewares/Third_Party/FreeRTOS/Source/tasks.c;Middlewares/Third_Party/FreeRTOS/Source/timers.c;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c;Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/system_stm32g4xx.c;Src/system_stm32g4xx.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_exti.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_ucpd.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_gpio.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_dma.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c;Middlewares/Third_Party/FreeRTOS/Source/croutine.c;Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;Middlewares/Third_Party/FreeRTOS/Source/list.c;Middlewares/Third_Party/FreeRTOS/Source/queue.c;Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;Middlewares/Third_Party/FreeRTOS/Source/tasks.c;Middlewares/Third_Party/FreeRTOS/Source/timers.c;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c;Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/system_stm32g4xx.c;Src/system_stm32g4xx.c;;;Middlewares/Third_Party/FreeRTOS/Source/croutine.c;Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;Middlewares/Third_Party/FreeRTOS/Source/list.c;Middlewares/Third_Party/FreeRTOS/Source/queue.c;Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;Middlewares/Third_Party/FreeRTOS/Source/tasks.c;Middlewares/Third_Party/FreeRTOS/Source/timers.c;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c; +HeaderPath=Drivers/STM32G4xx_HAL_Driver/Inc;Drivers/STM32G4xx_HAL_Driver/Inc/Legacy;Middlewares/Third_Party/FreeRTOS/Source/include;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F;Drivers/CMSIS/Device/ST/STM32G4xx/Include;Drivers/CMSIS/Include;Inc; +CDefines=USE_FULL_LL_DRIVER;USE_HAL_DRIVER;STM32G431xx;USE_FULL_LL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; [PreviousGenFiles] -HeaderPath=C:/Users/jan/Desktop/Privat/VNA2/Software/VNA_embedded/Inc -HeaderFiles=FreeRTOSConfig.h;usbpd.h;usbpd_dpm_conf.h;usbpd_dpm_user.h;usbpd_pwr_user.h;usbpd_pdo_defs.h;usbpd_pwr_if.h;usbpd_vdm_user.h;usbpd_dpm_core.h;usbpd_devices_conf.h;stm32g4xx_it.h;stm32_assert.h;stm32g4xx_hal_conf.h;main.h; -SourcePath=C:/Users/jan/Desktop/Privat/VNA2/Software/VNA_embedded/Src -SourceFiles=app_freertos.c;usbpd.c;usbpd_dpm_user.c;usbpd_pwr_user.c;usbpd_pwr_if.c;usbpd_vdm_user.c;usbpd_dpm_core.c;stm32g4xx_it.c;stm32g4xx_hal_msp.c;stm32g4xx_hal_timebase_tim.c;main.c; +HeaderPath=../Inc +HeaderFiles=FreeRTOSConfig.h;stm32g4xx_it.h;stm32_assert.h;stm32g4xx_hal_conf.h;main.h; +SourcePath=../Src +SourceFiles=app_freertos.c;stm32g4xx_it.c;stm32g4xx_hal_msp.c;stm32g4xx_hal_timebase_tim.c;main.c; diff --git a/Software/VNA_embedded/.project b/Software/VNA_embedded/.project index 4eb1f92..e410894 100644 --- a/Software/VNA_embedded/.project +++ b/Software/VNA_embedded/.project @@ -1,7 +1,7 @@ VNA_embedded - + @@ -19,10 +19,14 @@ + com.st.stm32cube.ide.mcu.MCUProjectNature + com.st.stm32cube.ide.mcu.MCUCubeProjectNature org.eclipse.cdt.core.cnature + com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature + com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature + com.st.stm32cube.ide.mcu.MCURootProjectNature org.eclipse.cdt.managedbuilder.core.managedBuildNature org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - fr.ac6.mcu.ide.core.MCUProjectNature org.eclipse.cdt.core.ccnature diff --git a/Software/VNA_embedded/.settings/language.settings.xml b/Software/VNA_embedded/.settings/language.settings.xml index 17b53d6..0c8cdbb 100644 --- a/Software/VNA_embedded/.settings/language.settings.xml +++ b/Software/VNA_embedded/.settings/language.settings.xml @@ -1,48 +1,27 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Software/VNA_embedded/.settings/stm32cubeide.project.prefs b/Software/VNA_embedded/.settings/stm32cubeide.project.prefs new file mode 100644 index 0000000..b186ead --- /dev/null +++ b/Software/VNA_embedded/.settings/stm32cubeide.project.prefs @@ -0,0 +1,4 @@ +66BE74F758C12D739921AEA421D593D3=2 +8DF89ED150041C4CBC7CB9A9CAA90856=6F84FD31C089E822CF61FFCABCD0B7D1 +DC22A860405A8BF2F2C095E5B6529F12=6F84FD31C089E822CF61FFCABCD0B7D1 +eclipse.preferences.version=1 diff --git a/Software/VNA_embedded/Application/VNA.cpp b/Software/VNA_embedded/Application/VNA.cpp index 14c39e4..3e9b9de 100644 --- a/Software/VNA_embedded/Application/VNA.cpp +++ b/Software/VNA_embedded/Application/VNA.cpp @@ -255,6 +255,11 @@ bool VNA::Setup(Protocol::SweepSettings s) { attenuator = amplitude.attenuator; } + // needs halt before first point to allow PLLs to settle + if (i == 0) { + needs_halt = true; + } + FPGA::WriteSweepConfig(i, lowband, Source.GetRegisters(), LO1.GetRegisters(), attenuator, freq, FPGA::SettlingTime::us20, FPGA::Samples::SPPRegister, needs_halt); @@ -419,6 +424,10 @@ void VNA::SweepHalted() { FPGA::Enable(FPGA::Periphery::SourceRF); } + if (pointCnt == 0) { + HAL_Delay(2); + } + if(adcShiftRequired) { FPGA::WriteRegister(FPGA::Reg::ADCPrescaler, alternativePrescaler); FPGA::WriteRegister(FPGA::Reg::PhaseIncrement, alternativePhaseInc); diff --git a/Software/VNA_embedded/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h b/Software/VNA_embedded/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h index 16ddad4..7e3265d 100644 --- a/Software/VNA_embedded/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h +++ b/Software/VNA_embedded/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h @@ -7,18 +7,17 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -45,11 +44,11 @@ /** * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ -#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ -#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ /** * @} @@ -912,6 +911,10 @@ typedef struct } UCPD_TypeDef; +/** + * @} + */ + /** @addtogroup Peripheral_memory_map * @{ */ @@ -1189,6 +1192,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -1438,10 +1450,6 @@ typedef struct #define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ #define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ -#define ADC_CFGR2_LFTRIG_Pos (29U) -#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ -#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */ - /******************** Bit definition for ADC_SMPR1 register *****************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -2196,10 +2204,6 @@ typedef struct #define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ #define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ -#define COMP_CSR_DEGLITCHEN_Pos (1U) -#define COMP_CSR_DEGLITCHEN_Msk (0x1UL << COMP_CSR_DEGLITCHEN_Pos) /*!< 0x00000002 */ -#define COMP_CSR_DEGLITCHEN COMP_CSR_DEGLITCHEN_Msk /*!< Comparator deglitcher enable */ - #define COMP_CSR_INMSEL_Pos (4U) #define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ #define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ @@ -2232,11 +2236,11 @@ typedef struct #define COMP_CSR_BRGEN_Pos (22U) #define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ -#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */ +#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */ #define COMP_CSR_SCALEN_Pos (23U) #define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ -#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */ +#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */ #define COMP_CSR_VALUE_Pos (30U) #define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ @@ -2307,7 +2311,6 @@ typedef struct #define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ #define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ - /******************************************************************************/ /* */ /* CRC calculation unit */ @@ -2456,9 +2459,9 @@ typedef struct /* */ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ - #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ /******************** Bit definition for DAC_CR register ********************/ #define DAC_CR_EN1_Pos (0U) @@ -2662,7 +2665,6 @@ typedef struct #define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */ #define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!
© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -57,14 +56,18 @@ application */ -#if !defined (STM32G431xx) && !defined (STM32G441xx) && \ - !defined (STM32G471xx) && !defined (STM32G473xx) && !defined (STM32G474xx) && !defined (STM32G484xx) && !defined (STM32GBK1CB) +#if !defined (STM32G431xx) && !defined (STM32G441xx) && !defined (STM32G471xx) && \ + !defined (STM32G473xx) && !defined (STM32G474xx) && !defined (STM32G484xx) && \ + !defined (STM32GBK1CB) && !defined (STM32G491xx) && !defined (STM32G4A1xx) /* #define STM32G431xx */ /*!< STM32G431xx Devices */ /* #define STM32G441xx */ /*!< STM32G441xx Devices */ /* #define STM32G471xx */ /*!< STM32G471xx Devices */ /* #define STM32G473xx */ /*!< STM32G473xx Devices */ + /* #define STM32G483xx */ /*!< STM32G483xx Devices */ /* #define STM32G474xx */ /*!< STM32G474xx Devices */ /* #define STM32G484xx */ /*!< STM32G484xx Devices */ + /* #define STM32G491xx */ /*!< STM32G491xx Devices */ + /* #define STM32G4A1xx */ /*!< STM32G4A1xx Devices */ /* #define STM32GBK1CB */ /*!< STM32GBK1CB Devices */ #endif @@ -81,11 +84,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number $VERSION$ + * @brief CMSIS Device version number V1.2.2 */ #define __STM32G4_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32G4_CMSIS_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ -#define __STM32G4_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32G4_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ +#define __STM32G4_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */ #define __STM32G4_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32G4_CMSIS_VERSION ((__STM32G4_CMSIS_VERSION_MAIN << 24)\ |(__STM32G4_CMSIS_VERSION_SUB1 << 16)\ @@ -108,10 +111,16 @@ #include "stm32g471xx.h" #elif defined(STM32G473xx) #include "stm32g473xx.h" +#elif defined(STM32G483xx) + #include "stm32g483xx.h" #elif defined(STM32G474xx) #include "stm32g474xx.h" #elif defined(STM32G484xx) #include "stm32g484xx.h" +#elif defined(STM32G491xx) + #include "stm32g491xx.h" +#elif defined(STM32G4A1xx) + #include "stm32g4a1xx.h" #elif defined(STM32GBK1CB) #include "stm32gbk1cb.h" #else @@ -168,6 +177,61 @@ typedef enum #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) +/* Use of CMSIS compiler intrinsics for register exclusive access */ +/* Atomic 32-bit register access macro to set one or several bits */ +#define ATOMIC_SET_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEAR_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint32_t val; \ + do { \ + val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to set one or several bits */ +#define ATOMIC_SETH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEARH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint16_t val; \ + do { \ + val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + /** * @} @@ -193,4 +257,3 @@ typedef enum -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h b/Software/VNA_embedded/Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h index 99b7f53..ba8bdae 100644 --- a/Software/VNA_embedded/Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h +++ b/Software/VNA_embedded/Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -103,4 +102,3 @@ extern void SystemCoreClockUpdate(void); /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/CMSIS/Device/ST/STM32G4xx/LICENSE.txt b/Software/VNA_embedded/Drivers/CMSIS/Device/ST/STM32G4xx/LICENSE.txt new file mode 100644 index 0000000..5306686 --- /dev/null +++ b/Software/VNA_embedded/Drivers/CMSIS/Device/ST/STM32G4xx/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the Apache-2.0 license shall apply. +You may obtain a copy of the Apache-2.0 at: +https://opensource.org/licenses/Apache-2.0 diff --git a/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_armcc.h b/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_armcc.h index 7d751fb..da9d654 100644 --- a/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_armcc.h +++ b/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_armcc.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_armcc.h * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file - * @version V5.0.4 - * @date 10. January 2018 + * @version V5.1.0 + * @date 08. May 2019 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -47,6 +47,10 @@ /* __ARM_ARCH_8M_BASE__ not applicable */ /* __ARM_ARCH_8M_MAIN__ not applicable */ +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif /* CMSIS compiler specific defines */ #ifndef __ASM @@ -100,6 +104,31 @@ #ifndef __RESTRICT #define __RESTRICT __restrict #endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface diff --git a/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_armclang.h b/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_armclang.h index d8031b0..478f75b 100644 --- a/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_armclang.h +++ b/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_armclang.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_armclang.h * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V5.0.4 - * @date 10. January 2018 + * @version V5.2.0 + * @date 08. May 2019 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -43,9 +43,9 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif -#ifndef __STATIC_FORCEINLINE +#ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif +#endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif @@ -110,7 +110,31 @@ #ifndef __RESTRICT #define __RESTRICT __restrict #endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface @@ -781,9 +805,11 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) * Otherwise, use general registers, specified by constraint "r" */ #if defined (__thumb__) && !defined (__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) #define __CMSIS_GCC_USE_REG(r) "l" (r) #else #define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) #define __CMSIS_GCC_USE_REG(r) "r" (r) #endif @@ -821,14 +847,14 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ -#define __ISB() __builtin_arm_isb(0xF); +#define __ISB() __builtin_arm_isb(0xF) /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ -#define __DSB() __builtin_arm_dsb(0xF); +#define __DSB() __builtin_arm_dsb(0xF) /** @@ -836,7 +862,7 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ -#define __DMB() __builtin_arm_dmb(0xF); +#define __DMB() __builtin_arm_dmb(0xF) /** @@ -908,7 +934,23 @@ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) \param [in] value Value to count the leading zeros \return number of leading zeros in value */ -#define __CLZ (uint8_t)__builtin_clz +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ @@ -1321,532 +1363,65 @@ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#if 0 -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) -#endif +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) diff --git a/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_armclang_ltm.h b/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000..1b5a965 --- /dev/null +++ b/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1891 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_compiler.h b/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_compiler.h index 79a2cac..21a2c71 100644 --- a/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_compiler.h +++ b/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_compiler.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file cmsis_compiler.h * @brief CMSIS compiler generic header file - * @version V5.0.4 - * @date 10. January 2018 + * @version V5.1.0 + * @date 09. October 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. @@ -35,9 +35,15 @@ /* - * Arm Compiler 6 (armclang) + * Arm Compiler 6.6 LTM (armclang) */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) #include "cmsis_armclang.h" @@ -115,8 +121,11 @@ #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 #endif @@ -187,6 +196,10 @@ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif /* @@ -255,6 +268,10 @@ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif #else diff --git a/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_gcc.h b/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_gcc.h index 1bd41a4..1e08e7e 100644 --- a/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_gcc.h +++ b/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_gcc.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_gcc.h * @brief CMSIS compiler GCC header file - * @version V5.0.4 - * @date 09. April 2018 + * @version V5.2.0 + * @date 08. May 2019 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -113,7 +113,74 @@ #ifndef __RESTRICT #define __RESTRICT __restrict #endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface @@ -1008,7 +1075,23 @@ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) \param [in] value Value to count the leading zeros \return number of leading zeros in value */ -#define __CLZ (uint8_t)__builtin_clz +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ diff --git a/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_iccarm.h b/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_iccarm.h index 3c90a2c..7af7562 100644 --- a/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_iccarm.h +++ b/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_iccarm.h @@ -1,13 +1,14 @@ /**************************************************************************//** * @file cmsis_iccarm.h * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.0.7 - * @date 19. June 2018 + * @version V5.1.0 + * @date 08. May 2019 ******************************************************************************/ //------------------------------------------------------------------------------ // -// Copyright (c) 2017-2018 IAR Systems +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. // // Licensed under the Apache License, Version 2.0 (the "License") // you may not use this file except in compliance with the License. @@ -110,6 +111,10 @@ #define __ASM __asm #endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + #ifndef __INLINE #define __INLINE inline #endif @@ -150,7 +155,12 @@ #endif #ifndef __RESTRICT - #define __RESTRICT __restrict + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif #endif #ifndef __STATIC_INLINE @@ -234,6 +244,25 @@ __packed struct __iar_u32 { uint32_t v; }; #endif #endif +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif #ifndef __ICCARM_INTRINSICS_VERSION__ #define __ICCARM_INTRINSICS_VERSION__ 0 diff --git a/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_version.h b/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_version.h index ae3f2e3..3174cf6 100644 --- a/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_version.h +++ b/Software/VNA_embedded/Drivers/CMSIS/Include/cmsis_version.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_version.h * @brief CMSIS Core(M) Version definitions - * @version V5.0.2 - * @date 19. April 2017 + * @version V5.0.3 + * @date 24. June 2019 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -33,7 +33,7 @@ /* CMSIS Version definitions */ #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ #endif diff --git a/Software/VNA_embedded/Drivers/CMSIS/Include/core_armv81mml.h b/Software/VNA_embedded/Drivers/CMSIS/Include/core_armv81mml.h new file mode 100644 index 0000000..8cee930 --- /dev/null +++ b/Software/VNA_embedded/Drivers/CMSIS/Include/core_armv81mml.h @@ -0,0 +1,2968 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 15. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +#define __ARM_ARCH_8M_MAIN__ 1 // patching for now +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Software/VNA_embedded/Drivers/CMSIS/Include/core_armv8mbl.h b/Software/VNA_embedded/Drivers/CMSIS/Include/core_armv8mbl.h index ec76ab2..266f180 100644 --- a/Software/VNA_embedded/Drivers/CMSIS/Include/core_armv8mbl.h +++ b/Software/VNA_embedded/Drivers/CMSIS/Include/core_armv8mbl.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_armv8mbl.h * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File - * @version V5.0.7 - * @date 22. June 2018 + * @version V5.0.8 + * @date 12. November 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. @@ -81,7 +81,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif @@ -1223,7 +1223,7 @@ typedef struct #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ @@ -1253,7 +1253,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -1552,6 +1554,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) uint32_t *vectors = (uint32_t *)0x0U; #endif vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); } diff --git a/Software/VNA_embedded/Drivers/CMSIS/Include/core_armv8mml.h b/Software/VNA_embedded/Drivers/CMSIS/Include/core_armv8mml.h index 2d0f106..ba5d83f 100644 --- a/Software/VNA_embedded/Drivers/CMSIS/Include/core_armv8mml.h +++ b/Software/VNA_embedded/Drivers/CMSIS/Include/core_armv8mml.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_armv8mml.h * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File - * @version V5.0.7 - * @date 06. July 2018 + * @version V5.1.0 + * @date 12. September 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. @@ -97,7 +97,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else @@ -538,14 +538,6 @@ typedef struct __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ } SCB_Type; /* SCB CPUID Register Definitions */ @@ -921,78 +913,6 @@ typedef struct #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - /*@} end of group CMSIS_SCB */ @@ -1097,10 +1017,7 @@ typedef struct __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ @@ -1163,18 +1080,6 @@ typedef struct #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ @@ -2093,7 +1998,7 @@ typedef struct #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ @@ -2122,7 +2027,7 @@ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } @@ -2148,7 +2053,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -2440,6 +2347,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); } @@ -2496,7 +2404,7 @@ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB_NS->AIRCR = reg_value; } diff --git a/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm0.h b/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm0.h index 6f82227..70e4505 100644 --- a/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm0.h +++ b/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm0.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_cm0.h * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V5.0.5 - * @date 28. May 2018 + * @version V5.0.6 + * @date 13. March 2019 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -81,7 +81,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif @@ -316,7 +316,7 @@ typedef struct __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; + uint32_t RESERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ @@ -624,7 +624,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -829,8 +831,9 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { - uint32_t *vectors = (uint32_t *)0x0U; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ } @@ -844,8 +847,8 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { - uint32_t *vectors = (uint32_t *)0x0U; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); } diff --git a/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm0plus.h b/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm0plus.h index b9377e8..fe7b424 100644 --- a/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm0plus.h +++ b/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm0plus.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_cm0plus.h * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V5.0.6 - * @date 28. May 2018 + * @version V5.0.7 + * @date 13. March 2019 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -81,7 +81,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif @@ -330,7 +330,7 @@ typedef struct __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; + uint32_t RESERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ @@ -742,7 +742,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -948,11 +950,12 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; + uint32_t vectors = SCB->VTOR; #else - uint32_t *vectors = (uint32_t *)0x0U; + uint32_t vectors = 0x0U; #endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ } @@ -967,12 +970,11 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; + uint32_t vectors = SCB->VTOR; #else - uint32_t *vectors = (uint32_t *)0x0U; + uint32_t vectors = 0x0U; #endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; - + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); } diff --git a/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm1.h b/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm1.h index fd1c407..44c2a49 100644 --- a/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm1.h +++ b/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm1.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_cm1.h * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File - * @version V1.0.0 - * @date 23. July 2018 + * @version V1.0.1 + * @date 12. November 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. @@ -81,7 +81,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif @@ -651,7 +651,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -858,6 +860,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)0x0U; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ } diff --git a/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm23.h b/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm23.h index 8202a8d..49f4a5b 100644 --- a/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm23.h +++ b/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm23.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_cm23.h * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File - * @version V5.0.7 - * @date 22. June 2018 + * @version V5.0.8 + * @date 12. November 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. @@ -81,7 +81,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif @@ -1298,7 +1298,7 @@ typedef struct #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ @@ -1328,7 +1328,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -1627,6 +1629,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) uint32_t *vectors = (uint32_t *)0x0U; #endif vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); } diff --git a/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm3.h b/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm3.h index b0dfbd3..1f69e8b 100644 --- a/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm3.h +++ b/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm3.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V5.0.8 - * @date 04. June 2018 + * @version V5.1.0 + * @date 13. March 2019 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -81,7 +81,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif @@ -342,7 +342,7 @@ typedef struct __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; + uint32_t RESERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ @@ -668,6 +668,12 @@ typedef struct #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ @@ -677,6 +683,7 @@ typedef struct #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif /*@} end of group CMSIS_SCnotSCB */ @@ -757,10 +764,7 @@ typedef struct __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ @@ -811,18 +815,6 @@ typedef struct #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ @@ -1055,13 +1047,13 @@ typedef struct /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ @@ -1084,13 +1076,13 @@ typedef struct /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ @@ -1512,7 +1504,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -1735,8 +1729,9 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ } @@ -1750,8 +1745,8 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); } @@ -1784,6 +1779,7 @@ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) #endif + /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface diff --git a/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm33.h b/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm33.h index 02f82e2..2f1d98e 100644 --- a/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm33.h +++ b/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm33.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_cm33.h * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File - * @version V5.0.9 - * @date 06. July 2018 + * @version V5.1.0 + * @date 12. November 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. @@ -97,7 +97,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined (__ARM_PCS_VFP) + #if defined (__ARM_FP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else @@ -538,14 +538,6 @@ typedef struct __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ } SCB_Type; /* SCB CPUID Register Definitions */ @@ -921,78 +913,6 @@ typedef struct #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - /*@} end of group CMSIS_SCB */ @@ -1097,10 +1017,7 @@ typedef struct __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ @@ -1163,18 +1080,6 @@ typedef struct #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ @@ -2168,7 +2073,7 @@ typedef struct #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ @@ -2197,7 +2102,7 @@ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } @@ -2223,7 +2128,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -2515,6 +2422,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); } diff --git a/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm35p.h b/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm35p.h new file mode 100644 index 0000000..7d34367 --- /dev/null +++ b/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm35p.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm4.h b/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm4.h index 308b868..90c2a72 100644 --- a/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm4.h +++ b/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm4.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_cm4.h * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V5.0.8 - * @date 04. June 2018 + * @version V5.1.0 + * @date 13. March 2019 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -86,7 +86,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else @@ -408,7 +408,7 @@ typedef struct __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; + uint32_t RESERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ @@ -822,10 +822,7 @@ typedef struct __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ @@ -876,18 +873,6 @@ typedef struct #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ @@ -1120,13 +1105,13 @@ typedef struct /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ @@ -1149,13 +1134,13 @@ typedef struct /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ @@ -1324,6 +1309,7 @@ typedef struct __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ @@ -1409,6 +1395,11 @@ typedef struct #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + /*@} end of group CMSIS_FPU */ @@ -1625,7 +1616,7 @@ typedef struct #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else @@ -1689,7 +1680,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -1912,8 +1905,9 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ } @@ -1927,8 +1921,8 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); } @@ -1953,6 +1947,7 @@ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) /*@} end of CMSIS_Core_NVICFunctions */ + /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) diff --git a/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm7.h b/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm7.h index ada6c2a..3da3c43 100644 --- a/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm7.h +++ b/Software/VNA_embedded/Drivers/CMSIS/Include/core_cm7.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_cm7.h * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V5.0.8 - * @date 04. June 2018 + * @version V5.1.1 + * @date 28. March 2019 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -86,7 +86,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else @@ -423,7 +423,7 @@ typedef struct __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; + uint32_t RESERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ @@ -930,6 +930,24 @@ typedef struct #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ @@ -1024,10 +1042,7 @@ typedef struct __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ @@ -1078,18 +1093,6 @@ typedef struct #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ @@ -1325,13 +1328,13 @@ typedef struct /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ @@ -1354,13 +1357,13 @@ typedef struct /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ @@ -1617,6 +1620,9 @@ typedef struct /* Media and FP Feature Register 2 Definitions */ +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + /*@} end of group CMSIS_FPU */ @@ -1897,7 +1903,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -2120,8 +2128,9 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + __DSB(); } @@ -2135,8 +2144,8 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); } @@ -2161,6 +2170,7 @@ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) /*@} end of CMSIS_Core_NVICFunctions */ + /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) @@ -2169,6 +2179,7 @@ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) #endif + /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface @@ -2204,7 +2215,6 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void) } } - /*@} end of CMSIS_Core_FpuFunctions */ @@ -2221,14 +2231,18 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void) #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ /** \brief Enable I-Cache \details Turns on I-Cache */ -__STATIC_INLINE void SCB_EnableICache (void) +__STATIC_FORCEINLINE void SCB_EnableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + __DSB(); __ISB(); SCB->ICIALLU = 0UL; /* invalidate I-Cache */ @@ -2245,7 +2259,7 @@ __STATIC_INLINE void SCB_EnableICache (void) \brief Disable I-Cache \details Turns off I-Cache */ -__STATIC_INLINE void SCB_DisableICache (void) +__STATIC_FORCEINLINE void SCB_DisableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) __DSB(); @@ -2262,7 +2276,7 @@ __STATIC_INLINE void SCB_DisableICache (void) \brief Invalidate I-Cache \details Invalidates I-Cache */ -__STATIC_INLINE void SCB_InvalidateICache (void) +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) __DSB(); @@ -2274,18 +2288,50 @@ __STATIC_INLINE void SCB_InvalidateICache (void) } +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + /** \brief Enable D-Cache \details Turns on D-Cache */ -__STATIC_INLINE void SCB_EnableDCache (void) +__STATIC_FORCEINLINE void SCB_EnableDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; @@ -2316,14 +2362,14 @@ __STATIC_INLINE void SCB_EnableDCache (void) \brief Disable D-Cache \details Turns off D-Cache */ -__STATIC_INLINE void SCB_DisableDCache (void) +__STATIC_FORCEINLINE void SCB_DisableDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ @@ -2354,14 +2400,14 @@ __STATIC_INLINE void SCB_DisableDCache (void) \brief Invalidate D-Cache \details Invalidates D-Cache */ -__STATIC_INLINE void SCB_InvalidateDCache (void) +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; @@ -2389,15 +2435,15 @@ __STATIC_INLINE void SCB_InvalidateDCache (void) \brief Clean D-Cache \details Cleans D-Cache */ -__STATIC_INLINE void SCB_CleanDCache (void) +__STATIC_FORCEINLINE void SCB_CleanDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); ccsidr = SCB->CCSIDR; @@ -2424,14 +2470,14 @@ __STATIC_INLINE void SCB_CleanDCache (void) \brief Clean & Invalidate D-Cache \details Cleans and Invalidates D-Cache */ -__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; @@ -2457,27 +2503,30 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache (void) /** \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address \param[in] dsize size of memory block (in number of bytes) */ -__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t)addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); - __DSB(); + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); - while (op_size > 0) { - SCB->DCIMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; + __DSB(); + __ISB(); } - - __DSB(); - __ISB(); #endif } @@ -2485,26 +2534,29 @@ __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize /** \brief D-Cache Clean by address \details Cleans D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address \param[in] dsize size of memory block (in number of bytes) */ -__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); - __DSB(); + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); - while (op_size > 0) { - SCB->DCCMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; + __DSB(); + __ISB(); } - - __DSB(); - __ISB(); #endif } @@ -2512,30 +2564,32 @@ __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) /** \brief D-Cache Clean and Invalidate by address \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. \param[in] addr address (aligned to 32-byte boundary) \param[in] dsize size of memory block (in number of bytes) */ -__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); - __DSB(); + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); - while (op_size > 0) { - SCB->DCCIMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; + __DSB(); + __ISB(); } - - __DSB(); - __ISB(); #endif } - /*@} end of CMSIS_Core_CacheFunctions */ diff --git a/Software/VNA_embedded/Drivers/CMSIS/Include/core_sc000.h b/Software/VNA_embedded/Drivers/CMSIS/Include/core_sc000.h index 9086c64..f315013 100644 --- a/Software/VNA_embedded/Drivers/CMSIS/Include/core_sc000.h +++ b/Software/VNA_embedded/Drivers/CMSIS/Include/core_sc000.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_sc000.h * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V5.0.5 - * @date 28. May 2018 + * @version V5.0.6 + * @date 12. November 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. @@ -81,7 +81,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif @@ -750,7 +750,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -904,6 +906,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ } diff --git a/Software/VNA_embedded/Drivers/CMSIS/Include/core_sc300.h b/Software/VNA_embedded/Drivers/CMSIS/Include/core_sc300.h index 665822d..ad031f2 100644 --- a/Software/VNA_embedded/Drivers/CMSIS/Include/core_sc300.h +++ b/Software/VNA_embedded/Drivers/CMSIS/Include/core_sc300.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_sc300.h * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V5.0.6 - * @date 04. June 2018 + * @version V5.0.8 + * @date 31. May 2019 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -81,7 +81,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif @@ -342,7 +342,7 @@ typedef struct __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; + uint32_t RESERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ @@ -653,13 +653,23 @@ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + /*@} end of group CMSIS_SCnotSCB */ @@ -739,10 +749,7 @@ typedef struct __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ @@ -793,18 +800,6 @@ typedef struct #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ @@ -1037,13 +1032,13 @@ typedef struct /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ @@ -1066,13 +1061,13 @@ typedef struct /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ @@ -1448,7 +1443,6 @@ typedef struct #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. @@ -1467,7 +1461,7 @@ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } @@ -1493,7 +1487,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -1716,8 +1712,9 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ } @@ -1731,8 +1728,8 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); } diff --git a/Software/VNA_embedded/Drivers/CMSIS/Include/mpu_armv7.h b/Software/VNA_embedded/Drivers/CMSIS/Include/mpu_armv7.h index 7d4b600..337eb65 100644 --- a/Software/VNA_embedded/Drivers/CMSIS/Include/mpu_armv7.h +++ b/Software/VNA_embedded/Drivers/CMSIS/Include/mpu_armv7.h @@ -1,11 +1,11 @@ /****************************************************************************** * @file mpu_armv7.h * @brief CMSIS MPU API for Armv7-M MPU - * @version V5.0.4 - * @date 10. January 2018 + * @version V5.1.0 + * @date 08. March 2019 ******************************************************************************/ /* - * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -86,10 +86,10 @@ * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. */ #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ - ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ - (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ - (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ - (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) /** * MPU Region Attribute and Size Register Value @@ -100,11 +100,14 @@ * \param SubRegionDisable Sub-region disable field. * \param Size Region size of the region to be configured, for example 4K, 8K. */ -#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ - ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ - (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ - (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) - +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + /** * MPU Region Attribute and Size Register Value * @@ -131,7 +134,7 @@ /** * MPU Memory Access Attribute for device memory. -* - TEX: 000b (if non-shareable) or 010b (if shareable) +* - TEX: 000b (if shareable) or 010b (if non-shareable) * - Shareable or non-shareable * - Non-cacheable * - Bufferable (if shareable) or non-bufferable (if non-shareable) @@ -187,20 +190,19 @@ typedef struct { */ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) { - __DSB(); - __ISB(); MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; #endif + __DSB(); + __ISB(); } /** Disable the MPU. */ __STATIC_INLINE void ARM_MPU_Disable(void) { - __DSB(); - __ISB(); + __DMB(); #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif @@ -243,7 +245,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t r * \param src Source data is copied from. * \param len Amount of data words to be copied. */ -__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; for (i = 0U; i < len; ++i) @@ -260,11 +262,11 @@ __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; while (cnt > MPU_TYPE_RALIASES) { - orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); table += MPU_TYPE_RALIASES; cnt -= MPU_TYPE_RALIASES; } - orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); } #endif diff --git a/Software/VNA_embedded/Drivers/CMSIS/Include/mpu_armv8.h b/Software/VNA_embedded/Drivers/CMSIS/Include/mpu_armv8.h index 99ee9f9..2fe28b6 100644 --- a/Software/VNA_embedded/Drivers/CMSIS/Include/mpu_armv8.h +++ b/Software/VNA_embedded/Drivers/CMSIS/Include/mpu_armv8.h @@ -1,11 +1,11 @@ /****************************************************************************** * @file mpu_armv8.h - * @brief CMSIS MPU API for Armv8-M MPU - * @version V5.0.4 - * @date 10. January 2018 + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 ******************************************************************************/ /* - * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -101,6 +101,21 @@ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ (MPU_RLAR_EN_Msk)) +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + /** * Struct for a single MPU Region */ @@ -114,20 +129,19 @@ typedef struct { */ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) { - __DSB(); - __ISB(); MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; #endif + __DSB(); + __ISB(); } /** Disable the MPU. */ __STATIC_INLINE void ARM_MPU_Disable(void) { - __DSB(); - __ISB(); + __DMB(); #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif @@ -140,20 +154,19 @@ __STATIC_INLINE void ARM_MPU_Disable(void) */ __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) { - __DSB(); - __ISB(); MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; #endif + __DSB(); + __ISB(); } /** Disable the Non-secure MPU. */ __STATIC_INLINE void ARM_MPU_Disable_NS(void) { - __DSB(); - __ISB(); + __DMB(); #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif @@ -267,7 +280,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t * \param src Source data is copied from. * \param len Amount of data words to be copied. */ -__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; for (i = 0U; i < len; ++i) @@ -287,7 +300,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; if (cnt == 1U) { mpu->RNR = rnr; - orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); } else { uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; @@ -295,7 +308,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ mpu->RNR = rnrBase; while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { uint32_t c = MPU_TYPE_RALIASES - rnrOffset; - orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); table += c; cnt -= c; rnrOffset = 0U; @@ -303,7 +316,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ mpu->RNR = rnrBase; } - orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); } } diff --git a/Software/VNA_embedded/Drivers/CMSIS/LICENSE.txt b/Software/VNA_embedded/Drivers/CMSIS/LICENSE.txt new file mode 100644 index 0000000..c0ee812 --- /dev/null +++ b/Software/VNA_embedded/Drivers/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright {yyyy} {name of copyright owner} + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 861e121..aca5b00 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -23,7 +22,7 @@ #define STM32_HAL_LEGACY #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -38,7 +37,14 @@ #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR - +#if defined(STM32U5) +#define CRYP_DATATYPE_32B CRYP_NO_SWAP +#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP +#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP +#define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF +#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF +#endif /* STM32U5 */ /** * @} */ @@ -207,6 +213,20 @@ * @{ */ #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +#if defined(STM32U5) +#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE +#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE +#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup CRC_Aliases CRC API aliases + * @{ + */ +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ /** * @} */ @@ -236,12 +256,19 @@ #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) -#define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH) -#define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH) +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif -#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) +#if defined(STM32U5) +#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 +#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #endif @@ -306,8 +333,22 @@ #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#endif + #endif /* STM32L4 */ +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM +#endif + #if defined(STM32H7) #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 @@ -365,8 +406,10 @@ #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT -#endif /* STM32H7 */ +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT +#endif /* STM32H7 */ /** * @} */ @@ -454,13 +497,24 @@ #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE #endif #if defined(STM32H7) -#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 -#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 -#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 -#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 -#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 -#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 -#endif +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ +#if defined(STM32U5) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U5 */ /** * @} @@ -503,6 +557,7 @@ #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ + /** * @} */ @@ -564,33 +619,54 @@ #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 -#endif + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ +#endif /* STM32H7 */ #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ #if defined(STM32L1) - #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L1 */ #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH #endif /* STM32F0 || STM32F3 || STM32F1 */ #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 + +#if defined(STM32U5) +#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose + * @{ + */ +#if defined(STM32U5) +#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#endif /* STM32U5 */ /** * @} */ @@ -622,7 +698,140 @@ #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL #endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) + +#endif /* STM32F3 */ /** * @} */ @@ -695,6 +904,31 @@ #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines LL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define LL_LPTIM_SetCompareCH1 LL_LPTIM_OC_SetCompareCH1 +#define LL_LPTIM_SetCompareCH2 LL_LPTIM_OC_SetCompareCH2 +#define LL_LPTIM_GetCompareCH1 LL_LPTIM_OC_GetCompareCH1 +#define LL_LPTIM_GetCompareCH2 LL_LPTIM_OC_GetCompareCH2 +/** + * @} + */ + +#if defined(STM32U5) +#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF +#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#define LPTIM_CHANNEL_ALL 0x00000000U +#endif /* STM32U5 */ /** * @} */ @@ -762,11 +996,16 @@ #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 -#if defined(STM32L1) || defined(STM32L4) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif +#if defined(STM32L4) || defined(STM32L5) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER +#elif defined(STM32G4) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED +#endif /** * @} @@ -778,15 +1017,15 @@ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS #if defined(STM32H7) - #define I2S_IT_TXE I2S_IT_TXP - #define I2S_IT_RXNE I2S_IT_RXP +#define I2S_IT_TXE I2S_IT_TXP +#define I2S_IT_RXNE I2S_IT_RXP - #define I2S_FLAG_TXE I2S_FLAG_TXP - #define I2S_FLAG_RXNE I2S_FLAG_RXP +#define I2S_FLAG_TXE I2S_FLAG_TXP +#define I2S_FLAG_RXNE I2S_FLAG_RXP #endif #if defined(STM32F7) - #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #endif /** * @} @@ -853,6 +1092,16 @@ #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT + +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL +#endif /* STM32H7 */ + /** * @} */ @@ -911,16 +1160,16 @@ #if defined(STM32H7) - #define SPI_FLAG_TXE SPI_FLAG_TXP - #define SPI_FLAG_RXNE SPI_FLAG_RXP +#define SPI_FLAG_TXE SPI_FLAG_TXP +#define SPI_FLAG_RXNE SPI_FLAG_RXP - #define SPI_IT_TXE SPI_IT_TXP - #define SPI_IT_RXNE SPI_IT_RXP +#define SPI_IT_TXE SPI_IT_TXP +#define SPI_IT_RXNE SPI_IT_RXP - #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET - #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET - #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET - #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET +#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET +#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET +#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET +#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET #endif /* STM32H7 */ @@ -1206,6 +1455,20 @@ */ #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) || defined(STM32U5) +/** @defgroup DMA2D_Aliases DMA2D API Aliases + * @{ + */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ +/** + * @} + */ + +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ + /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ */ @@ -1224,6 +1487,29 @@ * @} */ +/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose + * @{ + */ + +#if defined(STM32U5) +#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr +#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT +#endif /* STM32U5 */ + +/** + * @} + */ + +#if !defined(STM32F2) +/** @defgroup HASH_alias HASH API alias + * @{ + */ +#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ +/** + * + * @} + */ +#endif /* STM32F2 */ /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose * @{ */ @@ -1246,6 +1532,30 @@ #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ /** * @} */ @@ -1259,7 +1569,8 @@ #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode -#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) #if defined(STM32L0) @@ -1267,7 +1578,15 @@ #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) -#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + /** * @} */ @@ -1283,9 +1602,9 @@ #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program - /** +/** * @} - */ + */ /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose * @{ @@ -1295,18 +1614,21 @@ #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ + )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */ +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ #if defined(STM32F4) #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT @@ -1318,13 +1640,20 @@ #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA #endif /* STM32F4 */ - /** +/** * @} - */ + */ /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose * @{ */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown @@ -1368,9 +1697,9 @@ #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - /** +/** * @} - */ + */ /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ @@ -1397,14 +1726,14 @@ #define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4) +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA -#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */ +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ /** * @} */ @@ -1619,15 +1948,15 @@ #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC #if defined(STM32H7) - #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 - #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 - #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 - #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 #else - #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG - #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG - #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG - #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG #endif /* STM32H7 */ #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT @@ -1838,8 +2167,8 @@ */ #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ - ((WAVE) == DAC_WAVE_NOISE)|| \ - ((WAVE) == DAC_WAVE_TRIANGLE)) + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) /** * @} @@ -1895,7 +2224,7 @@ #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT #if defined(STM32H7) - #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG #endif /** @@ -2032,7 +2361,8 @@ #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE @@ -3000,9 +3330,8 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif @@ -3113,6 +3442,31 @@ #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 +#if defined(STM32U5) +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE +#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE +#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE +#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE +#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE +#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE +#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE +#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE +#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE +#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK +#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 +#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 +#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 +#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#endif /** * @} @@ -3130,7 +3484,7 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3150,19 +3504,19 @@ #else #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) #endif /* STM32F1 */ #define IS_ALARM IS_RTC_ALARM @@ -3187,13 +3541,22 @@ * @} */ -/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose +/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose * @{ */ #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1) +#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE +#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE +#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV +#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV +#endif + #if defined(STM32F4) || defined(STM32F2) #define SD_SDMMC_DISABLED SD_SDIO_DISABLED #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY @@ -3238,22 +3601,22 @@ #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT -#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS -#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT -#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND /* alias CMSIS for compatibilities */ #define SDIO_IRQn SDMMC1_IRQn #define SDIO_IRQHandler SDMMC1_IRQHandler #endif -#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef #endif -#if defined(STM32H7) +#if defined(STM32H7) || defined(STM32L5) #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback @@ -3346,6 +3709,13 @@ #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) +#define USART_OVERSAMPLING_16 0x00000000U +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 + +#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == USART_OVERSAMPLING_8)) +#endif /* STM32F0 || STM32F3 || STM32F7 */ /** * @} */ @@ -3494,12 +3864,12 @@ * @{ */ #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) -#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT -#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA -#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart -#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT -#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA -#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop #endif /** * @} @@ -3508,9 +3878,19 @@ /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32L4) +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE -#endif +#endif /* STM32L4 || STM32F4 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32F7) +#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE +#endif /* STM32F7 */ /** * @} */ @@ -3529,5 +3909,4 @@ #endif /* STM32_HAL_LEGACY */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h index d08b2aa..60a335b 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -461,7 +460,7 @@ extern "C" { ((__CONFIG__) == SYSCFG_BREAK_SRAMPARITY) || \ ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) -#if (CCMSRAM_SIZE == 0x00008000UL) +#if (CCMSRAM_SIZE == 0x00008000UL) || (CCMSRAM_SIZE == 0x00004000UL) #define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) ((__PAGE__) > 0U) #elif (CCMSRAM_SIZE == 0x00002800UL) #define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000003FFU)) @@ -623,4 +622,3 @@ void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page); #endif /* STM32G4xx_HAL_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h index 3ff136b..f0114a3 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -113,7 +112,7 @@ typedef struct 0 Gain compensation will be disabled and coefficient set to 0 1 -> 0x3FFF Gain compensation will be enabled and coefficient set to specified value - Note: Gain compensation when enabled is appied to all channels. */ + Note: Gain compensation when enabled is applied to all channels. */ uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. @@ -132,8 +131,8 @@ typedef struct This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. This parameter can be set to ENABLE or DISABLE. - Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag - to free the IRQ vector sequencer. + Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). + Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ @@ -251,7 +250,7 @@ typedef struct Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ - uint32_t OffsetSign; /*!< Define if the offset should be substracted (negative sign) or added (positive sign) from or to the raw converted data. + uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. This parameter can be a value of @ref ADCEx_OffsetSign. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ @@ -357,7 +356,7 @@ typedef struct external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ -#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 serie: End Of Sampling flag raised */ +#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */ /* States of ADC group injected */ #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, @@ -384,7 +383,7 @@ typedef struct typedef struct __ADC_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ { ADC_TypeDef *Instance; /*!< Register base address */ ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ @@ -499,7 +498,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ -#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ +#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ /** * @} */ @@ -666,17 +665,17 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ -#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 serie, ADC channel available on all instances but ADC2. */ -#define ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_TEMPSENSOR_ADC1) /*!< ADC internal channel connected to Temperature sensor. On this STM32 serie, ADC channel available only on ADC1 instance. */ -#define ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_TEMPSENSOR_ADC5) /*!< ADC internal channel connected to Temperature sensor. On this STM32 serie, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility */ -#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On this STM32 serie, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility */ -#define ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_VOPAMP1) /*!< ADC internal channel connected to OPAMP1 output. On this STM32 serie, ADC channel available only on ADC1 instance. */ -#define ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_VOPAMP2) /*!< ADC internal channel connected to OPAMP2 output. On this STM32 serie, ADC channel available only on ADC2 instance. */ -#define ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_VOPAMP3_ADC2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 serie, ADC channel available only on ADC2 instance. */ -#define ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_VOPAMP3_ADC3) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 serie, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */ -#define ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_VOPAMP4) /*!< ADC internal channel connected to OPAMP4 output. On this STM32 serie, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */ -#define ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_VOPAMP5) /*!< ADC internal channel connected to OPAMP5 output. On this STM32 serie, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */ -#define ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_VOPAMP6) /*!< ADC internal channel connected to OPAMP6 output. On this STM32 serie, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 availability */ +#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 series, ADC channel available on all instances but ADC2. */ +#define ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_TEMPSENSOR_ADC1) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC1 instance. */ +#define ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_TEMPSENSOR_ADC5) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility */ +#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On this STM32 series, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility */ +#define ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_VOPAMP1) /*!< ADC internal channel connected to OPAMP1 output. On this STM32 series, ADC channel available only on ADC1 instance. */ +#define ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_VOPAMP2) /*!< ADC internal channel connected to OPAMP2 output. On this STM32 series, ADC channel available only on ADC2 instance. */ +#define ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_VOPAMP3_ADC2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC2 instance. */ +#define ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_VOPAMP3_ADC3) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */ +#define ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_VOPAMP4) /*!< ADC internal channel connected to OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */ +#define ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_VOPAMP5) /*!< ADC internal channel connected to OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */ +#define ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_VOPAMP6) /*!< ADC internal channel connected to OPAMP6 output. On this STM32 series, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 availability */ /** * @} */ @@ -769,7 +768,6 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @} */ - /** @defgroup ADC_Event_type ADC Event type * @{ */ @@ -988,25 +986,25 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG10) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ - (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ + (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ - (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG4) || \ + (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ ((__REGTRIG__) == ADC_SOFTWARE_START) ) -#elif defined(STM32G473xx) +#elif defined(STM32G473xx) || defined(STM32G483xx) #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ @@ -1023,23 +1021,51 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ - (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ + (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ - (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ + (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ ((__REGTRIG__) == ADC_SOFTWARE_START) ) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) +#elif defined(STM32G471xx) +#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ + ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ + (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ + ((((__HANDLE__)->Instance == ADC3)) && \ + (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ + ((__REGTRIG__) == ADC_SOFTWARE_START) ) +#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ @@ -1059,6 +1085,39 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ ((__REGTRIG__) == ADC_SOFTWARE_START) ) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) +#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ + ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ + (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ + (((__HANDLE__)->Instance == ADC3) && \ + (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ + ((__REGTRIG__) == ADC_SOFTWARE_START) ) #endif /** @@ -1178,7 +1237,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #else #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ ((__HANDLE__)->State = HAL_ADC_STATE_RESET) -#endif +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @brief Enable ADC interrupt. @@ -1341,7 +1400,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval Value between Min_Data=0 and Max_Data=18 @@ -1395,7 +1454,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, @@ -1461,7 +1520,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). @@ -1522,7 +1581,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval Returned value can be one of the following values: @@ -1583,7 +1642,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. * Value "1" if the internal channel selected is available on the ADC instance selected. */ @@ -1606,7 +1665,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Helper macro to select the ADC common instance @@ -1677,10 +1736,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ __ADC_RESOLUTION_CURRENT__,\ - __ADC_RESOLUTION_TARGET__) \ - __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__), \ - (__ADC_RESOLUTION_CURRENT__), \ - (__ADC_RESOLUTION_TARGET__)) + __ADC_RESOLUTION_TARGET__) \ +__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ + (__ADC_RESOLUTION_CURRENT__),\ + (__ADC_RESOLUTION_TARGET__)) /** * @brief Helper macro to calculate the voltage (unit: mVolt) @@ -1700,10 +1759,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ __ADC_DATA__,\ - __ADC_RESOLUTION__) \ - __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__), \ - (__ADC_DATA__), \ - (__ADC_RESOLUTION__)) + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ + (__ADC_DATA__),\ + (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate analog reference voltage (Vref+) @@ -1715,7 +1774,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * connected to pin Vref+. * On devices with small package, the pin Vref+ is not present * and internally bonded to pin Vdda. - * @note On this STM32 serie, calibration data of internal voltage reference + * @note On this STM32 series, calibration data of internal voltage reference * VrefInt corresponds to a resolution of 12 bits, * this is the recommended ADC resolution to convert voltage of * internal voltage reference VrefInt. @@ -1731,9 +1790,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @retval Analog reference voltage (unit: mV) */ #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__), \ - (__ADC_RESOLUTION__)) + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ + (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) @@ -1762,7 +1821,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @note On this STM32 serie, calibration data of temperature sensor + * @note On this STM32 series, calibration data of temperature sensor * corresponds to a resolution of 12 bits, * this is the recommended ADC resolution to convert voltage of * temperature sensor. @@ -1782,10 +1841,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__), \ - (__TEMPSENSOR_ADC_DATA__), \ - (__ADC_RESOLUTION__)) + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ + (__TEMPSENSOR_ADC_DATA__),\ + (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) @@ -1836,13 +1895,13 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to __TEMPSENSOR_CALX_TEMP__,\ __VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__), \ - (__TEMPSENSOR_TYP_CALX_V__), \ - (__TEMPSENSOR_CALX_TEMP__), \ - (__VREFANALOG_VOLTAGE__), \ - (__TEMPSENSOR_ADC_DATA__), \ - (__ADC_RESOLUTION__)) + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ + (__TEMPSENSOR_TYP_CALX_V__),\ + (__TEMPSENSOR_CALX_TEMP__),\ + (__VREFANALOG_VOLTAGE__),\ + (__TEMPSENSOR_ADC_DATA__),\ + (__ADC_RESOLUTION__)) /** * @} @@ -1973,5 +2032,3 @@ void ADC_DMAError(DMA_HandleTypeDef *hdma); #endif /* STM32G4xx_HAL_ADC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h index 3d9b4a4..d2da2c2 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -114,7 +113,7 @@ typedef struct Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ - uint32_t InjectedOffsetSign; /*!< Define if the offset should be substracted (negative sign) or added (positive sign) from or to the raw converted data. + uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. This parameter can be a value of @ref ADCEx_OffsetSign. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ FunctionalState InjectedOffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. @@ -293,7 +292,7 @@ typedef struct /** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign * @{ */ -#define ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< Offset sign negative, offset is substracted */ +#define ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< Offset sign negative, offset is subtracted */ #define ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< Offset sign positive, offset is added */ /** * @} @@ -393,7 +392,7 @@ typedef struct ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ ADC_SMPR1_SMP0) -#endif +#endif /* ADC_SMPR1_SMPPLUS */ /** * @} */ @@ -429,7 +428,7 @@ typedef struct * Usage of this macro is not the Standard way of multimode * configuration and can lead to have HAL ADC handles status * misaligned. Usage of this macro must be limited to cases - * mentionned above. + * mentioned above. * @param __HANDLE__ ADC handle. * @retval None */ @@ -464,17 +463,25 @@ typedef struct * @note When multimode feature is not available, the macro always returns SET. * @retval SET (ADC is independent) or RESET (ADC is not). */ -#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) +#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define ADC_IS_INDEPENDENT(__HANDLE__) \ ( ( ( ((__HANDLE__)->Instance) == ADC5) \ )? \ - SET \ - : \ - RESET \ + SET \ + : \ + RESET \ + ) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) +#define ADC_IS_INDEPENDENT(__HANDLE__) \ + ( ( ( ((__HANDLE__)->Instance) == ADC3) \ + )? \ + SET \ + : \ + RESET \ ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) #define ADC_IS_INDEPENDENT(__HANDLE__) (RESET) -#endif +#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ /** * @brief Set the selected injected Channel rank. @@ -482,7 +489,8 @@ typedef struct * @param __RANKNB__ Rank number. * @retval None */ -#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) +#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__)\ + & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) /** * @brief Configure ADC injected context queue @@ -607,7 +615,7 @@ typedef struct ADC_CCR_DUAL) #endif /* ADC_MULTIMODE_SUPPORT */ -#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) +#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) /** * @brief Set handle instance of the ADC slave associated to the ADC master. * @param __HANDLE_MASTER__ ADC master handle. @@ -624,7 +632,7 @@ typedef struct : \ ((__HANDLE_SLAVE__)->Instance = NULL) \ ) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) +#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) /** * @brief Set handle instance of the ADC slave associated to the ADC master. * @param __HANDLE_MASTER__ ADC master handle. @@ -646,21 +654,23 @@ typedef struct * @param __HANDLE__ ADC handle. * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) */ -#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) +#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC5)) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) +#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) -#endif +#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ /** * @brief Verify the ADC instance connected to the battery voltage VBAT. * @param __HANDLE__ ADC handle. * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) */ -#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) +#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) != ADC2) || (((__HANDLE__)->Instance) != ADC4)) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) +#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) #endif /** @@ -691,7 +701,7 @@ typedef struct * @param __CHANNEL__ programmed ADC channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ -#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) +#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_6) || \ @@ -743,7 +753,37 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_16) || \ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) +#elif defined(STM32G471xx) +#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ + ((__CHANNEL__) == ADC_CHANNEL_2) || \ + ((__CHANNEL__) == ADC_CHANNEL_3) || \ + ((__CHANNEL__) == ADC_CHANNEL_4) || \ + ((__CHANNEL__) == ADC_CHANNEL_5) || \ + ((__CHANNEL__) == ADC_CHANNEL_6) || \ + ((__CHANNEL__) == ADC_CHANNEL_7) || \ + ((__CHANNEL__) == ADC_CHANNEL_8) || \ + ((__CHANNEL__) == ADC_CHANNEL_9) || \ + ((__CHANNEL__) == ADC_CHANNEL_10) || \ + ((__CHANNEL__) == ADC_CHANNEL_11) || \ + ((__CHANNEL__) == ADC_CHANNEL_12) || \ + ((__CHANNEL__) == ADC_CHANNEL_14) || \ + ((__CHANNEL__) == ADC_CHANNEL_15)) || \ + ((((__HANDLE__)->Instance) == ADC1) && \ + (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \ + ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \ + ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ + ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ + ((((__HANDLE__)->Instance) == ADC2) && \ + (((__CHANNEL__) == ADC_CHANNEL_13) || \ + ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \ + ((__CHANNEL__) == ADC_CHANNEL_17) || \ + ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \ + ((((__HANDLE__)->Instance) == ADC3) && \ + (((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \ + ((__CHANNEL__) == ADC_CHANNEL_16) || \ + ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ + ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))) +#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ @@ -768,7 +808,37 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \ ((__CHANNEL__) == ADC_CHANNEL_17) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2)))) -#endif +#elif defined(STM32G491xx) || defined(STM32G4A1xx) +#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ + ((__CHANNEL__) == ADC_CHANNEL_2) || \ + ((__CHANNEL__) == ADC_CHANNEL_3) || \ + ((__CHANNEL__) == ADC_CHANNEL_4) || \ + ((__CHANNEL__) == ADC_CHANNEL_5) || \ + ((__CHANNEL__) == ADC_CHANNEL_6) || \ + ((__CHANNEL__) == ADC_CHANNEL_7) || \ + ((__CHANNEL__) == ADC_CHANNEL_8) || \ + ((__CHANNEL__) == ADC_CHANNEL_9) || \ + ((__CHANNEL__) == ADC_CHANNEL_10) || \ + ((__CHANNEL__) == ADC_CHANNEL_11) || \ + ((__CHANNEL__) == ADC_CHANNEL_12) || \ + ((__CHANNEL__) == ADC_CHANNEL_14) || \ + ((__CHANNEL__) == ADC_CHANNEL_15)) || \ + ((((__HANDLE__)->Instance) == ADC1) && \ + (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \ + ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \ + ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ + ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ + ((((__HANDLE__)->Instance) == ADC2) && \ + (((__CHANNEL__) == ADC_CHANNEL_13) || \ + ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \ + ((__CHANNEL__) == ADC_CHANNEL_17) || \ + ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \ + ((((__HANDLE__)->Instance) == ADC3) && \ + (((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \ + ((__CHANNEL__) == ADC_CHANNEL_16) || \ + ((__CHANNEL__) == ADC_CHANNEL_VOPAMP6) || \ + ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))) +#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ /** * @brief Verify the ADC channel setting in differential mode. @@ -776,7 +846,7 @@ typedef struct * @param __CHANNEL__ programmed ADC channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ -#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) +#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_6) || \ ((__CHANNEL__) == ADC_CHANNEL_7) || \ @@ -815,7 +885,25 @@ typedef struct (((__CHANNEL__) == ADC_CHANNEL_12) || \ ((__CHANNEL__) == ADC_CHANNEL_13) || \ ((__CHANNEL__) == ADC_CHANNEL_15))) ) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) +#elif defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) +#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ + (((__CHANNEL__) == ADC_CHANNEL_2) || \ + ((__CHANNEL__) == ADC_CHANNEL_3) || \ + ((__CHANNEL__) == ADC_CHANNEL_4) || \ + ((__CHANNEL__) == ADC_CHANNEL_5) || \ + ((__CHANNEL__) == ADC_CHANNEL_6) || \ + ((__CHANNEL__) == ADC_CHANNEL_7) || \ + ((__CHANNEL__) == ADC_CHANNEL_8) || \ + ((__CHANNEL__) == ADC_CHANNEL_9) || \ + ((__CHANNEL__) == ADC_CHANNEL_10) || \ + ((__CHANNEL__) == ADC_CHANNEL_11) || \ + ((__CHANNEL__) == ADC_CHANNEL_14)) || \ + ((((__HANDLE__)->Instance) == ADC2) && \ + (((__CHANNEL__) == ADC_CHANNEL_12) || \ + ((__CHANNEL__) == ADC_CHANNEL_13))) || \ + ((((__HANDLE__)->Instance) == ADC3) && \ + ((__CHANNEL__) == ADC_CHANNEL_15))) ) +#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ @@ -901,24 +989,24 @@ typedef struct ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG10) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ - (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ + (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ - (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG3) || \ + (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) -#elif defined(STM32G473xx) +#elif defined(STM32G473xx) || defined(STM32G483xx) #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ @@ -935,22 +1023,50 @@ typedef struct ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ - (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ + (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ - (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \ + (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) +#elif defined(STM32G471xx) +#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ + ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ + (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ + ((((__HANDLE__)->Instance == ADC3)) && \ + (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ + ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) +#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ @@ -971,6 +1087,38 @@ typedef struct ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) +#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ + ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ + (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ + (((__HANDLE__)->Instance == ADC3) && \ + (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ + ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) #endif /** @@ -1212,7 +1360,8 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected); +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, + ADC_InjectionConfTypeDef *sConfigInjected); #if defined(ADC_MULTIMODE_SUPPORT) HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); #endif /* ADC_MULTIMODE_SUPPORT */ @@ -1242,6 +1391,3 @@ HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *h #endif #endif /* STM32G4xx_HAL_ADC_EX_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h index e97367e..c55a859 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -418,4 +417,3 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #endif /* __STM32G4xx_HAL_CORTEX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h index 60f4721..c16f6c7 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -107,7 +106,14 @@ typedef enum }while (0U) #endif /* USE_RTOS */ -#if defined ( __GNUC__ ) +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif +#ifndef __packed +#define __packed __attribute__((packed)) +#endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __weak #define __weak __attribute__((weak)) #endif /* __weak */ @@ -118,7 +124,14 @@ typedef enum /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ -#if defined (__GNUC__) /* GNU Compiler */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4))) +#endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4U))) #endif /* __ALIGN_END */ @@ -130,7 +143,7 @@ typedef enum #define __ALIGN_END #endif /* __ALIGN_END */ #ifndef __ALIGN_BEGIN -#if defined (__CC_ARM) /* ARM Compiler */ +#if defined (__CC_ARM) /* ARM Compiler V5*/ #define __ALIGN_BEGIN __align(4U) #elif defined (__ICCARM__) /* IAR Compiler */ #define __ALIGN_BEGIN @@ -141,9 +154,9 @@ typedef enum /** * @brief __RAM_FUNC definition */ -#if defined ( __CC_ARM ) -/* ARM Compiler - ------------ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +/* ARM Compiler V4/V5 and V6 + -------------------------- RAM functions are defined using the toolchain options. Functions that are executed in RAM should reside in a separate source module. Using the 'Options for File' dialog you can simply change the 'Code / Const' @@ -173,9 +186,9 @@ typedef enum /** * @brief __NOINLINE definition */ -#if defined ( __CC_ARM ) || defined ( __GNUC__ ) -/* ARM & GNUCompiler - ---------------- +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +/* ARM V4/V5 and V6 & GNU Compiler + ------------------------------- */ #define __NOINLINE __attribute__ ( (noinline) ) @@ -194,4 +207,3 @@ typedef enum #endif /* ___STM32G4xx_HAL_DEF */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h index c61cc7d..0e6eecf 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -851,4 +850,3 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); #endif /* __STM32G4xx_HAL_DMA_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h index 74b4d07..ac8d562 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -263,4 +262,3 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); #endif /* __STM32G4xx_HAL_DMA_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h index cf17386..afde61d 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -228,19 +227,19 @@ typedef struct /** @defgroup EXTI_Private_Macros EXTI Private Macros * @{ */ -#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \ - ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ - (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ - (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ - (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ - (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u)))) +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \ + ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ + (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u)))) -#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00U) && \ - (((__LINE__) & ~EXTI_MODE_MASK) == 0x00U)) +#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00U) && \ + (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00U)) -#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U) +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U) -#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00U) +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U) #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ ((__PORT__) == EXTI_GPIOB) || \ @@ -314,4 +313,3 @@ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); #endif /* STM32G4xx_HAL_EXTI_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h index 72c137c..f13aa0b 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -273,6 +272,9 @@ typedef struct #define OB_USER_BFB2 0x00000080U /*!< Dual-bank boot */ #define OB_USER_DBANK 0x00000100U /*!< Single bank with 128-bits data or two banks with 64-bits data */ #endif +#if defined (FLASH_OPTR_PB4_PUPEN) +#define OB_USER_PB4_PUPEN 0x00000100U /*!< USB power delivery dead-battery/TDI pull-up */ +#endif #define OB_USER_nBOOT1 0x00000200U /*!< Boot configuration */ #define OB_USER_SRAM_PE 0x00000400U /*!< SRAM parity check enable (first 32kB of SRAM1 + CCM SRAM) */ #define OB_USER_CCMSRAM_RST 0x00000800U /*!< CCMSRAM Erase when system reset */ @@ -380,6 +382,17 @@ typedef struct */ #endif +#if defined (FLASH_OPTR_PB4_PUPEN) +/** @defgroup FLASH_OB_USER_PB4_PUPEN FLASH Option Bytes User PB4 PUPEN bit + * @{ + */ +#define OB_PB4_PUPEN_DISABLE 0x00000000U /*!< USB power delivery dead-battery enabled/ TDI pull-up deactivated */ +#define OB_PB4_PUPEN_ENABLE FLASH_OPTR_PB4_PUPEN /*!< USB power delivery dead-battery disabled/ TDI pull-up activated */ +/** + * @} + */ +#endif + /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type * @{ */ @@ -558,14 +571,22 @@ typedef struct * @brief Set the FLASH Latency. * @param __LATENCY__ FLASH Latency. * This parameter can be one of the following values : - * @arg FLASH_LATENCY_0: FLASH Zero wait state - * @arg FLASH_LATENCY_1: FLASH One wait state - * @arg FLASH_LATENCY_2: FLASH Two wait states - * @arg FLASH_LATENCY_3: FLASH Three wait states - * @arg FLASH_LATENCY_4: FLASH Four wait states - * @arg FLASH_LATENCY_5: FLASH Five wait states - * @arg FLASH_LATENCY_6: FLASH Six wait states - * @arg FLASH_LATENCY_7: FLASH Seven wait states + * @arg FLASH_LATENCY_0: FLASH Zero wait state + * @arg FLASH_LATENCY_1: FLASH One wait state + * @arg FLASH_LATENCY_2: FLASH Two wait states + * @arg FLASH_LATENCY_3: FLASH Three wait states + * @arg FLASH_LATENCY_4: FLASH Four wait states + * @arg FLASH_LATENCY_5: FLASH Five wait states + * @arg FLASH_LATENCY_6: FLASH Six wait states + * @arg FLASH_LATENCY_7: FLASH Seven wait states + * @arg FLASH_LATENCY_8: FLASH Eight wait states + * @arg FLASH_LATENCY_9: FLASH Nine wait states + * @arg FLASH_LATENCY_10: FLASH Ten wait state + * @arg FLASH_LATENCY_11: FLASH Eleven wait state + * @arg FLASH_LATENCY_12: FLASH Twelve wait states + * @arg FLASH_LATENCY_13: FLASH Thirteen wait states + * @arg FLASH_LATENCY_14: FLASH Fourteen wait states + * @arg FLASH_LATENCY_15: FLASH Fifteen wait states * @retval None */ #define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)) @@ -574,14 +595,22 @@ typedef struct * @brief Get the FLASH Latency. * @retval FLASH_Latency. * This parameter can be one of the following values : - * @arg FLASH_LATENCY_0: FLASH Zero wait state - * @arg FLASH_LATENCY_1: FLASH One wait state - * @arg FLASH_LATENCY_2: FLASH Two wait states - * @arg FLASH_LATENCY_3: FLASH Three wait states - * @arg FLASH_LATENCY_4: FLASH Four wait states - * @arg FLASH_LATENCY_5: FLASH Five wait states - * @arg FLASH_LATENCY_6: FLASH Six wait states - * @arg FLASH_LATENCY_7: FLASH Seven wait states + * @arg FLASH_LATENCY_0: FLASH Zero wait state + * @arg FLASH_LATENCY_1: FLASH One wait state + * @arg FLASH_LATENCY_2: FLASH Two wait states + * @arg FLASH_LATENCY_3: FLASH Three wait states + * @arg FLASH_LATENCY_4: FLASH Four wait states + * @arg FLASH_LATENCY_5: FLASH Five wait states + * @arg FLASH_LATENCY_6: FLASH Six wait states + * @arg FLASH_LATENCY_7: FLASH Seven wait states + * @arg FLASH_LATENCY_8: FLASH Eight wait states + * @arg FLASH_LATENCY_9: FLASH Nine wait states + * @arg FLASH_LATENCY_10: FLASH Ten wait state + * @arg FLASH_LATENCY_11: FLASH Eleven wait state + * @arg FLASH_LATENCY_12: FLASH Twelve wait states + * @arg FLASH_LATENCY_13: FLASH Thirteen wait states + * @arg FLASH_LATENCY_14: FLASH Fourteen wait states + * @arg FLASH_LATENCY_15: FLASH Fifteen wait states */ #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) @@ -850,7 +879,8 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x80UL << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U)) #define FLASH_BANK_SIZE (FLASH_SIZE) -#define FLASH_PAGE_NB 64U +#define FLASH_PAGE_NB ((FLASH_SIZE == 0x00080000U) ? 256U : \ + ((FLASH_SIZE == 0x00040000U) ? 128U : 64U)) #endif #define FLASH_PAGE_SIZE 0x800U /* 2 KB */ @@ -936,6 +966,10 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS)) #endif +#if defined (FLASH_OPTR_PB4_PUPEN) +#define IS_OB_USER_PB4_PUPEN(VALUE) (((VALUE) == OB_PB4_PUPEN_DISABLE) || ((VALUE) == OB_PB4_PUPEN_ENABLE)) +#endif + #define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM)) #define IS_OB_USER_SRAM_PARITY(VALUE) (((VALUE) == OB_SRAM_PARITY_ENABLE) || ((VALUE) == OB_SRAM_PARITY_DISABLE)) @@ -981,4 +1015,3 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #endif /* STM32G4xx_HAL_FLASH_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h index b65d855..b785f6f 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -88,4 +87,3 @@ void FLASH_FlushCaches(void); #endif /* STM32G4xx_HAL_FLASH_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h index 738c536..3f0f1bb 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -73,4 +72,3 @@ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig); #endif /* STM32G4xx_FLASH_RAMFUNC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h index 5123ff7..1b710c1 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -107,26 +106,28 @@ typedef enum /** @defgroup GPIO_mode GPIO mode * @brief GPIO Configuration Mode - * Elements values convention: 0xX0yz00YZ - * - X : GPIO mode or EXTI Mode - * - y : External IT or Event trigger detection - * - z : IO configuration on External IT or Event - * - Y : Output type (Push Pull or Open Drain) - * - Z : IO Direction mode (Input, Output, Alternate or Analog) + * Elements values convention: 0x00WX00YZ + * - W : EXTI trigger detection on 3 bits + * - X : EXTI mode (IT or Event) on 2 bits + * - Y : Output type (Push Pull or Open Drain) on 1 bit + * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits * @{ - */ -#define GPIO_MODE_INPUT (0x00000000U) /*!< Input Floating Mode */ -#define GPIO_MODE_OUTPUT_PP (0x00000001U) /*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_OD (0x00000011U) /*!< Output Open Drain Mode */ -#define GPIO_MODE_AF_PP (0x00000002U) /*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_OD (0x00000012U) /*!< Alternate Function Open Drain Mode */ -#define GPIO_MODE_ANALOG (0x00000003U) /*!< Analog Mode */ -#define GPIO_MODE_IT_RISING (0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_FALLING (0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING (0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING (0x10120000U) /*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_FALLING (0x10220000U) /*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */ + */ +#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ + +#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ + +#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + +#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ /** * @} */ @@ -208,13 +209,38 @@ typedef enum */ /* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_MODE_Pos 0U +#define GPIO_MODE (0x3UL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0UL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos) +#define MODE_AF (0x2UL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4U +#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16U +#define EXTI_MODE (0x3UL << EXTI_MODE_Pos) +#define EXTI_IT (0x1UL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2UL << EXTI_MODE_Pos) +#define TRIGGER_MODE_Pos 20U +#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos) +/** + * @} + */ + /** @defgroup GPIO_Private_Macros GPIO Private Macros * @{ */ #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) -#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ - (((__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ + (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) #define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ @@ -298,4 +324,3 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); #endif /* STM32G4xx_HAL_GPIO_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h index 38ec27a..ec466f9 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -82,6 +81,7 @@ extern "C" { #endif /* TIM5 */ #define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */ #define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /* TIM16 Alternate Function mapping */ #if defined(TIM20) #define GPIO_AF2_TIM20 ((uint8_t)0x02) /* TIM20 Alternate Function mapping */ #endif /* TIM20 */ @@ -214,6 +214,7 @@ extern "C" { * @brief AF 9 selection */ #define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */ +#define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */ #define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */ #define GPIO_AF9_TIM1_COMP1 ((uint8_t)0x09) /* TIM1/COMP1 Break in Alternate Function mapping */ #define GPIO_AF9_TIM8_COMP1 ((uint8_t)0x09) /* TIM8/COMP1 Break in Alternate Function mapping */ @@ -245,6 +246,7 @@ extern "C" { #define GPIO_AF11_FDCAN3 ((uint8_t)0x0B) /* FDCAN3 Alternate Function mapping */ #endif /* FDCAN3 */ #define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */ +#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */ #define GPIO_AF11_TIM8_COMP1 ((uint8_t)0x0B) /* TIM8/COMP1 Break in Alternate Function mapping */ #define GPIO_AF11_LPTIM1 ((uint8_t)0x0B) /* LPTIM1 Alternate Function mapping */ @@ -252,7 +254,8 @@ extern "C" { * @brief AF 12 selection */ #define GPIO_AF12_LPUART1 ((uint8_t)0x0C) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */ +#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */ +#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */ #define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */ #if defined(HRTIM1) #define GPIO_AF12_HRTIM1 ((uint8_t)0x0C) /* HRTIM1 Alternate Function mapping */ @@ -335,4 +338,3 @@ extern "C" { #endif /* STM32G4xx_HAL_GPIO_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h index 9968e12..a2ae591 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -48,29 +47,30 @@ extern "C" { typedef struct { uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. - This parameter calculated by referring to I2C initialization - section in Reference manual */ + This parameter calculated by referring to I2C initialization section + in Reference manual */ uint32_t OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ + This parameter can be a 7-bit or 10-bit address. */ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. - This parameter can be a value of @ref I2C_ADDRESSING_MODE */ + This parameter can be a value of @ref I2C_ADDRESSING_MODE */ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ + This parameter can be a 7-bit address. */ - uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected - This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing + mode is selected. + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ + This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ + This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ } I2C_InitTypeDef; @@ -200,7 +200,8 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t PreviousState; /*!< I2C communication Previous state */ - HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); + /*!< I2C transfer IRQ handler function pointer */ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ @@ -217,20 +218,32 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */ - void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */ - void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */ - void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */ - void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */ - void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */ - void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */ - void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */ - void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */ + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Abort callback */ - void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */ + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< I2C Slave Address Match callback */ - void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */ - void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */ + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp DeInit callback */ #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } I2C_HandleTypeDef; @@ -259,8 +272,11 @@ typedef enum /** * @brief HAL I2C Callback pointer definition */ -typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */ -typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); +/*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an I2C Address Match callback function */ #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ /** @@ -440,14 +456,14 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * @retval None */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) -#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) -#endif +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ /** @brief Enable the specified I2C interrupt. * @param __HANDLE__ specifies the I2C Handle. @@ -495,7 +511,8 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified I2C flag is set or not. * @param __HANDLE__ specifies the I2C Handle. @@ -521,7 +538,8 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * @retval The new state of __FLAG__ (SET or RESET). */ #define I2C_FLAG_MASK (0x0001FFFFU) -#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \ + (__FLAG__)) == (__FLAG__)) ? SET : RESET) /** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the I2C Handle. @@ -540,26 +558,27 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * * @retval None */ -#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ - : ((__HANDLE__)->Instance->ICR = (__FLAG__))) +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) /** @brief Enable the specified I2C peripheral. * @param __HANDLE__ specifies the I2C Handle. * @retval None */ -#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) +#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Disable the specified I2C peripheral. * @param __HANDLE__ specifies the I2C Handle. * @retval None */ -#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) +#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. * @param __HANDLE__ specifies the I2C Handle. * @retval None */ -#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) +#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) /** * @} */ @@ -583,7 +602,8 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); @@ -598,49 +618,72 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); */ /* IO operation functions ****************************************************/ /******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout); /******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); /******* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); /** * @} */ /** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ + * @{ + */ /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); @@ -732,10 +775,15 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) -#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ + I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ + I2C_CR2_RD_WRN))) -#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)) -#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)) +#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \ + >> 16U)) +#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \ + >> 16U)) #define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) #define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) #define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) @@ -743,13 +791,20 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) #define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) -#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U))) +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \ + (uint16_t)(0xFF00U))) >> 8U))) #define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) -#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ + (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_ADD10) | (I2C_CR2_START)) & \ + (~I2C_CR2_RD_WRN))) -#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ + ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) #define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) /** * @} @@ -778,5 +833,3 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #endif /* STM32G4xx_HAL_I2C_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h index 1b5fd8c..9fda573 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -38,7 +37,6 @@ extern "C" { /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ - /** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants * @{ */ @@ -67,7 +65,7 @@ extern "C" { #define I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ #else #define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */ -#endif +#endif /* SYSCFG_CFGR1_I2C4_FMP */ /** * @} */ @@ -77,24 +75,50 @@ extern "C" { */ /* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros + * @{ + */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ /** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions * @{ */ -/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions +/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions * @{ */ - /* Peripheral Control functions ************************************************/ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @{ + */ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @{ + */ void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); +/** + * @} + */ + +/** + * @} + */ /* Private constants ---------------------------------------------------------*/ /** @defgroup I2CEx_Private_Constants I2C Extended Private Constants @@ -110,7 +134,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); * @{ */ #define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ - ((FILTER) == I2C_ANALOGFILTER_DISABLE)) + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) #define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) @@ -144,18 +168,8 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); * @} */ -/** - * @} - */ - -/** - * @} - */ - #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_I2C_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h index 7d88f65..48b51e1 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -99,16 +98,16 @@ typedef struct __PCD_HandleTypeDef typedef struct #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { - PCD_TypeDef *Instance; /*!< Register base address */ - PCD_InitTypeDef Init; /*!< PCD required parameters */ - __IO uint8_t USB_Address; /*!< USB Address */ + PCD_TypeDef *Instance; /*!< Register base address */ + PCD_InitTypeDef Init; /*!< PCD required parameters */ + __IO uint8_t USB_Address; /*!< USB Address */ PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ - HAL_LockTypeDef Lock; /*!< PCD peripheral status */ - __IO PCD_StateTypeDef State; /*!< PCD communication state */ - __IO uint32_t ErrorCode; /*!< PCD Error code */ - uint32_t Setup[12]; /*!< Setup packet buffer */ - PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ + HAL_LockTypeDef Lock; /*!< PCD peripheral status */ + __IO PCD_StateTypeDef State; /*!< PCD communication state */ + __IO uint32_t ErrorCode; /*!< PCD Error code */ + uint32_t Setup[12]; /*!< Setup packet buffer */ + PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ uint32_t BESL; @@ -155,7 +154,7 @@ typedef struct /** @defgroup PCD_Speed PCD Speed * @{ */ -#define PCD_SPEED_FULL 2U +#define PCD_SPEED_FULL USBD_FS_SPEED /** * @} */ @@ -188,27 +187,21 @@ typedef struct /* Exported macros -----------------------------------------------------------*/ /** @defgroup PCD_Exported_Macros PCD Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ -#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__)) +#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\ + & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE -#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE) -#define __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR1 & (USB_WAKEUP_EXTI_LINE) -#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR1 = USB_WAKEUP_EXTI_LINE - -#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ - do { \ - EXTI->FTSR1 &= ~(USB_WAKEUP_EXTI_LINE); \ - EXTI->RTSR1 |= USB_WAKEUP_EXTI_LINE; \ - } while(0U) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\ + &= (uint16_t)(~(__INTERRUPT__))) +#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE +#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE) /** @@ -242,7 +235,7 @@ typedef enum HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */ HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */ HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */ - HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */ + HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */ HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */ HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */ @@ -269,25 +262,41 @@ typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgType * @} */ -HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, + HAL_PCD_CallbackIDTypeDef CallbackID, + pPCD_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, + HAL_PCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataOutStageCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataInStageCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoOutIncpltCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoInIncpltCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, + pPCD_BcdCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, + pPCD_LpmCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ /** @@ -326,16 +335,22 @@ void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint16_t ep_mps, uint8_t ep_type); + HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint8_t *pBuf, uint32_t len); + +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint8_t *pBuf, uint32_t len); + HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); /** * @} */ @@ -362,7 +377,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); */ -#define USB_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */ +#define USB_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */ /** @@ -372,10 +387,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** @defgroup PCD_EP0_MPS PCD EP0 MPS * @{ */ -#define PCD_EP0MPS_64 DEP0CTL_MPS_64 -#define PCD_EP0MPS_32 DEP0CTL_MPS_32 -#define PCD_EP0MPS_16 DEP0CTL_MPS_16 -#define PCD_EP0MPS_08 DEP0CTL_MPS_8 +#define PCD_EP0MPS_64 EP_MPS_64 +#define PCD_EP0MPS_32 EP_MPS_32 +#define PCD_EP0MPS_16 EP_MPS_16 +#define PCD_EP0MPS_08 EP_MPS_8 /** * @} */ @@ -410,21 +425,22 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /* Private macros ------------------------------------------------------------*/ /** @defgroup PCD_Private_Macros PCD Private Macros - * @{ - */ + * @{ + */ /******************** Bit definition for USB_COUNTn_RX register *************/ #define USB_CNTRX_NBLK_MSK (0x1FU << 10) #define USB_CNTRX_BLSIZE (0x1U << 15) /* SetENDPOINT */ -#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue)) +#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)\ + (&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue)) /* GetENDPOINT */ -#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U))) +#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U))) /* ENDPOINT transfer */ -#define USB_EP0StartXfer USB_EPStartXfer +#define USB_EP0StartXfer USB_EPStartXfer /** * @brief sets the type in the endpoint register(bits EP_TYPE[1:0]) @@ -433,8 +449,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wType Endpoint Type. * @retval None */ -#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX))) +#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum))\ + & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX))) + /** * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) @@ -451,18 +468,19 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum, bDir * @retval None */ -#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) do { \ - if ((bDir) == 0U) \ - { \ - /* OUT double buffered endpoint */ \ - PCD_TX_DTOG((USBx), (bEpNum)); \ - } \ - else if ((bDir) == 1U) \ - { \ - /* IN double buffered endpoint */ \ - PCD_RX_DTOG((USBx), (bEpNum)); \ - } \ -} while(0) +#define PCD_FREE_USER_BUFFER(USBx, bEpNum, bDir) \ + do { \ + if ((bDir) == 0U) \ + { \ + /* OUT double buffered endpoint */ \ + PCD_TX_DTOG((USBx), (bEpNum)); \ + } \ + else if ((bDir) == 1U) \ + { \ + /* IN double buffered endpoint */ \ + PCD_RX_DTOG((USBx), (bEpNum)); \ + } \ + } while(0) /** * @brief sets the status for tx transfer (bits STAT_TX[1:0]). @@ -471,21 +489,22 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wState new state * @retval None */ -#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) do { \ - register uint16_t _wRegVal; \ - \ +#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \ + do { \ + uint16_t _wRegVal; \ + \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \ - /* toggle first bit ? */ \ - if ((USB_EPTX_DTOG1 & (wState))!= 0U) \ - { \ + /* toggle first bit ? */ \ + if ((USB_EPTX_DTOG1 & (wState))!= 0U) \ + { \ _wRegVal ^= USB_EPTX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if ((USB_EPTX_DTOG2 & (wState))!= 0U) \ - { \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPTX_DTOG2 & (wState))!= 0U) \ + { \ _wRegVal ^= USB_EPTX_DTOG2; \ - } \ - PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ } while(0) /* PCD_SET_EP_TX_STATUS */ /** @@ -495,19 +514,20 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wState new state * @retval None */ -#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) do { \ - register uint16_t _wRegVal; \ +#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \ + do { \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \ /* toggle first bit ? */ \ if ((USB_EPRX_DTOG1 & (wState))!= 0U) \ { \ - _wRegVal ^= USB_EPRX_DTOG1; \ + _wRegVal ^= USB_EPRX_DTOG1; \ } \ /* toggle second bit ? */ \ if ((USB_EPRX_DTOG2 & (wState))!= 0U) \ { \ - _wRegVal ^= USB_EPRX_DTOG2; \ + _wRegVal ^= USB_EPRX_DTOG2; \ } \ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ } while(0) /* PCD_SET_EP_RX_STATUS */ @@ -520,8 +540,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wStatetx new state. * @retval None */ -#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) do { \ - register uint16_t _wRegVal; \ +#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \ + do { \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \ /* toggle first bit ? */ \ @@ -573,10 +594,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum Endpoint Number. * @retval TRUE = endpoint in stall condition. */ -#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \ - == USB_EP_TX_STALL) -#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \ - == USB_EP_RX_STALL) +#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL) +#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL) /** * @brief set & clear EP_KIND bit. @@ -584,16 +603,18 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum Endpoint Number. * @retval None */ -#define PCD_SET_EP_KIND(USBx, bEpNum) do { \ - register uint16_t _wRegVal; \ +#define PCD_SET_EP_KIND(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ \ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \ } while(0) /* PCD_SET_EP_KIND */ -#define PCD_CLEAR_EP_KIND(USBx, bEpNum) do { \ - register uint16_t _wRegVal; \ +#define PCD_CLEAR_EP_KIND(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \ \ @@ -615,8 +636,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum Endpoint Number. * @retval None */ -#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) -#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) +#define PCD_SET_BULK_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) +#define PCD_CLEAR_BULK_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) /** * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. @@ -624,16 +645,18 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum Endpoint Number. * @retval None */ -#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) do { \ - register uint16_t _wRegVal; \ +#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \ \ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \ } while(0) /* PCD_CLEAR_RX_EP_CTR */ -#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) do { \ - register uint16_t _wRegVal; \ +#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \ \ @@ -646,16 +669,18 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum Endpoint Number. * @retval None */ -#define PCD_RX_DTOG(USBx, bEpNum) do { \ - register uint16_t _wEPVal; \ +#define PCD_RX_DTOG(USBx, bEpNum) \ + do { \ + uint16_t _wEPVal; \ \ _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ \ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \ } while(0) /* PCD_RX_DTOG */ -#define PCD_TX_DTOG(USBx, bEpNum) do { \ - register uint16_t _wEPVal; \ +#define PCD_TX_DTOG(USBx, bEpNum) \ + do { \ + uint16_t _wEPVal; \ \ _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ \ @@ -667,8 +692,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum Endpoint Number. * @retval None */ -#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) do { \ - register uint16_t _wRegVal; \ +#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ \ @@ -678,8 +704,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); } \ } while(0) /* PCD_CLEAR_RX_DTOG */ -#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) do { \ - register uint16_t _wRegVal; \ +#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ \ @@ -696,8 +723,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bAddr Address. * @retval None */ -#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) do { \ - register uint16_t _wRegVal; \ +#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \ + do { \ + uint16_t _wRegVal; \ \ _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \ \ @@ -712,8 +740,12 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); */ #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) -#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) -#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) +#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\ + + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) + +#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\ + + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) + /** * @brief sets address of the tx/rx buffer. @@ -722,23 +754,25 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wAddr address to be set (must be word aligned). * @retval None */ -#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) do { \ - register uint16_t *_wRegVal; \ - register uint32_t _wRegBase = (uint32_t)USBx; \ - \ - _wRegBase += (uint32_t)(USBx)->BTABLE; \ - _wRegVal = (uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \ - *_wRegVal = ((wAddr) >> 1) << 1; \ -} while(0) /* PCD_SET_EP_TX_ADDRESS */ +#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \ + do { \ + __IO uint16_t *_wRegVal; \ + uint32_t _wRegBase = (uint32_t)USBx; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \ + *_wRegVal = ((wAddr) >> 1) << 1; \ + } while(0) /* PCD_SET_EP_TX_ADDRESS */ -#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) do { \ - register uint16_t *_wRegVal; \ - register uint32_t _wRegBase = (uint32_t)USBx; \ - \ - _wRegBase += (uint32_t)(USBx)->BTABLE; \ - _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \ - *_wRegVal = ((wAddr) >> 1) << 1; \ -} while(0) /* PCD_SET_EP_RX_ADDRESS */ +#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \ + do { \ + __IO uint16_t *_wRegVal; \ + uint32_t _wRegBase = (uint32_t)USBx; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \ + *_wRegVal = ((wAddr) >> 1) << 1; \ + } while(0) /* PCD_SET_EP_RX_ADDRESS */ /** * @brief Gets address of the tx/rx buffer. @@ -756,12 +790,18 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wNBlocks no. of Blocks. * @retval None */ -#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) do { \ +#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \ + do { \ (wNBlocks) = (wCount) >> 5; \ + if (((wCount) & 0x1fU) == 0U) \ + { \ + (wNBlocks)--; \ + } \ *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \ } while(0) /* PCD_CALC_BLK32 */ -#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) do { \ +#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \ + do { \ (wNBlocks) = (wCount) >> 1; \ if (((wCount) & 0x1U) != 0U) \ { \ @@ -770,29 +810,35 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); *(pdwReg) = (uint16_t)((wNBlocks) << 10); \ } while(0) /* PCD_CALC_BLK2 */ -#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) do { \ +#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \ + do { \ uint32_t wNBlocks; \ - if ((wCount) == 0U) \ + \ + if ((wCount) > 62U) \ { \ - *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \ - *(pdwReg) |= USB_CNTRX_BLSIZE; \ - } \ - else if((wCount) < 62U) \ - { \ - PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ + PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ } \ else \ { \ - PCD_CALC_BLK32((pdwReg),(wCount), wNBlocks); \ + if ((wCount) == 0U) \ + { \ + *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \ + *(pdwReg) |= USB_CNTRX_BLSIZE; \ + } \ + else \ + { \ + PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ + } \ } \ } while(0) /* PCD_SET_EP_CNT_RX_REG */ -#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) do { \ - register uint32_t _wRegBase = (uint32_t)(USBx); \ - uint16_t *pdwReg; \ - \ +#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \ + do { \ + uint32_t _wRegBase = (uint32_t)(USBx); \ + __IO uint16_t *pdwReg; \ + \ _wRegBase += (uint32_t)(USBx)->BTABLE; \ - pdwReg = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ + pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \ } while(0) @@ -803,23 +849,25 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wCount Counter value. * @retval None */ -#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) do { \ - register uint32_t _wRegBase = (uint32_t)(USBx); \ - uint16_t *_wRegVal; \ +#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \ + do { \ + uint32_t _wRegBase = (uint32_t)(USBx); \ + __IO uint16_t *_wRegVal; \ \ _wRegBase += (uint32_t)(USBx)->BTABLE; \ - _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ *_wRegVal = (uint16_t)(wCount); \ -} while(0) + } while(0) -#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) do { \ - register uint32_t _wRegBase = (uint32_t)(USBx); \ - uint16_t *_wRegVal; \ +#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \ + do { \ + uint32_t _wRegBase = (uint32_t)(USBx); \ + __IO uint16_t *_wRegVal; \ \ _wRegBase += (uint32_t)(USBx)->BTABLE; \ - _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \ -} while(0) + } while(0) /** * @brief gets counter of the tx buffer. @@ -837,10 +885,13 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wBuf0Addr buffer 0 address. * @retval Counter value */ -#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) do { \ +#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \ + do { \ PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \ } while(0) /* PCD_SET_EP_DBUF0_ADDR */ -#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) do { \ + +#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \ + do { \ PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \ } while(0) /* PCD_SET_EP_DBUF1_ADDR */ @@ -852,7 +903,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wBuf1Addr = buffer 1 address. * @retval None */ -#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) do { \ +#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \ + do { \ PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \ PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \ } while(0) /* PCD_SET_EP_DBUF_ADDR */ @@ -875,7 +927,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wCount: Counter value * @retval None */ -#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) do { \ +#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \ + do { \ if ((bDir) == 0U) \ /* OUT endpoint */ \ { \ @@ -891,9 +944,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); } \ } while(0) /* SetEPDblBuf0Count*/ -#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) do { \ - register uint32_t _wBase = (uint32_t)(USBx); \ - uint16_t *_wEPRegVal; \ +#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \ + do { \ + uint32_t _wBase = (uint32_t)(USBx); \ + __IO uint16_t *_wEPRegVal; \ \ if ((bDir) == 0U) \ { \ @@ -906,16 +960,17 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); { \ /* IN endpoint */ \ _wBase += (uint32_t)(USBx)->BTABLE; \ - _wEPRegVal = (uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ + _wEPRegVal = (__IO uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ *_wEPRegVal = (uint16_t)(wCount); \ } \ } \ } while(0) /* SetEPDblBuf1Count */ -#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) do { \ +#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \ + do { \ PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \ PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \ - } while(0) /* PCD_SET_EP_DBUF_CNT */ + } while(0) /* PCD_SET_EP_DBUF_CNT */ /** * @brief Gets buffer 0/1 rx/tx counter for double buffering. @@ -946,5 +1001,3 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #endif #endif /* STM32G4xx_HAL_PCD_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h index d4247f3..300eab2 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -23,7 +22,7 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /* __cplusplus */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" @@ -49,10 +48,8 @@ extern "C" { -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, - uint16_t ep_addr, - uint16_t ep_kind, - uint32_t pmaadress); +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, + uint16_t ep_kind, uint32_t pmaadress); HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); @@ -85,9 +82,7 @@ void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); #ifdef __cplusplus } -#endif +#endif /* __cplusplus */ #endif /* STM32G4xx_HAL_PCD_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h index 29f9c15..fe23556 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -410,4 +409,3 @@ void HAL_PWR_PVDCallback(void); #endif /* STM32G4xx_HAL_PWR_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h index 600eb0a..923f83c 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -767,15 +766,6 @@ void HAL_PWREx_EnablePVM4(void); void HAL_PWREx_DisablePVM4(void); HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); -#if defined(PWR_CR3_UCPD_DBDIS) -void HAL_PWREx_EnableUSBDeadBatteryPD(void); -void HAL_PWREx_DisableUSBDeadBatteryPD(void); -#endif /* PWR_CR3_UCPD_DBDIS */ -#if defined(PWR_CR3_UCPD_STDBY) -void HAL_PWREx_EnableUSBStandByModePD(void); -void HAL_PWREx_DisableUSBStandByModePD (void); -#endif /* PWR_CR3_UCPD_STDBY */ - /* Low Power modes configuration functions ************************************/ void HAL_PWREx_EnableLowPowerRunMode(void); HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); @@ -793,6 +783,15 @@ void HAL_PWREx_PVM2Callback(void); void HAL_PWREx_PVM3Callback(void); void HAL_PWREx_PVM4Callback(void); +#if defined(PWR_CR3_UCPD_STDBY) +void HAL_PWREx_EnableUCPDStandbyMode(void); +void HAL_PWREx_DisableUCPDStandbyMode(void); +#endif /* PWR_CR3_UCPD_STDBY */ +#if defined(PWR_CR3_UCPD_DBDIS) +void HAL_PWREx_EnableUCPDDeadBattery(void); +void HAL_PWREx_DisableUCPDDeadBattery(void); +#endif /* PWR_CR3_UCPD_DBDIS */ + /** * @} */ @@ -816,4 +815,3 @@ void HAL_PWREx_PVM4Callback(void); #endif /* STM32G4xx_HAL_PWR_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h index d26fcba..c0969dc 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -386,7 +384,24 @@ typedef struct /** @defgroup RCC_MCO_Index MCO Index * @{ */ -#define RCC_MCO1 0x00000000U +/* 32 28 20 16 0 + -------------------------------- + | MCO | GPIO | GPIO | GPIO | + | Index | AF | Port | Pin | + -------------------------------*/ + +#define RCC_MCO_GPIOPORT_POS 16U +#define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS) +#define RCC_MCO_GPIOAF_POS 20U +#define RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS) +#define RCC_MCO_INDEX_POS 28U +#define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS) +#define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */ +#define RCC_MCO_PA8 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) +#define RCC_MCO_PG10 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOG) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10) + +/* Legacy Defines*/ +#define RCC_MCO1 RCC_MCO_PA8 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ /** * @} @@ -3300,7 +3315,8 @@ typedef struct ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) -#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1) +#define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO_PA8) || \ + ((__MCOX__) == RCC_MCO_PG10)) #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ @@ -3388,4 +3404,3 @@ void HAL_RCC_CSSCallback(void); #endif /* STM32G4xx_HAL_RCC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h index 29481cf..3dcc2f8 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -1220,14 +1218,14 @@ typedef struct #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) /** - * @brief Enable the automatic hardware adjustement of TRIM bits. + * @brief Enable the automatic hardware adjustment of TRIM bits. * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. * @retval None */ #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) /** - * @brief Enable or disable the automatic hardware adjustement of TRIM bits. + * @brief Enable or disable the automatic hardware adjustment of TRIM bits. * @retval None */ #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) @@ -1338,8 +1336,29 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \ (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) -#elif defined(STM32G473xx) +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \ + (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined(STM32G473xx) || defined(STM32G483xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ @@ -1355,6 +1374,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ @@ -1584,4 +1604,3 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #endif /* STM32G4xx_HAL_RCC_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi.h index a01f6da..28743ea 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -582,7 +581,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) /** @brief Check whether the specified SPI flag is set or not. - * @param __SR__ copy of SPI SR regsiter. + * @param __SR__ copy of SPI SR register. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SPI_FLAG_RXNE: Receive buffer not empty flag @@ -596,10 +595,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @arg SPI_FLAG_FRLVL: SPI fifo reception level * @retval SET or RESET. */ -#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) +#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ + ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. - * @param __CR2__ copy of SPI CR2 regsiter. + * @param __CR2__ copy of SPI CR2 register. * @param __INTERRUPT__ specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable @@ -607,15 +607,16 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @arg SPI_IT_ERR: Error interrupt enable * @retval SET or RESET. */ -#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ + (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if SPI Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Mode. * This parameter can be a value of @ref SPI_Mode * @retval None */ -#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ - ((__MODE__) == SPI_MODE_MASTER)) +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ + ((__MODE__) == SPI_MODE_MASTER)) /** @brief Checks if SPI Direction Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Direction Mode. @@ -663,33 +664,33 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be a value of @ref SPI_Clock_Polarity * @retval None */ -#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ - ((__CPOL__) == SPI_POLARITY_HIGH)) +#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ + ((__CPOL__) == SPI_POLARITY_HIGH)) /** @brief Checks if SPI Clock Phase parameter is in allowed range. * @param __CPHA__ specifies the SPI Clock Phase. * This parameter can be a value of @ref SPI_Clock_Phase * @retval None */ -#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ - ((__CPHA__) == SPI_PHASE_2EDGE)) +#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ + ((__CPHA__) == SPI_PHASE_2EDGE)) /** @brief Checks if SPI Slave Select parameter is in allowed range. * @param __NSS__ specifies the SPI Slave Select management parameter. * This parameter can be a value of @ref SPI_Slave_Select_management * @retval None */ -#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ - ((__NSS__) == SPI_NSS_HARD_INPUT) || \ - ((__NSS__) == SPI_NSS_HARD_OUTPUT)) +#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ + ((__NSS__) == SPI_NSS_HARD_INPUT) || \ + ((__NSS__) == SPI_NSS_HARD_OUTPUT)) /** @brief Checks if SPI NSS Pulse parameter is in allowed range. * @param __NSSP__ specifies the SPI NSS Pulse Mode parameter. * This parameter can be a value of @ref SPI_NSSP_Mode * @retval None */ -#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \ - ((__NSSP__) == SPI_NSS_PULSE_DISABLE)) +#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \ + ((__NSSP__) == SPI_NSS_PULSE_DISABLE)) /** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. * @param __PRESCALER__ specifies the SPI Baudrate prescaler. @@ -710,16 +711,16 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be a value of @ref SPI_MSB_LSB_transmission * @retval None */ -#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ - ((__BIT__) == SPI_FIRSTBIT_LSB)) +#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ + ((__BIT__) == SPI_FIRSTBIT_LSB)) /** @brief Checks if SPI TI mode parameter is in allowed range. * @param __MODE__ specifies the SPI TI mode. * This parameter can be a value of @ref SPI_TI_mode * @retval None */ -#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ - ((__MODE__) == SPI_TIMODE_ENABLE)) +#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ + ((__MODE__) == SPI_TIMODE_ENABLE)) /** @brief Checks if SPI CRC calculation enabled state is in allowed range. * @param __CALCULATION__ specifies the SPI CRC calculation enable state. @@ -734,8 +735,8 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be a value of @ref SPI_CRC_length * @retval None */ -#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) ||\ - ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \ +#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \ + ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \ ((__LENGTH__) == SPI_CRC_LENGTH_16BIT)) /** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. @@ -743,7 +744,9 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 * @retval None */ -#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U)) +#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ + ((__POLYNOMIAL__) <= 0xFFFFU) && \ + (((__POLYNOMIAL__)&0x1U) != 0U)) /** @brief Checks if DMA handle is valid. * @param __HANDLE__ specifies a DMA Handle. @@ -774,7 +777,8 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ /** @@ -845,4 +849,3 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); #endif /* STM32G4xx_HAL_SPI_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi_ex.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi_ex.h index 56276c9..4db1186 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi_ex.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -72,4 +71,3 @@ HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi); #endif /* STM32G4xx_HAL_SPI_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h index d75b57b..acc47aa 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -55,9 +54,10 @@ typedef struct uint32_t Period; /*!< Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFEF if dithering is activated) - Macros __HAL_TIM_CALC_PERIOD(), __HAL_TIM_CALC_PERIOD_DITHER(), __HAL_TIM_CALC_PERIOD_BY_DELAY(), __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY() - can be used to calculate Period value */ + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF + (or 0xFFEF if dithering is activated)Macros __HAL_TIM_CALC_PERIOD(), + __HAL_TIM_CALC_PERIOD_DITHER(),__HAL_TIM_CALC_PERIOD_BY_DELAY(), + __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY()can be used to calculate Period value */ uint32_t ClockDivision; /*!< Specifies the clock division. This parameter can be a value of @ref TIM_ClockDivision */ @@ -68,8 +68,10 @@ typedef struct This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode - GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. - Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. */ uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. This parameter can be a value of @ref TIM_AutoReloadPreload */ @@ -84,9 +86,10 @@ typedef struct This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFEF if dithering is activated) - Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() - can be used to calculate Pulse value */ + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF + (or 0xFFEF if dithering is activated) + Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate + Pulse value */ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_Output_Compare_Polarity */ @@ -118,9 +121,10 @@ typedef struct This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFEF if dithering is activated) - Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() - can be used to calculate Pulse value */ + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF + (or 0xFFEF if dithering is activated) + Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate + Pulse value */ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_Output_Compare_Polarity */ @@ -174,7 +178,7 @@ typedef struct This parameter can be a value of @ref TIM_Encoder_Mode */ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ uint32_t IC1Selection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ @@ -186,7 +190,7 @@ typedef struct This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ uint32_t IC2Selection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ @@ -225,7 +229,8 @@ typedef struct uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity This parameter can be a value of @ref TIM_ClearInput_Polarity */ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler - This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + This parameter must be 0: When OCRef clear feature is used with ETR source, + ETR prescaler must be off */ uint32_t ClearInputFilter; /*!< TIM Clear Input filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_ClearInputConfigTypeDef; @@ -242,7 +247,12 @@ typedef struct uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ uint32_t MasterSlaveMode; /*!< Master/slave mode selection - This parameter can be a value of @ref TIM_Master_Slave_Mode */ + This parameter can be a value of @ref TIM_Master_Slave_Mode + @note When the Master/slave mode is enabled, the effect of + an event on the trigger input (TRGI) is delayed to allow a + perfect synchronization between the current timer and its + slaves (through TRGO). It is not mandatory in case of timer + synchronization mode. */ } TIM_MasterConfigTypeDef; /** @@ -270,32 +280,32 @@ typedef struct */ typedef struct { - uint32_t OffStateRunMode; /*!< TIM off state in run mode - This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode - This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - uint32_t LockLevel; /*!< TIM Lock level - This parameter can be a value of @ref TIM_Lock_level */ - uint32_t DeadTime; /*!< TIM dead Time - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - uint32_t BreakState; /*!< TIM Break State - This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - uint32_t BreakPolarity; /*!< TIM Break input polarity - This parameter can be a value of @ref TIM_Break_Polarity */ - uint32_t BreakFilter; /*!< Specifies the break input filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input. - This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ - uint32_t Break2State; /*!< TIM Break2 State - This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ - uint32_t Break2Polarity; /*!< TIM Break2 input polarity - This parameter can be a value of @ref TIM_Break2_Polarity */ - uint32_t Break2Filter; /*!< TIM break2 input filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input. - This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ - uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ + + uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + + uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ + + uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ + + uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ + + uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ + + uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ + + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + } TIM_BreakDeadTimeConfigTypeDef; /** @@ -310,6 +320,26 @@ typedef enum HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ } HAL_TIM_StateTypeDef; +/** + * @brief TIM Channel States definition + */ +typedef enum +{ + HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ + HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ + HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ +} HAL_TIM_ChannelStateTypeDef; + +/** + * @brief DMA Burst States definition + */ +typedef enum +{ + HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ + HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ + HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ +} HAL_TIM_DMABurstStateTypeDef; + /** * @brief HAL Active channel structures definition */ @@ -333,13 +363,16 @@ typedef struct __TIM_HandleTypeDef typedef struct #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ { - TIM_TypeDef *Instance; /*!< Register base address */ - TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ - DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array - This array is accessed by a @ref DMA_Handle_index */ - HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ + __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ @@ -383,39 +416,39 @@ typedef struct */ typedef enum { - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ - ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ - ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ - ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ - ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ - ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ - ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ - ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ - ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ - ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ - ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ - ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ - ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ - ,HAL_TIM_ENCODER_INDEX_CB_ID = 0x1CU /*!< TIM Encoder Index Callback ID */ - ,HAL_TIM_DIRECTION_CHANGE_CB_ID = 0x1DU /*!< TIM Direction Change Callback ID */ - ,HAL_TIM_INDEX_ERROR_CB_ID = 0x1EU /*!< TIM Index Error Callback ID */ - ,HAL_TIM_TRANSITION_ERROR_CB_ID = 0x1FU /*!< TIM Transition Error Callback ID */ + , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ + , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ + , HAL_TIM_ENCODER_INDEX_CB_ID = 0x1CU /*!< TIM Encoder Index Callback ID */ + , HAL_TIM_DIRECTION_CHANGE_CB_ID = 0x1DU /*!< TIM Direction Change Callback ID */ + , HAL_TIM_INDEX_ERROR_CB_ID = 0x1EU /*!< TIM Index Error Callback ID */ + , HAL_TIM_TRANSITION_ERROR_CB_ID = 0x1FU /*!< TIM Transition Error Callback ID */ } HAL_TIM_CallbackIDTypeDef; /** @@ -549,6 +582,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap + * @{ + */ +#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ +#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ +/** + * @} + */ + /** @defgroup TIM_ClockDivision TIM Clock Division * @{ */ @@ -642,13 +684,20 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity + * @{ + */ +#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ +#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ +/** + * @} + */ + /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection * @{ */ -#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ /** * @} @@ -931,19 +980,18 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @{ */ #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ -#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event - (if none of the break inputs BRK and BRK2 is active) */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ /** * @} */ -/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 +/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 * @{ */ -#define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ -#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ -#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ -#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ +#define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ +#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ +#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ +#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ /** * @} */ @@ -1096,32 +1144,32 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length * @{ */ -#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_19TRANSFERS 0x00001200U /*!< The transfer is done to 19 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_20TRANSFERS 0x00001300U /*!< The transfer is done to 20 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_21TRANSFERS 0x00001400U /*!< The transfer is done to 21 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_22TRANSFERS 0x00001500U /*!< The transfer is done to 22 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_23TRANSFERS 0x00001600U /*!< The transfer is done to 23 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_24TRANSFERS 0x00001700U /*!< The transfer is done to 24 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_25TRANSFERS 0x00001800U /*!< The transfer is done to 25 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_26TRANSFERS 0x00001900U /*!< The transfer is done to 26 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_19TRANSFERS 0x00001200U /*!< The transfer is done to 19 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_20TRANSFERS 0x00001300U /*!< The transfer is done to 20 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_21TRANSFERS 0x00001400U /*!< The transfer is done to 21 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_22TRANSFERS 0x00001500U /*!< The transfer is done to 22 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_23TRANSFERS 0x00001600U /*!< The transfer is done to 23 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_24TRANSFERS 0x00001700U /*!< The transfer is done to 24 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_25TRANSFERS 0x00001800U /*!< The transfer is done to 25 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_26TRANSFERS 0x00001900U /*!< The transfer is done to 26 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ /** * @} */ @@ -1177,25 +1225,49 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @retval None */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ - (__HANDLE__)->Base_MspInitCallback = NULL; \ - (__HANDLE__)->Base_MspDeInitCallback = NULL; \ - (__HANDLE__)->IC_MspInitCallback = NULL; \ - (__HANDLE__)->IC_MspDeInitCallback = NULL; \ - (__HANDLE__)->OC_MspInitCallback = NULL; \ - (__HANDLE__)->OC_MspDeInitCallback = NULL; \ - (__HANDLE__)->PWM_MspInitCallback = NULL; \ - (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ - (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ - (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ } while(0) #else -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** @@ -1232,7 +1304,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @brief Disable the TIM main Output. * @param __HANDLE__ TIM handle * @retval None - * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been + * disabled */ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ do { \ @@ -1421,12 +1494,38 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to */ #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) + +/** + * @brief Get update interrupt flag (UIF) copy status. + * @param __COUNTER__ Counter value. + * @retval The state of UIFCPY (TRUE or FALSE). +mode. + */ +#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) + /** * @brief Indicates whether or not the TIM Counter is used as downcounter. * @param __HANDLE__ TIM handle. * @retval False (Counter used as upcounter) or True (Counter used as downcounter) - * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder -mode. + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode + * or Encoder mode. */ #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) @@ -1440,6 +1539,9 @@ mode. /** * @brief Set the TIM Counter Register value on runtime. + * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in + * case of 32 bits counter TIM instance. + * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. * @param __HANDLE__ TIM handle. * @param __COUNTER__ specifies the Counter register new value. * @retval None @@ -1500,7 +1602,8 @@ mode. #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) /** - * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() + * function. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: @@ -1621,12 +1724,62 @@ mode. * @retval None */ #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\ - ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE)) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) + +/** + * @brief Enable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is enabled an active edge on the trigger input acts + * like a compare match on CCx output. Delay to sample the trigger + * input and to activate CCx output is reduced to 3 clock cycles. + * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) + +/** + * @brief Disable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is disabled CCx output behaves normally depending + * on counter and CCRx values even when the trigger is ON. The minimum + * delay to activate CCx output when an active edge occurs on the + * trigger input is 5 clock cycles. + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. @@ -1749,6 +1902,9 @@ mode. ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) +#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ + ((__MODE__) == TIM_UIFREMAP_ENALE)) + #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) @@ -1771,6 +1927,9 @@ mode. #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ ((__STATE__) == TIM_OCNIDLESTATE_RESET)) +#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) + #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) @@ -1850,7 +2009,23 @@ mode. ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) +#elif defined(TIM20) +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) #else #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -1867,7 +2042,6 @@ mode. ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) #endif /* TIM5 && TIM20 */ @@ -1991,22 +2165,6 @@ mode. ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) #if defined (TIM5) && defined(TIM20) -#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ - ((__SELECTION__) == TIM_TS_ITR4) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR9) || \ - ((__SELECTION__) == TIM_TS_ITR10) || \ - ((__SELECTION__) == TIM_TS_ITR11) || \ - ((__SELECTION__) == TIM_TS_ETRF)) #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ @@ -2022,22 +2180,6 @@ mode. ((__SELECTION__) == TIM_TS_ITR11)|| \ ((__SELECTION__) == TIM_TS_NONE)) #elif defined (TIM5) -#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ - ((__SELECTION__) == TIM_TS_ITR4) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10) || \ - ((__SELECTION__) == TIM_TS_ITR11) || \ - ((__SELECTION__) == TIM_TS_ETRF)) - #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ @@ -2050,22 +2192,19 @@ mode. ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_ITR11)|| \ ((__SELECTION__) == TIM_TS_NONE)) -#else -#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10) || \ - ((__SELECTION__) == TIM_TS_ITR11) || \ - ((__SELECTION__) == TIM_TS_ETRF)) - +#elif defined (TIM20) +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_ITR11)|| \ + ((__SELECTION__) == TIM_TS_NONE)) +#else #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ @@ -2074,7 +2213,6 @@ mode. ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_ITR11)|| \ ((__SELECTION__) == TIM_TS_NONE)) #endif /* TIM5 && TIM20 */ @@ -2095,15 +2233,15 @@ mode. #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) -#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ @@ -2143,10 +2281,10 @@ mode. ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ - ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ @@ -2155,10 +2293,64 @@ mode. ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ - ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ + (__HANDLE__)->ChannelState[5]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = \ + (__CHANNEL_STATE__); \ + } while(0) + +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ + (__HANDLE__)->ChannelNState[3]) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelNState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = \ + (__CHANNEL_STATE__); \ + } while(0) /** * @} @@ -2332,14 +2524,14 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_Sla HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, - uint32_t DataLength); + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, - uint32_t DataLength); + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); @@ -2385,6 +2577,11 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); + +/* Peripheral Channel state functions ************************************************/ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); /** * @} */ @@ -2404,7 +2601,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); void TIM_DMAError(DMA_HandleTypeDef *hdma); void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); @@ -2433,5 +2629,3 @@ void TIM_ResetCallback(TIM_HandleTypeDef *htim); #endif #endif /* STM32G4xx_HAL_TIM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h index d00de67..b40d85c 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -71,27 +70,26 @@ typedef struct This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ uint32_t Polarity; /*!< Specifies the break input source polarity. This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */ -} -TIMEx_BreakInputConfigTypeDef; +} TIMEx_BreakInputConfigTypeDef; /** * @brief TIM Encoder index configuration */ typedef struct { - uint32_t Polarity; /*!< TIM Encoder index polarity. - This parameter can be a value of @ref TIM_Encoder_Index_Polarity */ - uint32_t Prescaler; /*!< TIM Encoder index prescaler. - This parameter can be a value of @ref TIM_Encoder_Index_Prescaler */ - uint32_t Filter; /*!< TIM Encoder index filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - FunctionalState FirstIndexEnable; /*!< Specifies whether or not the encoder first index is enabled. - This parameter value can be ENABLE or DISABLE. */ - uint32_t Position; /*!< Specifies in which AB input configuration the index event resets the counter. - This parameter can be a value of @ref TIMEx_Encoder_Index_Position */ - uint32_t Direction; /*!< Specifies in which counter direction the index event resets the counter. - This parameter can be a value of @ref TIMEx_Encoder_Index_Direction */ -} TIMEx_EncoderIndexConfigTypeDef ; + uint32_t Polarity; /*!< TIM Encoder index polarity.This parameter can be a value of @ref TIMEx_Encoder_Index_Polarity */ + + uint32_t Prescaler; /*!< TIM Encoder index prescaler.This parameter can be a value of @ref TIMEx_Encoder_Index_Prescaler */ + + uint32_t Filter; /*!< TIM Encoder index filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + FunctionalState FirstIndexEnable; /*!< Specifies whether or not the encoder first index is enabled.This parameter value can be ENABLE or DISABLE. */ + + uint32_t Position; /*!< Specifies in which AB input configuration the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Position */ + + uint32_t Direction; /*!< Specifies in which counter direction the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Direction */ + +} TIMEx_EncoderIndexConfigTypeDef; /** * @} @@ -237,15 +235,23 @@ typedef struct #define TIM_TIM20_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */ #define TIM_TIM20_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */ #define TIM_TIM20_ETR_COMP4 TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */ +#if defined(COMP5) #define TIM_TIM20_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */ +#endif /* COMP5 */ +#if defined(COMP6) #define TIM_TIM20_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */ +#endif /* COMP6 */ +#if defined(COMP7) #define TIM_TIM20_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */ +#endif /* COMP7 */ #define TIM_TIM20_ETR_ADC3_AWD1 TIM1_AF1_ETRSEL_3 /* !< ADC3 analog watchdog 1 */ #define TIM_TIM20_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ADC3 analog watchdog 2 */ #define TIM_TIM20_ETR_ADC3_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /* !< ADC3 analog watchdog 3 */ +#if defined (ADC5) #define TIM_TIM20_ETR_ADC5_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ADC5 analog watchdog 1 */ #define TIM_TIM20_ETR_ADC5_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /* !< ADC5 analog watchdog 2 */ #define TIM_TIM20_ETR_ADC5_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ADC5 analog watchdog 3 */ +#endif /* ADC5 */ #endif /* TIM20 */ /** * @} @@ -254,8 +260,8 @@ typedef struct /** @defgroup TIMEx_Break_Input TIM Extended Break input * @{ */ -#define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */ -#define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */ +#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */ +#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */ /** * @} */ @@ -284,8 +290,8 @@ typedef struct /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling * @{ */ -#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */ -#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */ +#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */ +#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */ /** * @} */ @@ -293,8 +299,8 @@ typedef struct /** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity * @{ */ -#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */ -#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */ +#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */ +#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */ /** * @} */ @@ -592,19 +598,22 @@ typedef struct (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U /** - * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required output signal frequency. + * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required + * output signal frequency. * @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER(1000000, 0, 10000); - * @note This macro should be used only if ditehring is already enabled + * @note This macro should be used only if dithering is already enabled * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler * @param __FREQ__ output signal frequency (in Hz) * @retval Auto-reload value (between Min_Data=0 and Max_Data=65519) */ #define __HAL_TIM_CALC_PERIOD_DITHER(__TIMCLK__, __PSC__, __FREQ__) \ - (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (uint32_t)(((uint64_t)(__TIMCLK__)*16/((__FREQ__) * ((__PSC__) + 1U)) - 16U)) : 0U + (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \ + (uint32_t)(((uint64_t)(__TIMCLK__)*16/((__FREQ__) * ((__PSC__) + 1U)) - 16U)) : 0U /** - * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. + * @brief HELPER macro calculating the compare value required to achieve the required timer output compare + * active/inactive delay. * @note ex: @ref __HAL_TIM_CALC_PULSE(1000000, 0, 10); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler @@ -616,9 +625,10 @@ typedef struct / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) /** - * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer output compare active/inactive delay. + * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer + * output compare active/inactive delay. * @note ex: @ref __HAL_TIM_CALC_PULSE_DITHER(1000000, 0, 10); - * @note This macro should be used only if ditehring is already enabled + * @note This macro should be used only if dithering is already enabled * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler * @param __DELAY__ timer output compare active/inactive delay (in us) @@ -629,7 +639,8 @@ typedef struct / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) /** - * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). + * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration + * (when the timer operates in one pulse mode). * @note ex: @ref __HAL_TIM_CALC_PERIOD_BY_DELAY(1000000, 0, 10, 20); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler @@ -642,9 +653,10 @@ typedef struct + __HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__DELAY__)))) /** - * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required pulse duration (when the timer operates in one pulse mode). + * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required + * pulse duration (when the timer operates in one pulse mode). * @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(1000000, 0, 10, 20); - * @note This macro should be used only if ditehring is already enabled + * @note This macro should be used only if dithering is already enabled * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler * @param __DELAY__ timer output compare active/inactive delay (in us) @@ -1095,8 +1107,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM2) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -1113,7 +1124,6 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ @@ -1130,8 +1140,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM4) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -1147,8 +1156,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM5) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -1164,8 +1172,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM8) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -1181,8 +1188,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM15) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -1196,8 +1202,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)))) + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))) #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ @@ -1212,8 +1217,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10))) \ + ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM2) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ @@ -1228,7 +1232,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10) || \ ((__SELECTION__) == TIM_TS_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ @@ -1243,8 +1246,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10))) \ + ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM4) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ @@ -1258,8 +1260,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10))) \ + ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM5) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ @@ -1273,8 +1274,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10))) \ + ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM8) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ @@ -1288,8 +1288,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10))) \ + ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM15) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ @@ -1302,8 +1301,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)))) + ((__SELECTION__) == TIM_TS_ITR8)))) #define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ @@ -1315,7 +1313,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM2) && \ @@ -1327,7 +1324,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_ITR11)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ @@ -1340,7 +1336,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM4) && \ @@ -1352,7 +1347,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM5) && \ @@ -1364,7 +1358,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM8) && \ @@ -1376,7 +1369,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM15) && \ @@ -1388,10 +1380,8 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE)))) - -#else +#elif defined(TIM20) #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ ((((INSTANCE) == TIM1) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -1407,7 +1397,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \ || \ (((INSTANCE) == TIM2) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -1423,7 +1413,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ @@ -1440,7 +1430,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \ || \ (((INSTANCE) == TIM4) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -1456,7 +1446,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \ || \ (((INSTANCE) == TIM8) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -1472,7 +1462,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \ || \ (((INSTANCE) == TIM15) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -1486,7 +1476,291 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)))) + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \ + || \ + (((INSTANCE) == TIM20) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))) + +#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ + ((((INSTANCE) == TIM1) && \ + (((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9))) \ + || \ + (((INSTANCE) == TIM2) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_ITR11))) \ + || \ + (((INSTANCE) == TIM3) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9))) \ + || \ + (((INSTANCE) == TIM4) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9))) \ + || \ + (((INSTANCE) == TIM8) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9))) \ + || \ + (((INSTANCE) == TIM15) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9))) \ + || \ + (((INSTANCE) == TIM20) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8)))) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ + ((((INSTANCE) == TIM1) && \ + (((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM2) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_ITR11)|| \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM3) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM4) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM8) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM15) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM20) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_NONE)))) +#else +#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ + ((((INSTANCE) == TIM1) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ + || \ + (((INSTANCE) == TIM2) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \ + || \ + (((INSTANCE) == TIM3) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ + || \ + (((INSTANCE) == TIM4) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ + || \ + (((INSTANCE) == TIM8) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ + || \ + (((INSTANCE) == TIM15) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))) #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ @@ -1500,8 +1774,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10))) \ + ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM2) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ @@ -1515,7 +1788,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10) || \ ((__SELECTION__) == TIM_TS_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ @@ -1529,8 +1801,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10))) \ + ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM4) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ @@ -1543,8 +1814,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10))) \ + ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM8) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ @@ -1557,8 +1827,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10))) \ + ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM15) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ @@ -1570,8 +1839,7 @@ typedef struct ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)))) + ((__SELECTION__) == TIM_TS_ITR8)))) #define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ @@ -1582,7 +1850,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM2) && \ @@ -1593,7 +1860,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_ITR11)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ @@ -1605,7 +1871,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM4) && \ @@ -1616,7 +1881,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM8) && \ @@ -1627,7 +1891,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM15) && \ @@ -1638,7 +1901,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE)))) #endif /* TIM5 && TIM20 */ @@ -1839,6 +2101,7 @@ void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim); */ /* Extended Peripheral State functions ***************************************/ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); /** * @} */ @@ -1849,7 +2112,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); /* End of exported functions -------------------------------------------------*/ /* Private functions----------------------------------------------------------*/ -/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions +/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions * @{ */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); @@ -1873,5 +2136,3 @@ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); #endif /* STM32G4xx_HAL_TIM_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h index c0443cb..0df466b 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -46,51 +45,54 @@ extern "C" { */ typedef struct { - uint32_t BaudRate; /*!< This member configures the UART communication baud rate. - The baud rate register is computed using the following formula: - LPUART: - ======= - Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) - where lpuart_ker_ck_pres is the UART input clock divided by a prescaler - UART: - ===== - - If oversampling is 16 or in LIN mode, - Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - - If oversampling is 8, - Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4] - Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1 - where uart_ker_ck_pres is the UART input clock divided by a prescaler */ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate register is computed using the following formula: + LPUART: + ======= + Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler + UART: + ===== + - If oversampling is 16 or in LIN mode, + Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) + - If oversampling is 8, + Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where uart_ker_ck_pres is the UART input clock divided by a prescaler */ - uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref UARTEx_Word_Length. */ + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UARTEx_Word_Length. */ - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref UART_Stop_Bits. */ + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits. */ - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref UART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ - uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref UART_Mode. */ + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode. */ - uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref UART_Hardware_Flow_Control. */ + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control. */ - uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8). - This parameter can be a value of @ref UART_Over_Sampling. */ + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, + to achieve higher speed (up to f_PCLK/8). + This parameter can be a value of @ref UART_Over_Sampling. */ - uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. - Selecting the single sample method increases the receiver tolerance to clock - deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ + uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. + Selecting the single sample method increases the receiver tolerance to clock + deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ - uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. - This parameter can be a value of @ref UART_ClockPrescaler. */ + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. + This parameter can be a value of @ref UART_ClockPrescaler. */ } UART_InitTypeDef; @@ -101,7 +103,8 @@ typedef struct { uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several Advanced Features may be initialized at the same time . - This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */ + This parameter can be a value of + @ref UART_Advanced_Features_Initialization_Type. */ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. This parameter can be a value of @ref UART_Tx_Inv. */ @@ -133,11 +136,10 @@ typedef struct This parameter can be a value of @ref UART_MSB_First. */ } UART_AdvFeatureInitTypeDef; - - /** * @brief HAL UART State definition - * @note HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition). + * @note HAL UART State value is a combination of 2 different substates: + * gState and RxState (see @ref UART_State_Definition). * - gState contains UART state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -148,7 +150,7 @@ typedef struct * 11 : Error * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized. HAL UART Init function already called) + * 1 : Init done (Peripheral initialized. HAL UART Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state @@ -165,7 +167,7 @@ typedef struct * xx : Should be set to 00 * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -189,6 +191,17 @@ typedef enum UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ } UART_ClockSourceTypeDef; +/** + * @brief HAL UART Reception type definition + * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. + * It is expected to admit following values : + * HAL_UART_RECEPTION_STANDARD = 0x00U, + * HAL_UART_RECEPTION_TOIDLE = 0x01U, + * HAL_UART_RECEPTION_TORTO = 0x02U, + * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U, + */ +typedef uint32_t HAL_UART_RxTypeTypeDef; + /** * @brief UART handle Structure definition */ @@ -200,7 +213,7 @@ typedef struct __UART_HandleTypeDef UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ uint16_t TxXferSize; /*!< UART Tx Transfer size */ @@ -221,9 +234,11 @@ typedef struct __UART_HandleTypeDef uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ + __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ - void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ @@ -232,11 +247,11 @@ typedef struct __UART_HandleTypeDef HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management - and also related to Tx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ + and also related to Tx operations. This parameter + can be a value of @ref HAL_UART_StateTypeDef */ - __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This + parameter can be a value of @ref HAL_UART_StateTypeDef */ __IO uint32_t ErrorCode; /*!< UART Error code */ @@ -252,6 +267,7 @@ typedef struct __UART_HandleTypeDef void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */ void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */ + void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ @@ -285,7 +301,9 @@ typedef enum /** * @brief HAL UART Callback pointer definition */ -typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_RxEventCallbackTypeDef) +(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ @@ -312,8 +330,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing Value is allowed for RxState only */ #define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ + Not to be used for neither gState nor RxState.Value is result + of combination (Or) between gState and RxState values */ #define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state Value is allowed for gState only */ #define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error @@ -325,14 +343,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_Error_Definition UART Error Definition * @{ */ -#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ -#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ +#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */ + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */ +#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** * @} @@ -429,19 +449,23 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode * @{ */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection on 0x55 frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection + on start bit */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection + on falling edge */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection + on 0x7F frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection + on 0x55 frame detection */ /** * @} */ -/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut +/** @defgroup UART_Receiver_Timeout UART Receiver Timeout * @{ */ -#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART receiver timeout disable */ -#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART receiver timeout enable */ +#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */ +#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */ /** * @} */ @@ -594,8 +618,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_MSB_First UART Advanced Feature MSB First * @{ */ -#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */ -#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */ +#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received + first disable */ +#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received + first enable */ /** * @} */ @@ -621,7 +647,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register * @{ */ -#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ +#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ /** * @} */ @@ -629,9 +655,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection * @{ */ -#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ -#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ -#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */ +#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ +#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ +#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register + not empty or RXFIFO is not empty */ /** * @} */ @@ -648,7 +675,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register * @{ */ -#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB position in CR1 register */ +#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB + position in CR1 register */ /** * @} */ @@ -656,7 +684,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register * @{ */ -#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB position in CR1 register */ +#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB + position in CR1 register */ /** * @} */ @@ -695,6 +724,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ #define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ #define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ +#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */ #define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ #define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ #define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ @@ -730,27 +760,28 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * - ZZZZ : Flag position in the ISR register(4bits) * @{ */ -#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ -#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ -#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ -#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ -#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ -#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ -#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ -#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ -#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ -#define UART_IT_CM 0x112EU /*!< UART character match interruption */ -#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ -#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */ -#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ -#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ -#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ +#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ +#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ +#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ +#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ +#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ +#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ +#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ +#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ +#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ +#define UART_IT_CM 0x112EU /*!< UART character match interruption */ +#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ +#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */ +#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ +#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ +#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ +#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ -#define UART_IT_ERR 0x0060U /*!< UART error interruption */ +#define UART_IT_ERR 0x0060U /*!< UART error interruption */ -#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ -#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ -#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ +#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ +#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ +#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ /** * @} */ @@ -769,10 +800,21 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ #define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ #define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ +#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */ /** * @} */ +/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values + * @{ + */ +#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ +#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ +#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */ +#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */ +/** + * @} + */ /** * @} @@ -822,6 +864,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag * @arg @ref UART_CLEAR_CMF Character Match Clear Flag @@ -890,6 +933,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_FLAG_TC Transmission Complete flag * @arg @ref UART_FLAG_RXNE Receive data register not empty flag * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag + * @arg @ref UART_FLAG_RTOF Receiver Timeout flag * @arg @ref UART_FLAG_IDLE Idle Line detection flag * @arg @ref UART_FLAG_ORE Overrun Error flag * @arg @ref UART_FLAG_NE Noise Error flag @@ -916,15 +960,21 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) * @retval None */ -#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK)))) - +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) /** @brief Disable the specified UART interrupt. * @param __HANDLE__ specifies the UART Handle. @@ -943,14 +993,21 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval None */ -#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK)))) +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) /** @brief Check whether the specified UART interrupt has occurred or not. * @param __HANDLE__ specifies the UART Handle. @@ -969,6 +1026,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) @@ -994,14 +1052,19 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + UART_IT_MASK))) != RESET) ? SET : RESET) /** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the UART Handle. @@ -1013,6 +1076,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag @@ -1067,15 +1131,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ } while(0U) /** @brief Disable CTS flow control. @@ -1085,15 +1150,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ - do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ } while(0U) /** @brief Enable RTS flow control. @@ -1103,15 +1169,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ } while(0U) /** @brief Disable RTS flow control. @@ -1121,15 +1188,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ - do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ } while(0U) /** * @} @@ -1163,8 +1231,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\ - + (uint32_t)((__BAUD__)/2U)) / (__BAUD__))) +#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \ + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)) \ + ) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ UART clock. @@ -1172,8 +1242,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\ - + ((__BAUD__)/2U)) / (__BAUD__)) +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. * @param __PCLK__ UART clock. @@ -1181,8 +1251,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\ - + ((__BAUD__)/2U)) / (__BAUD__)) +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief Check whether or not UART instance is Low Power UART. * @param __HANDLE__ specifies the UART Handle. @@ -1294,8 +1364,15 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __TIMEOUT__ UART receiver timeout setting. * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) */ -#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ - ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) +#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ + ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) + +/** @brief Check the receiver timeout value. + * @note The maximum UART receiver timeout value is 0xFFFFFF. + * @param __TIMEOUTVALUE__ receiver timeout value. + * @retval Test result (TRUE or FALSE) + */ +#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) /** * @brief Ensure that UART LIN state is valid. @@ -1416,8 +1493,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __AUTOBAUDRATE__ UART auto Baud rate state. * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) */ -#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ - ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) +#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \ + UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ + ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) /** * @brief Ensure that UART DMA enabling or disabling on error setting is valid. @@ -1493,7 +1571,6 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /* Include UART HAL Extended module */ #include "stm32g4xx_hal_uart_ex.h" - /* Exported functions --------------------------------------------------------*/ /** @addtogroup UART_Exported_Functions UART Exported Functions * @{ @@ -1517,6 +1594,9 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** @@ -1528,11 +1608,11 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); @@ -1555,6 +1635,8 @@ void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); +void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); + /** * @} */ @@ -1564,6 +1646,10 @@ void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); */ /* Peripheral Control functions ************************************************/ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue); +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart); + HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); @@ -1596,14 +1682,27 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); * @{ */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); -void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +/** + * @} + */ + +/* Private variables -----------------------------------------------------------*/ +/** @defgroup UART_Private_variables UART Private variables + * @{ + */ +/* Prescaler Table used in BRR computation macros. + Declared as extern here to allow use of private UART macros, outside of HAL UART functions */ +extern const uint16_t UARTPrescTable[12]; /** * @} */ @@ -1622,4 +1721,3 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); #endif /* STM32G4xx_HAL_UART_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h index 9838cbe..1408711 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -69,9 +68,9 @@ typedef struct /** @defgroup UARTEx_Word_Length UARTEx Word Length * @{ */ -#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ -#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ -#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ +#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ +#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ +#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ /** * @} */ @@ -79,8 +78,8 @@ typedef struct /** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length * @{ */ -#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ -#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ +#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ /** * @} */ @@ -89,8 +88,8 @@ typedef struct * @brief UART FIFO mode * @{ */ -#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ -#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ /** * @} */ @@ -99,12 +98,12 @@ typedef struct * @brief UART TXFIFO threshold level * @{ */ -#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ -#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ -#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ -#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ -#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ -#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ +#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */ +#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */ /** * @} */ @@ -113,12 +112,12 @@ typedef struct * @brief UART RXFIFO threshold level * @{ */ -#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ -#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ -#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ -#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ -#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ -#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ +#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */ +#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */ /** * @} */ @@ -166,12 +165,20 @@ void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); + HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); + HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); + + /** * @} */ @@ -642,4 +649,3 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 #endif /* STM32G4xx_HAL_UART_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h index 5c53282..11dc3e6 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -58,7 +57,8 @@ extern "C" { #define ADC_SQR3_REGOFFSET (0x00000200UL) #define ADC_SQR4_REGOFFSET (0x00000300UL) -#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) +#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \ + | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */ #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) @@ -95,7 +95,8 @@ extern "C" { #define ADC_JDR3_REGOFFSET (0x00000200UL) #define ADC_JDR4_REGOFFSET (0x00000300UL) -#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) +#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \ + | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) #define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */ @@ -178,7 +179,8 @@ extern "C" { #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH) #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH) #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos) -#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) +#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \ + | ADC_CHANNEL_ID_INTERNAL_CH_MASK) /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */ @@ -200,24 +202,25 @@ extern "C" { /* Definition of channels ID number information to be inserted into */ /* channels literals definition. */ #define ADC_CHANNEL_0_NUMBER (0x00000000UL) -#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 ) -#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 ) -#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 ) -#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 ) -#define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 ) -#define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 ) -#define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 ) -#define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 ) -#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 ) +#define ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1) +#define ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2) +#define ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1) +#define ADC_CHANNEL_7_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3) +#define ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1) +#define ADC_CHANNEL_11_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2) +#define ADC_CHANNEL_13_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_14_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1) +#define ADC_CHANNEL_15_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \ + ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4) +#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1) /* Definition of channels ID bitfield information to be inserted into */ /* channels literals definition. */ @@ -321,7 +324,8 @@ extern "C" { #define ADC_OFR2_REGOFFSET (0x00000001UL) #define ADC_OFR3_REGOFFSET (0x00000002UL) #define ADC_OFR4_REGOFFSET (0x00000003UL) -#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET) +#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \ + | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET) /* ADC registers bits positions */ @@ -344,10 +348,9 @@ extern "C" { #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32G4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32G4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ #define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ -#define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ #define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ - /** * @} */ @@ -394,7 +397,7 @@ typedef struct { uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE - @note On this STM32 serie, if ADC group injected is used, some + @note On this STM32 series, if ADC group injected is used, some clock ratio constraints between ADC clock and AHB clock must be respected. Refer to reference manual. @@ -481,7 +484,7 @@ typedef struct { uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE - @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge + @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge(). @@ -541,7 +544,7 @@ typedef struct { uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE - @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge + @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge(). @@ -615,7 +618,7 @@ typedef struct #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */ #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */ #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */ -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ @@ -648,7 +651,7 @@ typedef struct #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ #if defined(ADC_MULTIMODE_SUPPORT) #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ @@ -683,7 +686,7 @@ typedef struct /* If they are not listed below, they do not require any specific */ /* path enable. In this case, Access to measurement path is done */ /* only by selecting the corresponding ADC internal channel. */ -#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement pathes all disabled */ +#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */ #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSESEL) /*!< ADC measurement path to internal channel temperature sensor */ #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATSEL) /*!< ADC measurement path to internal channel Vbat */ @@ -706,7 +709,7 @@ typedef struct * @{ */ #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ -#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ +#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ /** * @} */ @@ -789,17 +792,17 @@ typedef struct #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ -#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 serie, ADC channel available on all instances but ADC2. */ -#define LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On this STM32 serie, ADC channel available only on ADC1 instance. */ -#define LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_4 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On this STM32 serie, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility */ -#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On this STM32 serie, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility */ -#define LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP1 output. On this STM32 serie, ADC channel available only on ADC1 instance. */ -#define LL_ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2 output. On this STM32 serie, ADC channel available only on ADC2 instance. */ -#define LL_ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 serie, ADC channel available only on ADC2 instance. */ -#define LL_ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 serie, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */ -#define LL_ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_5 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP4 output. On this STM32 serie, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP4 availability */ -#define LL_ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_3 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP5 output. On this STM32 serie, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP5 availability */ -#define LL_ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP6 output. On this STM32 serie, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 & OPAMP6 availability */ +#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 series, ADC channel available on all instances but ADC2. */ +#define LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC1 instance. */ +#define LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_4 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility */ +#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On this STM32 series, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility */ +#define LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP1 output. On this STM32 series, ADC channel available only on ADC1 instance. */ +#define LL_ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2 output. On this STM32 series, ADC channel available only on ADC2 instance. */ +#define LL_ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC2 instance. */ +#define LL_ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */ +#define LL_ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_5 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP4 availability */ +#define LL_ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_3 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP5 availability */ +#define LL_ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP6 output. On this STM32 series, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 & OPAMP6 availability */ /** * @} */ @@ -815,39 +818,39 @@ typedef struct ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM2_CH1 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM4_CH1 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM7_TRGO (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< @@ -858,60 +861,60 @@ typedef struct ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM20_TRGO (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, TIM20 is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_TIM20_TRGO2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, TIM20 is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_TIM20_CH1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, TIM20 is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_TIM20_CH2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_TIM20_CH3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG5 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG6 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG7 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG8 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG9 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG10 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 2. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_REG_TRIG_EXT_LPTIM_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */ /** @@ -1053,33 +1056,33 @@ typedef struct ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< @@ -1090,62 +1093,62 @@ typedef struct ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, TIM20 is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, TIM20 is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Trigger available only on ADC3/4/5 instances. On this STM32 serie, TIM20 is not available on all devices. Refer to device datasheet for more details */ + Trigger available only on ADC3/4/5 instances. On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM20 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Trigger available only on ADC1/2 instances. On this STM32 serie, TIM20 is not available on all devices. Refer to device datasheet for more details */ + Trigger available only on ADC1/2 instances. On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 3. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances. */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances. */ #define LL_ADC_INJ_TRIG_EXT_LPTIM_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */ /** @@ -1499,7 +1502,7 @@ typedef struct /* configuration (system clock versus ADC clock), */ /* and therefore must be defined in user application. */ /* Indications for estimation of ADC timeout delays, for this */ -/* STM32 serie: */ +/* STM32 series: */ /* - ADC calibration time: maximum delay is 112/fADC. */ /* (refer to device datasheet, parameter "tCAL") */ /* - ADC enable time: maximum delay is 1 conversion cycle. */ @@ -1515,28 +1518,28 @@ typedef struct /* Delay set to maximum value (refer to device datasheet, */ /* parameter "tADCVREG_STUP"). */ /* Unit: us */ -#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */ +#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */ /* Delay for internal voltage reference stabilization time. */ /* Delay set to maximum value (refer to device datasheet, */ /* parameter "tstart_vrefint"). */ /* Unit: us */ -#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */ +#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */ /* Delay for temperature sensor stabilization time. */ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART"). */ /* Unit: us */ -#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */ +#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */ /* Delay required between ADC end of calibration and ADC enable. */ -/* Note: On this STM32 serie, a minimum number of ADC clock cycles */ +/* Note: On this STM32 series, a minimum number of ADC clock cycles */ /* are required between ADC end of calibration and ADC enable. */ /* Wait time can be computed in user application by waiting for the */ /* equivalent number of CPU cycles, by taking into account */ /* ratio of CPU clock versus ADC clock prescalers. */ /* Unit: ADC clock cycles. */ -#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */ +#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */ /** * @} @@ -1628,16 +1631,16 @@ typedef struct * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval Value between Min_Data=0 and Max_Data=18 */ #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ - ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \ - ? ( \ + ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \ + ( \ ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \ - ) \ + ) \ : \ ( \ (uint32_t)POSITION_VAL((__CHANNEL__)) \ @@ -1690,7 +1693,7 @@ typedef struct * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, @@ -1698,12 +1701,12 @@ typedef struct * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - (((__DECIMAL_NB__) <= 9UL) \ - ? ( \ + (((__DECIMAL_NB__) <= 9UL) ? \ + ( \ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ - ) \ + ) \ : \ ( \ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ @@ -1768,7 +1771,7 @@ typedef struct * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). @@ -1829,7 +1832,7 @@ typedef struct * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval Returned value can be one of the following values: @@ -1890,11 +1893,11 @@ typedef struct * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. * Value "1" if the internal channel selected is available on the ADC instance selected. */ -#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) +#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ ((((__ADC_INSTANCE__) == ADC1) \ &&( \ @@ -1937,7 +1940,7 @@ typedef struct ) \ ) \ ) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) +#elif defined(STM32G471xx) #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ ((((__ADC_INSTANCE__) == ADC1) \ &&( \ @@ -1954,6 +1957,58 @@ typedef struct ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \ ) \ ) \ + || \ + (((__ADC_INSTANCE__) == ADC3) \ + &&( \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ + ) \ + ) \ + ) +#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) +#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ + ((((__ADC_INSTANCE__) == ADC1) \ + &&( \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ + ) \ + ) \ + || \ + (((__ADC_INSTANCE__) == ADC2) \ + &&( \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \ + ) \ + ) \ + ) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) +#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ + ((((__ADC_INSTANCE__) == ADC1) \ + &&( \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ + ) \ + ) \ + || \ + (((__ADC_INSTANCE__) == ADC2) \ + &&( \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \ + ) \ + ) \ + || \ + (((__ADC_INSTANCE__) == ADC3) \ + &&( \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ + ) \ + ) \ ) #endif @@ -2005,7 +2060,7 @@ typedef struct * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, @@ -2119,7 +2174,7 @@ typedef struct * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. */ #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ @@ -2223,7 +2278,7 @@ typedef struct */ #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST) -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ #if defined(ADC_MULTIMODE_SUPPORT) /** @@ -2259,8 +2314,8 @@ typedef struct : \ (__ADCx__) \ ) -#endif -#endif +#endif /* ADC5 */ +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Helper macro to select the ADC common instance @@ -2285,7 +2340,7 @@ typedef struct ) #else #define __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON) -#endif +#endif /* ADC345_COMMON */ /** * @brief Helper macro to check if all ADC instances sharing the same * ADC common instance are disabled. @@ -2304,6 +2359,7 @@ typedef struct * is enabled. */ #if defined(ADC345_COMMON) +#if defined(ADC4) && defined(ADC5) #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ (((__ADCXY_COMMON__) == ADC12_COMMON) \ ? ( \ @@ -2318,6 +2374,17 @@ typedef struct ) \ ) #else +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + (((__ADCXY_COMMON__) == ADC12_COMMON) \ + ? ( \ + (LL_ADC_IsEnabled(ADC1) | \ + LL_ADC_IsEnabled(ADC2) ) \ + ) \ + : \ + (LL_ADC_IsEnabled(ADC3)) \ + ) +#endif /* ADC4 && ADC5 */ +#else #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2)) #endif @@ -2358,11 +2425,11 @@ typedef struct */ #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ __ADC_RESOLUTION_CURRENT__,\ - __ADC_RESOLUTION_TARGET__) \ - (((__DATA__) \ - << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \ - >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \ - ) + __ADC_RESOLUTION_TARGET__) \ +(((__DATA__) \ + << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \ + >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \ +) /** * @brief Helper macro to calculate the voltage (unit: mVolt) @@ -2382,10 +2449,10 @@ typedef struct */ #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ __ADC_DATA__,\ - __ADC_RESOLUTION__) \ - ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ - / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ - ) + __ADC_RESOLUTION__) \ +((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ +) /** * @brief Helper macro to calculate analog reference voltage (Vref+) @@ -2397,7 +2464,7 @@ typedef struct * connected to pin Vref+. * On devices with small package, the pin Vref+ is not present * and internally bonded to pin Vdda. - * @note On this STM32 serie, calibration data of internal voltage reference + * @note On this STM32 series, calibration data of internal voltage reference * VrefInt corresponds to a resolution of 12 bits, * this is the recommended ADC resolution to convert voltage of * internal voltage reference VrefInt. @@ -2413,11 +2480,12 @@ typedef struct * @retval Analog reference voltage (unit: mV) */ #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ - / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ - (__ADC_RESOLUTION__), \ - LL_ADC_RESOLUTION_12B)) + __ADC_RESOLUTION__) \ +(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ + / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_12B) \ +) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) @@ -2446,7 +2514,7 @@ typedef struct * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @note On this STM32 serie, calibration data of temperature sensor + * @note On this STM32 series, calibration data of temperature sensor * corresponds to a resolution of 12 bits, * this is the recommended ADC resolution to convert voltage of * temperature sensor. @@ -2466,17 +2534,17 @@ typedef struct */ #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ - (__ADC_RESOLUTION__), \ - LL_ADC_RESOLUTION_12B) \ - * (__VREFANALOG_VOLTAGE__)) \ - / TEMPSENSOR_CAL_VREFANALOG) \ - - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ - ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ - ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ - ) + TEMPSENSOR_CAL1_TEMP \ - ) + __ADC_RESOLUTION__) \ +(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_12B) \ + * (__VREFANALOG_VOLTAGE__)) \ + / TEMPSENSOR_CAL_VREFANALOG) \ + - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ + ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ + ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ + ) + TEMPSENSOR_CAL1_TEMP \ +) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) @@ -2527,18 +2595,17 @@ typedef struct __TEMPSENSOR_CALX_TEMP__,\ __VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - ((( ( \ - (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ - / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ - * 1000UL) \ - - \ - (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ - * 1000UL) \ - ) \ - ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \ - ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \ - ) + __ADC_RESOLUTION__) \ +(((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ + * 1000UL) \ + - \ + (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ + * 1000UL) \ + ) \ + ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \ + ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \ +) /** * @} @@ -2594,7 +2661,7 @@ typedef struct #if defined(ADC_MULTIMODE_SUPPORT) __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) { - register uint32_t data_reg_addr; + uint32_t data_reg_addr; if (Register == LL_ADC_DMA_REG_REGULAR_DATA) { @@ -2618,7 +2685,7 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Regis /* Retrieve address of register DR */ return (uint32_t) &(ADCx->DR); } -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @} @@ -2630,11 +2697,11 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Regis /** * @brief Set parameter common to several ADC: Clock source and prescaler. - * @note On this STM32 serie, if ADC group injected is used, some + * @note On this STM32 series, if ADC group injected is used, some * clock ratio constraints between ADC clock and AHB clock * must be respected. * Refer to reference manual. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * This check can be done with function @ref LL_ADC_IsEnabled() for each @@ -2696,11 +2763,13 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) } /** - * @brief Set parameter common to several ADC: measurement path to internal - * channels (VrefInt, temperature sensor, ...). + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Configure all paths (overwrite current configuration). * @note One or several values can be selected. * Example: (LL_ADC_PATH_INTERNAL_VREFINT | * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * The values not selected are removed from configuration. * @note Stabilization time of measurement path to internal channel: * After enabling internal paths, before starting ADC conversion, * a delay is required for internal voltage reference and @@ -2729,6 +2798,65 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_CO MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal); } +/** + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Add paths to the current configuration. + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @note Stabilization time of measurement path to internal channel: + * After enabling internal paths, before starting ADC conversion, + * a delay is required for internal voltage reference and + * temperature sensor stabilization time. + * Refer to device datasheet. + * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. + * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. + * @note ADC internal channel sampling time constraint: + * For ADC conversion of internal channels, + * a sampling time minimum value is required. + * Refer to device datasheet. + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n + * CCR VSENSESEL LL_ADC_SetCommonPathInternalChAdd\n + * CCR VBATSEL LL_ADC_SetCommonPathInternalChAdd + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @arg @ref LL_ADC_PATH_INTERNAL_VBAT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + SET_BIT(ADCxy_COMMON->CCR, PathInternal); +} + +/** + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Remove paths to the current configuration. + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n + * CCR VSENSESEL LL_ADC_SetCommonPathInternalChRem\n + * CCR VBATSEL LL_ADC_SetCommonPathInternalChRem + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @arg @ref LL_ADC_PATH_INTERNAL_VBAT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal); +} + /** * @brief Get parameter common to several ADC: measurement path to internal * channels (VrefInt, temperature sensor, ...). @@ -2776,7 +2904,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCx * both calibration factors must be concatenated. * To perform this processing, use helper macro * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled, without calibration on going, without conversion * on going on group regular. @@ -2819,14 +2947,16 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t /* "SingleDiff". */ /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */ /* containing other bits reserved for other purpose. */ - return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)); + return (uint32_t)(READ_BIT(ADCx->CALFACT, + (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> + ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)); } /** * @brief Set ADC resolution. * Refer to reference manual for alignments formats * dependencies to ADC resolutions. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -2865,7 +2995,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) * @brief Set ADC conversion data alignment. * @note Refer to reference manual for alignments formats * dependencies to ADC resolutions. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -2913,9 +3043,12 @@ __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) * Moreover, this avoids risk of overrun for low frequency * applications. * How to use this low power mode: - * - Do not use with interruption or DMA since these modes - * have to clear immediately the EOC flag to free the - * IRQ vector sequencer. + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). * - Do use with polling: 1. Start conversion, * 2. Later on, when conversion data is needed: poll for end of * conversion to ensure that conversion is completed and @@ -2933,7 +3066,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) * Therefore, the ADC conversion data may be outdated: does not * correspond to the current voltage level on the selected * ADC channel. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -2966,9 +3099,12 @@ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPower * Moreover, this avoids risk of overrun for low frequency * applications. * How to use this low power mode: - * - Do not use with interruption or DMA since these modes - * have to clear immediately the EOC flag to free the - * IRQ vector sequencer. + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). * - Do use with polling: 1. Start conversion, * 2. Later on, when conversion data is needed: poll for end of * conversion to ensure that conversion is completed and @@ -3012,7 +3148,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) * to disable state using function LL_ADC_SetOffsetState(). * @note If a channel is mapped on several offsets numbers, only the offset * with the lowest value is considered for the subtraction. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -3075,7 +3211,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF @@ -3083,7 +3219,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); MODIFY_REG(*preg, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, @@ -3157,7 +3293,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, @@ -3166,7 +3302,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); } @@ -3192,7 +3328,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Off */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1); } @@ -3204,7 +3340,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offse * @note This function should be needed only in case of offset to be * enabled-disabled dynamically, and should not be needed in other cases: * function LL_ADC_SetOffset() automatically enables the offset. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -3225,7 +3361,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offse */ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); MODIFY_REG(*preg, ADC_OFR1_OFFSET1_EN, @@ -3251,7 +3387,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN); } @@ -3259,7 +3395,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offse /** * @brief Set for the ADC selected offset number 1, 2, 3 or 4: * choose offset sign. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -3280,7 +3416,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offse */ __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); MODIFY_REG(*preg, ADC_OFR1_OFFSETPOS, @@ -3306,7 +3442,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, u */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSETPOS); } @@ -3314,7 +3450,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offset /** * @brief Set for the ADC selected offset number 1, 2, 3 or 4: * choose offset saturation mode. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -3335,7 +3471,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offset */ __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); MODIFY_REG(*preg, ADC_OFR1_SATEN, @@ -3361,7 +3497,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offs */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_SATEN); } @@ -3373,8 +3509,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t * DATA = DATA(raw) * (gain compensation coef) / 4096 * @note This function enables the gain compensation if given * coefficient is above 0, otherwise it disables it. - * @note Gain compensation when enabled is appied to all channels. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note Gain compensation when enabled is applied to all channels. + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -3410,7 +3546,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(ADC_TypeDef *ADCx) /** * @brief Set ADC sampling time common configuration impacting * settings of sampling time channel wise. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -3453,7 +3589,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx) * @brief Set ADC group regular conversion trigger source: * internal (SW start) or from external peripheral (timer event, * external interrupt line). - * @note On this STM32 serie, setting trigger source to external trigger + * @note On this STM32 series, setting trigger source to external trigger * also set trigger polarity to rising edge * (default setting for compatibility with some ADC on other * STM32 families having this setting set by HW default value). @@ -3461,7 +3597,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx) * function @ref LL_ADC_REG_SetTriggerEdge(). * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -3510,9 +3646,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT * - * (1) On STM32G4 serie, parameter not available on all ADC instances: ADC1, ADC2.\n - * (2) On STM32G4 serie, parameter not available on all ADC instances: ADC3, ADC4, ADC5. - * On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n + * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) @@ -3577,17 +3713,17 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT * - * (1) On STM32G4 serie, parameter not available on all ADC instances: ADC1, ADC2.\n - * (2) On STM32G4 serie, parameter not available on all ADC instances: ADC3, ADC4, ADC5. - * On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n + * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. */ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) { - register __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); + __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */ - register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */ /* to match with triggers literals definition. */ @@ -3616,7 +3752,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) /** * @brief Set ADC group regular conversion trigger polarity. * @note Applicable only for trigger source set to external trigger. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -3652,8 +3788,8 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) * @brief Set ADC sampling mode. * @note This function set the ADC conversion sampling mode * @note This mode applies to regular group only. - * @note Set sampling mode is appied to all conversion of regular group. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note Set sampling mode is applied to all conversion of regular group. + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -3715,7 +3851,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(ADC_TypeDef *ADCx) * function "LL_ADC_REG_SetSequencerChannels()". * @note Sequencer disabled is equivalent to sequencer of 1 rank: * ADC conversion on only 1 channel. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -3807,7 +3943,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) * continuous mode and sequencer discontinuous mode. * @note It is not possible to enable both ADC auto-injected mode * and ADC group regular sequencer discontinuous mode. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -3860,17 +3996,17 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) * @note This function performs configuration of: * - Channels ordering into each rank of scan sequence: * whatever channel can be placed into whatever rank. - * @note On this STM32 serie, ADC group regular sequencer is + * @note On this STM32 series, ADC group regular sequencer is * fully configurable: sequencer length and each rank * affectation to a channel are configurable. * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). * @note Depending on devices and packages, some channels may not be available. * Refer to device datasheet for channels availability. - * @note On this STM32 serie, to measure internal channels (VrefInt, + * @note On this STM32 series, to measure internal channels (VrefInt, * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -3947,7 +4083,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval None @@ -3958,7 +4094,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); MODIFY_REG(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), @@ -3968,7 +4104,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /** * @brief Get ADC group regular sequence: channel on the selected * scan sequence rank. - * @note On this STM32 serie, ADC group regular sequencer is + * @note On this STM32 series, ADC group regular sequencer is * fully configurable: sequencer length and each rank * affectation to a channel are configurable. * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). @@ -4058,7 +4194,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, @@ -4067,7 +4203,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); return (uint32_t)((READ_BIT(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) @@ -4083,7 +4219,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_ * conversions launched successively automatically. * @note It is not possible to enable both ADC group regular * continuous mode and sequencer discontinuous mode. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -4138,7 +4274,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) * settings are available using function @ref LL_ADC_SetMultiDMATransfer(). * @note To configure DMA source address (peripheral address), * use function @ref LL_ADC_DMA_GetRegAddr(). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -4200,7 +4336,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) * The default setting of overrun is data preserved. * Therefore, for compatibility with all devices, parameter * overrun should be set to data overwritten. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -4242,7 +4378,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) * @brief Set ADC group injected conversion trigger source: * internal (SW start) or from external peripheral (timer event, * external interrupt line). - * @note On this STM32 serie, setting trigger source to external trigger + * @note On this STM32 series, setting trigger source to external trigger * also set trigger polarity to rising edge * (default setting for compatibility with some ADC on other * STM32 families having this setting set by HW default value). @@ -4250,7 +4386,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) * function @ref LL_ADC_INJ_SetTriggerEdge(). * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. @@ -4298,9 +4434,9 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT * - * (1) On STM32G4 serie, parameter not available on all ADC instances: ADC1, ADC2.\n - * (2) On STM32G4 serie, parameter not available on all ADC instances: ADC3, ADC4, ADC5. - * On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n + * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * @retval None */ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) @@ -4364,17 +4500,17 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT * - * (1) On STM32G4 serie, parameter not available on all ADC instances: ADC1, ADC2.\n - * (2) On STM32G4 serie, parameter not available on all ADC instances: ADC3, ADC4, ADC5. - * On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n + * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) { - register __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); + __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */ - register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL)); /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */ /* to match with triggers literals definition. */ @@ -4403,7 +4539,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) /** * @brief Set ADC group injected conversion trigger polarity. * Applicable only for trigger source set to external trigger. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. @@ -4443,7 +4579,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) * scan direction is forward (from rank 1 to rank n). * @note Sequencer disabled is equivalent to sequencer of 1 rank: * ADC conversion on only 1 channel. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. @@ -4520,13 +4656,13 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) * sequence rank. * @note Depending on devices and packages, some channels may not be available. * Refer to device datasheet for channels availability. - * @note On this STM32 serie, to measure internal channels (VrefInt, + * @note On this STM32 series, to measure internal channels (VrefInt, * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). * @note On STM32G4, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN1..5). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. @@ -4579,7 +4715,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval None @@ -4660,7 +4796,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, @@ -4694,7 +4830,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_ * from ADC group regular. * @note It is not possible to enable both ADC group injected * auto-injected mode and sequencer discontinuous mode. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -4752,7 +4888,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) * on either groups regular or injected. * @note A modification of the context mode (bit JQDIS) causes the contexts * queue to be flushed and the register JSQR is cleared. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -4802,13 +4938,13 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_INJ_GetTriggerSource() * @arg @ref LL_ADC_INJ_GetTriggerEdge() * @arg @ref LL_ADC_INJ_GetSequencerRanks() - * @note On this STM32 serie, to measure internal channels (VrefInt, + * @note On this STM32 series, to measure internal channels (VrefInt, * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). * @note On STM32G4, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN1..5). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. @@ -4861,9 +4997,9 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT * - * (1) On STM32G4 serie, parameter not available on all ADC instances: ADC1, ADC2.\n - * (2) On STM32G4 serie, parameter not available on all ADC instances: ADC3, ADC4, ADC5. - * On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n + * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * @param ExternalTriggerEdge This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING @@ -4915,7 +5051,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @param Rank2_Channel This parameter can be one of the following values: @@ -4957,7 +5093,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @param Rank3_Channel This parameter can be one of the following values: @@ -4999,7 +5135,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @param Rank4_Channel This parameter can be one of the following values: @@ -5041,7 +5177,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval None @@ -5061,7 +5197,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, /* because containing other bits reserved for other purpose. */ /* If parameter "TriggerSource" is set to SW start, then parameter */ /* "ExternalTriggerEdge" is discarded. */ - register uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL); + uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL); MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | @@ -5070,7 +5206,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 | ADC_JSQR_JL, - TriggerSource | + (TriggerSource & ADC_JSQR_JEXTSEL) | (ExternalTriggerEdge * (is_trigger_not_sw)) | (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) | (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) | @@ -5101,7 +5237,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, * Refer to device datasheet for timings values (parameters TS_vrefint, * TS_temp, ...). * @note Conversion time is the addition of sampling time and processing time. - * On this STM32 serie, ADC processing time is: + * On this STM32 series, ADC processing time is: * - 12.5 ADC clock cycles at ADC resolution 12 bits * - 10.5 ADC clock cycles at ADC resolution 10 bits * - 8.5 ADC clock cycles at ADC resolution 8 bits @@ -5110,7 +5246,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, * temperature sensor, ...), a sampling time minimum value * is required. * Refer to device datasheet. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -5173,7 +5309,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @param SamplingTime This parameter can be one of the following values: @@ -5197,7 +5333,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); MODIFY_REG(*preg, ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), @@ -5210,7 +5346,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * @note On this device, sampling time is on channel scope: independently * of channel mapped on ADC group regular or injected. * @note Conversion time is the addition of sampling time and processing time. - * On this STM32 serie, ADC processing time is: + * On this STM32 series, ADC processing time is: * - 12.5 ADC clock cycles at ADC resolution 12 bits * - 10.5 ADC clock cycles at ADC resolution 10 bits * - 8.5 ADC clock cycles at ADC resolution 8 bits @@ -5274,7 +5410,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval Returned value can be one of the following values: @@ -5293,7 +5429,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C */ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); return (uint32_t)(READ_BIT(*preg, ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)) @@ -5328,7 +5464,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32 * @note For ADC channels configured in differential mode, both inputs * should be biased at (Vref+)/2 +/-200mV. * (Vref+ is the analog voltage reference) - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @note One or several values can be selected. @@ -5358,12 +5494,20 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32 */ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff) { - /* Bits of channels in single or differential mode are set only for */ - /* differential mode (for single mode, mask of bits allowed to be set is */ - /* shifted out of range of bits of channels in single or differential mode. */ - MODIFY_REG(ADCx->DIFSEL, - Channel & ADC_SINGLEDIFF_CHANNEL_MASK, - (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); + /* Bits for single or differential mode selection for each channel are set */ + /* to 1 only when the differential mode is selected, and to 0 when the */ + /* single mode is selected. */ + + if (SingleDiff == LL_ADC_DIFFERENTIAL_ENDED) + { + SET_BIT(ADCx->DIFSEL, + Channel & ADC_SINGLEDIFF_CHANNEL_MASK); + } + else + { + CLEAR_BIT(ADCx->DIFSEL, + Channel & ADC_SINGLEDIFF_CHANNEL_MASK); + } } /** @@ -5435,7 +5579,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t * @note In case of need to define a single channel to monitor * with analog watchdog from sequencer channel definition, * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). - * @note On this STM32 serie, there are 2 kinds of analog watchdog + * @note On this STM32 series, there are 2 kinds of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. @@ -5456,7 +5600,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t * - resolution: resolution is limited to 8 bits: if ADC resolution is * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits * the 2 LSB are ignored. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -5575,7 +5719,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * @retval None */ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup) @@ -5584,8 +5728,8 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t /* in register and register position depending on parameter "AWDy". */ /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ /* containing other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) - + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); MODIFY_REG(*preg, (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), @@ -5607,7 +5751,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). * Applicable only when the analog watchdog is set to monitor * one channel. - * @note On this STM32 serie, there are 2 kinds of analog watchdog + * @note On this STM32 series, there are 2 kinds of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. @@ -5628,7 +5772,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * - resolution: resolution is limited to 8 bits: if ADC resolution is * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits * the 2 LSB are ignored. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -5716,10 +5860,10 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) - + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); - register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); + uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & ADC_AWD_CR_ALL_CHANNEL_MASK); /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */ /* (parameter value LL_ADC_AWD_DISABLE). */ @@ -5778,7 +5922,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint * @note In case of ADC resolution different of 12 bits, * analog watchdog thresholds data require a specific shift. * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). - * @note On this STM32 serie, there are 2 kinds of analog watchdog + * @note On this STM32 series, there are 2 kinds of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. @@ -5826,7 +5970,7 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t /* "AWDy". */ /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ /* containing other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); MODIFY_REG(*preg, ADC_TR1_HT1 | ADC_TR1_LT1, @@ -5841,7 +5985,7 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t * @note In case of ADC resolution different of 12 bits, * analog watchdog thresholds data require a specific shift. * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). - * @note On this STM32 serie, there are 2 kinds of analog watchdog + * @note On this STM32 series, there are 2 kinds of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. @@ -5866,7 +6010,7 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t * impacted: the comparison of analog watchdog thresholds is done on * oversampling final computation (after ratio and shift application): * ADC data register bitfield [15:4] (12 most significant bits). - * @note On this STM32 serie, setting of this feature is not conditioned to + * @note On this STM32 series, setting of this feature is not conditioned to * ADC state: * ADC can be disabled, enabled with or without conversion on going * on either ADC groups regular or injected. @@ -5895,7 +6039,8 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW /* "AWDThresholdsHighLow" and "AWDy". */ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ /* containing other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, + ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); MODIFY_REG(*preg, AWDThresholdsHighLow, @@ -5932,21 +6077,22 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, + ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); return (uint32_t)(READ_BIT(*preg, (AWDThresholdsHighLow | ADC_TR1_LT1)) - >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1)) - ); + >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) + & ~(AWDThresholdsHighLow & ADC_TR1_LT1))); } /** * @brief Set ADC analog watchdog filtering configuration - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. - * @note On this STM32 serie, this feature is only available on first + * @note On this STM32 series, this feature is only available on first * analog watchdog (AWD1) * @rmtoll TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration * @param ADCx ADC instance @@ -5972,7 +6118,7 @@ __STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint /** * @brief Get ADC analog watchdog filtering configuration - * @note On this STM32 serie, this feature is only available on first + * @note On this STM32 series, this feature is only available on first * analog watchdog (AWD1) * @rmtoll TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration * @param ADCx ADC instance @@ -6012,7 +6158,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, * the oversampling on ADC group regular is either * temporary stopped and continued, or resumed from start * (oversampler buffer reset). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -6066,11 +6212,11 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) * are done from 1 trigger) * - discontinuous mode (each conversion of oversampling ratio * needs a trigger) - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. - * @note On this STM32 serie, oversampling discontinuous mode + * @note On this STM32 series, oversampling discontinuous mode * (triggered mode) can be used only when oversampling is * set on group regular only and in resumed mode. * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont @@ -6110,7 +6256,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) * @note This function set the 2 items of oversampling configuration: * - ratio * - shift - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -6199,7 +6345,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) * @note If multimode configuration: the selected ADC instance is * either master or slave depending on hardware. * Refer to reference manual. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * This check can be done with function @ref LL_ADC_IsEnabled() for each @@ -6278,7 +6424,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) * A macro is available to get the conversion data of * ADC master or ADC slave: see helper macro * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled * or enabled without conversion on going on group regular. @@ -6352,7 +6498,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_CO * - ADC resolution 10 bits can have maximum delay of 10 cycles. * - ADC resolution 8 bits can have maximum delay of 8 cycles. * - ADC resolution 6 bits can have maximum delay of 6 cycles. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * This check can be done with function @ref LL_ADC_IsEnabled() for each @@ -6427,7 +6573,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADC * state, the internal analog calibration is lost. After exiting from * deep power down, calibration must be relaunched or calibration factor * (preliminarily saved) must be set back into calibration register. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown @@ -6450,7 +6596,7 @@ __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx) * state, the internal analog calibration is lost. After exiting from * deep power down, calibration must be relaunched or calibration factor * (preliminarily saved) must be set back into calibration register. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown @@ -6478,12 +6624,12 @@ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) /** * @brief Enable ADC instance internal voltage regulator. - * @note On this STM32 serie, after ADC internal voltage regulator enable, + * @note On this STM32 series, after ADC internal voltage regulator enable, * a delay for ADC internal voltage regulator stabilization * is required before performing a ADC calibration or ADC enable. * Refer to device datasheet, parameter tADCVREG_STUP. * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator @@ -6502,7 +6648,7 @@ __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) /** * @brief Disable ADC internal voltage regulator. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator @@ -6527,14 +6673,14 @@ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) /** * @brief Enable the selected ADC instance. - * @note On this STM32 serie, after ADC enable, a delay for + * @note On this STM32 series, after ADC enable, a delay for * ADC internal analog stabilization is required before performing a * ADC conversion start. * Refer to device datasheet, parameter tSTAB. - * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled and ADC internal voltage regulator enabled. * @rmtoll CR ADEN LL_ADC_Enable @@ -6553,7 +6699,7 @@ __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) /** * @brief Disable the selected ADC instance. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be not disabled. Must be enabled without conversion on going * on either groups regular or injected. @@ -6573,7 +6719,7 @@ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) /** * @brief Get the selected ADC instance enable state. - * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) * @rmtoll CR ADEN LL_ADC_IsEnabled @@ -6599,7 +6745,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) /** * @brief Start ADC calibration in the mode single-ended * or differential (for devices with differential mode available). - * @note On this STM32 serie, a minimum number of ADC clock cycles + * @note On this STM32 series, a minimum number of ADC clock cycles * are required between ADC end of calibration and ADC enable. * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. * @note For devices with differential mode available: @@ -6608,7 +6754,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) * (calibration run must be performed for each of these * differential modes, if used afterwards and if the application * requires their calibration). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR ADCAL LL_ADC_StartCalibration\n @@ -6650,14 +6796,14 @@ __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) /** * @brief Start ADC group regular conversion. - * @note On this STM32 serie, this function is relevant for both + * @note On this STM32 series, this function is relevant for both * internal trigger (SW start) and external trigger: * - If ADC trigger has been set to software start, ADC conversion * starts immediately. * - If ADC trigger has been set to external trigger, ADC conversion * will start at next trigger event (on the selected trigger edge) * following the ADC start conversion command. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group regular, * without conversion stop command on going on group regular, @@ -6678,7 +6824,7 @@ __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) /** * @brief Stop ADC group regular conversion. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled with conversion on going on group regular, * without ADC disable command on going. @@ -6724,7 +6870,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set * using @ref LL_ADC_REG_SetSamplingMode * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group regular, * without conversion stop command on going on group regular, @@ -6746,7 +6892,7 @@ __STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx) * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source * - @ref LL_ADC_REG_StartSamplingPhase has been called to start * the sampling phase - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group regular, * without conversion stop command on going on group regular, @@ -6875,14 +7021,14 @@ __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef /** * @brief Start ADC group injected conversion. - * @note On this STM32 serie, this function is relevant for both + * @note On this STM32 series, this function is relevant for both * internal trigger (SW start) and external trigger: * - If ADC trigger has been set to software start, ADC conversion * starts immediately. * - If ADC trigger has been set to external trigger, ADC conversion * will start at next trigger event (on the selected trigger edge) * following the ADC start conversion command. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group injected, * without conversion stop command on going on group injected, @@ -6903,7 +7049,7 @@ __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx) /** * @brief Stop ADC group injected conversion. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled with conversion on going on group injected, * without ADC disable command on going. @@ -6944,7 +7090,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) } /** - * @brief Get ADC group regular conversion data, range fit for + * @brief Get ADC group injected conversion data, range fit for * all ADC configurations: all ADC resolutions and * all oversampling increased data width (for devices * with feature oversampling). @@ -6962,7 +7108,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6989,7 +7135,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -7016,7 +7162,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -7043,7 +7189,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -7070,7 +7216,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32 */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -7087,7 +7233,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32 /** * @brief Get flag ADC ready. - * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY @@ -7211,7 +7357,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) /** * @brief Clear flag ADC ready. - * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY @@ -8035,5 +8181,3 @@ void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); #endif #endif /* STM32G4xx_LL_ADC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h index 09231f7..8641c9f 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h @@ -23,14 +23,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -1680,4 +1678,3 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs) #endif /* STM32G4xx_LL_BUS_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cortex.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cortex.h index c3faec6..a0283f2 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cortex.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cortex.h @@ -3,6 +3,17 @@ * @file stm32g4xx_ll_cortex.h * @author MCD Application Team * @brief Header file of CORTEX LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -10,7 +21,7 @@ [..] The LL CORTEX driver contains a set of generic APIs that can be used by user: - (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick + (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick functions (+) Low power mode configuration (SCB register of Cortex-MCU) (+) MPU API to configure and enable regions @@ -18,18 +29,6 @@ (+) API to enable fault handler (SHCSR accesses) @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -636,4 +635,3 @@ __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) #endif /* __STM32G4xx_LL_CORTEX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crs.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crs.h index eb09374..054d572 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crs.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crs.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -94,7 +93,7 @@ extern "C" { /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source * @{ */ -#define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal soucre GPIO */ +#define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal source GPIO */ #define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ #define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ /** @@ -780,4 +779,3 @@ ErrorStatus LL_CRS_DeInit(void); #endif /* __STM32G4xx_LL_CRS_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h index 627b849..76dfbf0 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -272,17 +271,17 @@ typedef struct /** @defgroup DMA_LL_EC_CHANNEL CHANNEL * @{ */ -#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ -#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ -#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ -#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ -#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ -#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ +#define LL_DMA_CHANNEL_1 0x00000000U /*!< DMA Channel 1 */ +#define LL_DMA_CHANNEL_2 0x00000001U /*!< DMA Channel 2 */ +#define LL_DMA_CHANNEL_3 0x00000002U /*!< DMA Channel 3 */ +#define LL_DMA_CHANNEL_4 0x00000003U /*!< DMA Channel 4 */ +#define LL_DMA_CHANNEL_5 0x00000004U /*!< DMA Channel 5 */ +#define LL_DMA_CHANNEL_6 0x00000005U /*!< DMA Channel 6 */ #if defined (DMA1_Channel7) -#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ +#define LL_DMA_CHANNEL_7 0x00000006U /*!< DMA Channel 7 */ #endif /* DMA1_Channel7 */ #if defined (DMA1_Channel8) -#define LL_DMA_CHANNEL_8 0x00000008U /*!< DMA Channel 8 */ +#define LL_DMA_CHANNEL_8 0x00000007U /*!< DMA Channel 8 */ #endif /* DMA1_Channel8 */ #if defined(USE_FULL_LL_DRIVER) #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ @@ -517,9 +516,8 @@ typedef struct */ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_EN); } /** @@ -540,9 +538,8 @@ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_EN); } /** @@ -563,9 +560,8 @@ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL); } @@ -602,9 +598,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, Configuration); } @@ -632,9 +627,8 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, */ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); } @@ -660,9 +654,8 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM)); } @@ -689,9 +682,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint */ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_CIRC, Mode); } @@ -715,9 +707,8 @@ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_ */ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_CIRC)); } @@ -742,9 +733,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_PINC, PeriphOrM2MSrcIncMode); } @@ -768,9 +758,8 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_PINC)); } @@ -795,9 +784,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_MINC, MemoryOrM2MDstIncMode); } @@ -821,9 +809,8 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_MINC)); } @@ -849,9 +836,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_PSIZE, PeriphOrM2MSrcDataSize); } @@ -876,9 +862,8 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_PSIZE)); } @@ -904,9 +889,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channe */ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_MSIZE, MemoryOrM2MDstDataSize); } @@ -931,9 +915,8 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_MSIZE)); } @@ -960,9 +943,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channe */ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_PL, Priority); } @@ -988,9 +970,8 @@ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_PL)); } @@ -1015,9 +996,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint3 */ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CNDTR, DMA_CNDTR_NDT, NbData); } @@ -1041,16 +1021,15 @@ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CNDTR, DMA_CNDTR_NDT)); } /** * @brief Configure the Source and Destination addresses. * @note This API must not be called when the DMA channel is enabled. - * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). + * @note Each IP using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr). * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n * CMAR MA LL_DMA_ConfigAddresses * @param DMAx DMAx Instance @@ -1075,19 +1054,19 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channe __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; /* Direction Memory to Periph */ if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) { - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, DstAddress); } /* Direction Periph to Memory and Memory to Memory */ else { - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, DstAddress); } } @@ -1112,9 +1091,8 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, */ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, MemoryAddress); } /** @@ -1138,9 +1116,8 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, PeriphAddress); } /** @@ -1162,9 +1139,8 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR)); } /** @@ -1186,9 +1162,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR)); } /** @@ -1212,9 +1187,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, MemoryAddress); } /** @@ -1238,9 +1212,8 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, MemoryAddress); } /** @@ -1262,9 +1235,8 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR)); } /** @@ -1286,9 +1258,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR)); } /** @@ -1313,6 +1284,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMA_CHANNEL_8 (*) * (*) Not on all G4 devices * @param PeriphRequest This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM * @arg @ref LL_DMAMUX_REQ_GENERATOR0 * @arg @ref LL_DMAMUX_REQ_GENERATOR1 * @arg @ref LL_DMAMUX_REQ_GENERATOR2 @@ -1433,9 +1405,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest) { - UNUSED(DMAx); - MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Channel - 1U))))->CCR, - DMAMUX_CxCR_DMAREQ_ID, PeriphRequest); + uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 8U); + MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, PeriphRequest); } /** @@ -1459,6 +1430,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_DMA_CHANNEL_8 (*) * (*) Not on all G4 devices * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM * @arg @ref LL_DMAMUX_REQ_GENERATOR0 * @arg @ref LL_DMAMUX_REQ_GENERATOR1 * @arg @ref LL_DMAMUX_REQ_GENERATOR2 @@ -1578,9 +1550,8 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) { - UNUSED(DMAx); - return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * - (Channel - 1U)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); + uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 8U); + return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID)); } /** @@ -1961,6 +1932,10 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx) /** * @brief Clear Channel 1 global interrupt flag. + * @note Do not Clear Channel 1 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1, + LL_DMA_ClearFlag_TE1. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 * @param DMAx DMAx Instance * @retval None @@ -1972,6 +1947,10 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) /** * @brief Clear Channel 2 global interrupt flag. + * @note Do not Clear Channel 2 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2, + LL_DMA_ClearFlag_TE2. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 * @param DMAx DMAx Instance * @retval None @@ -1983,6 +1962,10 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) /** * @brief Clear Channel 3 global interrupt flag. + * @note Do not Clear Channel 3 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3, + LL_DMA_ClearFlag_TE3. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 * @param DMAx DMAx Instance * @retval None @@ -1994,6 +1977,10 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) /** * @brief Clear Channel 4 global interrupt flag. + * @note Do not Clear Channel 4 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4, + LL_DMA_ClearFlag_TE4. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 * @param DMAx DMAx Instance * @retval None @@ -2005,6 +1992,10 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) /** * @brief Clear Channel 5 global interrupt flag. + * @note Do not Clear Channel 5 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5, + LL_DMA_ClearFlag_TE5. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 * @param DMAx DMAx Instance * @retval None @@ -2016,6 +2007,10 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) /** * @brief Clear Channel 6 global interrupt flag. + * @note Do not Clear Channel 6 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6, + LL_DMA_ClearFlag_TE6. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 * @param DMAx DMAx Instance * @retval None @@ -2028,6 +2023,10 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) #if defined (DMA1_Channel7) /** * @brief Clear Channel 7 global interrupt flag. + * @note Do not Clear Channel 7 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7, + LL_DMA_ClearFlag_TE7. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 * @param DMAx DMAx Instance * @retval None @@ -2041,6 +2040,10 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) #if defined (DMA1_Channel8) /** * @brief Clear Channel 8 global interrupt flag. + * @note Do not Clear Channel 8 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC8, LL_DMA_ClearFlag_HT8, + LL_DMA_ClearFlag_TE8. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF8 LL_DMA_ClearFlag_GI8 * @param DMAx DMAx Instance * @retval None @@ -2352,9 +2355,8 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TCIE); } /** @@ -2375,9 +2377,8 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_HTIE); } /** @@ -2398,9 +2399,8 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TEIE); } /** @@ -2421,9 +2421,8 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TCIE); } /** @@ -2444,9 +2443,8 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_HTIE); } /** @@ -2467,9 +2465,8 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TEIE); } /** @@ -2490,9 +2487,8 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL); } @@ -2514,9 +2510,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Chann */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL); } @@ -2538,9 +2533,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Chann */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAx; - - return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); } @@ -2582,4 +2576,3 @@ void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); #endif /* __STM32G4xx_LL_DMA_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h index f413d09..7cd04b4 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -246,10 +245,10 @@ extern "C" { #define LL_DMAMUX_REQ_SPI4_TX 0x0000006BU /*!< DMAMUX SPI4 TX request */ #define LL_DMAMUX_REQ_SAI1_A 0x0000006CU /*!< DMAMUX SAI1 A request */ #define LL_DMAMUX_REQ_SAI1_B 0x0000006DU /*!< DMAMUX SAI1 B request */ -#define LL_DMAMUX_REQ_FMAC_WRITE 0x0000006EU /*!< DMAMUX FMAC WRITE request */ -#define LL_DMAMUX_REQ_FMAC_READ 0x0000006FU /*!< DMAMUX FMAC READ request */ -#define LL_DMAMUX_REQ_CORDIC_WRITE 0x00000070U /*!< DMAMUX CORDIC WRITE request*/ -#define LL_DMAMUX_REQ_CORDIC_READ 0x00000071U /*!< DMAMUX CORDIC READ request */ +#define LL_DMAMUX_REQ_FMAC_READ 0x0000006EU /*!< DMAMUX FMAC READ request */ +#define LL_DMAMUX_REQ_FMAC_WRITE 0x0000006FU /*!< DMAMUX FMAC WRITE request */ +#define LL_DMAMUX_REQ_CORDIC_READ 0x00000070U /*!< DMAMUX CORDIC READ request */ +#define LL_DMAMUX_REQ_CORDIC_WRITE 0x00000071U /*!< DMAMUX CORDIC WRITE request*/ #define LL_DMAMUX_REQ_UCPD1_RX 0x00000072U /*!< DMAMUX USBPD1_RX request */ #define LL_DMAMUX_REQ_UCPD1_TX 0x00000073U /*!< DMAMUX USBPD1_TX request */ @@ -274,8 +273,8 @@ extern "C" { #define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX Channel 11 connected to DMA2 Channel 4 */ #define LL_DMAMUX_CHANNEL_12 0x0000000CU /*!< DMAMUX Channel 12 connected to DMA2 Channel 5 */ #define LL_DMAMUX_CHANNEL_13 0x0000000DU /*!< DMAMUX Channel 13 connected to DMA2 Channel 6 */ -#define LL_DMAMUX_CHANNEL_14 0x0000000EU /*!< DMAMUX Channel 13 connected to DMA2 Channel 7 */ -#define LL_DMAMUX_CHANNEL_15 0x0000000FU /*!< DMAMUX Channel 13 connected to DMA2 Channel 8 */ +#define LL_DMAMUX_CHANNEL_14 0x0000000EU /*!< DMAMUX Channel 14 connected to DMA2 Channel 7 */ +#define LL_DMAMUX_CHANNEL_15 0x0000000FU /*!< DMAMUX Channel 15 connected to DMA2 Channel 8 */ /** * @} */ @@ -314,7 +313,7 @@ extern "C" { #define LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel1 Event */ #define LL_DMAMUX_SYNC_DMAMUX_CH2 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from DMAMUX channel2 Event */ #define LL_DMAMUX_SYNC_DMAMUX_CH3 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel3 Event */ -#define LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from LPTIM1 Ouput */ +#define LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from LPTIM1 Output */ /** * @} */ @@ -364,7 +363,7 @@ extern "C" { #define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel1 Event */ #define LL_DMAMUX_REQ_GEN_DMAMUX_CH2 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from DMAMUX channel2 Event */ #define LL_DMAMUX_REQ_GEN_DMAMUX_CH3 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel3 Event */ -#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from LPTIM1 Ouput */ +#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from LPTIM1 Output */ /** * @} */ @@ -436,6 +435,7 @@ extern "C" { * @arg @ref LL_DMAMUX_CHANNEL_14 * @arg @ref LL_DMAMUX_CHANNEL_15 * @param Request This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM * @arg @ref LL_DMAMUX_REQ_GENERATOR0 * @arg @ref LL_DMAMUX_REQ_GENERATOR1 * @arg @ref LL_DMAMUX_REQ_GENERATOR2 @@ -556,15 +556,13 @@ extern "C" { */ __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) { - register uint32_t dma_base_addr = (uint32_t)DMAMUXx; - - MODIFY_REG(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, - DMAMUX_CxCR_DMAREQ_ID, Request); + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); } /** * @brief Get DMAMUX request ID for DMAMUX Channel x. - * @note DMAMUX channel 1 to 7 are mapped to DMA1 channel 1 to 8. + * @note DMAMUX channel 0 to 7 are mapped to DMA1 channel 1 to 8. * DMAMUX channel 8 to 15 are mapped to DMA2 channel 1 to 8. * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID * @param DMAMUXx DMAMUXx Instance @@ -587,6 +585,8 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @arg @ref LL_DMAMUX_CHANNEL_15 * (*) Not on all G4 devices * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 * @arg @ref LL_DMAMUX_REQ_GENERATOR0 * @arg @ref LL_DMAMUX_REQ_GENERATOR1 * @arg @ref LL_DMAMUX_REQ_GENERATOR2 @@ -706,10 +706,8 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uin */ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAMUXx; - - return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel - 1U)))))->CCR, - DMAMUX_CxCR_DMAREQ_ID)); + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID)); } /** @@ -738,10 +736,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, */ __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) { - register uint32_t dma_base_addr = (uint32_t)DMAMUXx; - - MODIFY_REG(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, - DMAMUX_CxCR_NBREQ, RequestNb - 1U); + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos)); } /** @@ -769,10 +765,8 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, */ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAMUXx; - - return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, - DMAMUX_CxCR_NBREQ) + 1U); + (void)(DMAMUXx); + return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U); } /** @@ -805,10 +799,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) { - register uint32_t dma_base_addr = (uint32_t)DMAMUXx; - - MODIFY_REG(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, - DMAMUX_CxCR_SPOL, Polarity); + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity); } /** @@ -840,10 +832,8 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, */ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAMUXx; - - return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, - DMAMUX_CxCR_SPOL)); + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL)); } /** @@ -871,9 +861,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMU */ __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAMUXx; - - SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_EGE); + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); } /** @@ -901,10 +890,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAMUXx; - - CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, - DMAMUX_CxCR_EGE); + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); } /** @@ -932,10 +919,8 @@ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAMUXx; - - return ((READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, - DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL); + (void)(DMAMUXx); + return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE))? 1UL : 0UL); } /** @@ -963,9 +948,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeD */ __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAMUXx; - - SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SE); + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); } /** @@ -993,9 +977,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint3 */ __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAMUXx; - - CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SE); + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); } /** @@ -1023,10 +1006,8 @@ __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAMUXx; - - return ((READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, - DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL); + (void)(DMAMUXx); + return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE))? 1UL : 0UL); } /** @@ -1076,10 +1057,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx */ __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) { - register uint32_t dma_base_addr = (uint32_t)DMAMUXx; - - MODIFY_REG(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, - DMAMUX_CxCR_SYNC_ID, SyncID); + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID); } /** @@ -1128,10 +1107,8 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32 */ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAMUXx; - - return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, - DMAMUX_CxCR_SYNC_ID)); + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID)); } /** @@ -1147,9 +1124,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, ui */ __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - UNUSED(DMAMUXx); - SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * - (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); + (void)(DMAMUXx); + SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); } /** @@ -1165,9 +1141,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, */ __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - UNUSED(DMAMUXx); - CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * - (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); + (void)(DMAMUXx); + CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); } /** @@ -1183,9 +1158,8 @@ __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - UNUSED(DMAMUXx); - return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * - (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL); + (void)(DMAMUXx); + return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE))? 1UL : 0UL); } /** @@ -1890,9 +1864,8 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAMUXx; - - SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE); + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE); } /** @@ -1920,10 +1893,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint */ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAMUXx; - - CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, - DMAMUX_CxCR_SOIE); + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE); } /** @@ -1951,10 +1922,8 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uin */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - register uint32_t dma_base_addr = (uint32_t)DMAMUXx; - - return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, - DMAMUX_CxCR_SOIE)); + (void)(DMAMUXx); + return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE))? 1UL : 0UL); } /** @@ -2035,4 +2004,3 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMU #endif /* __STM32G4xx_LL_DMAMUX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_exti.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_exti.h index 4e390d5..db1d280 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_exti.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_exti.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1173,7 +1172,7 @@ __STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) /** * @brief Generate a software Interrupt Event for Lines in range 32 to 63 - * @note If the interrupt is enabled on this line inthe EXTI_IMR2, writing a 1 to + * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2 * resulting in an interrupt request generation. * This bit is cleared by clearing the corresponding bit in the EXTI_PR2 @@ -1421,4 +1420,3 @@ void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); #endif /* __STM32G4xx_LL_EXTI_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h index f9373ec..faf0e9a 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -952,7 +951,8 @@ __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMas */ __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) { - WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask); + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); } /** @@ -992,4 +992,3 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); #endif /* STM32G4xx_LL_GPIO_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h index caeba4e..a15c7cf 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -433,87 +432,85 @@ __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) #if defined(PWR_CR3_UCPD_STDBY) /** - * @brief Enable (write 1) the USB Type-C and Power Delivery standby mode. - * @note Enable just before entering standby when using UCPD1. - * @rmtoll CR3 UCPD1_STDBY LL_PWR_EnableUSBStandByModePD + * @brief Enable the USB Type-C and Power Delivery memorization in Standby mode. + * @note This function must be called just before entering Standby mode. + * @rmtoll CR3 UCPD_STDBY LL_PWR_EnableUCPDStandbyMode * @retval None */ -__STATIC_INLINE void LL_PWR_EnableUSBStandByModePD(void) +__STATIC_INLINE void LL_PWR_EnableUCPDStandbyMode(void) { SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); } /** - * @brief Disable (write 0) USB Type-C and Power Delivery standby mode. - * @note Disable immediately after standby exit when using UCPD1, - * (and before writing any UCPD1 registers). - * @rmtoll CR3 UCPD1_STDBY LL_PWR_DisableUSBStandByModePD + * @brief Disable the USB Type-C and Power Delivery memorization in Standby mode. + * @note This function must be called after exiting Standby mode and before any + * UCPD configuration update. + * @rmtoll CR3 UCPD_STDBY LL_PWR_DisableUCPDStandbyMode * @retval None */ -__STATIC_INLINE void LL_PWR_DisableUSBStandByModePD(void) +__STATIC_INLINE void LL_PWR_DisableUCPDStandbyMode(void) { CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); } /** - * @brief Check the USB Type-C and Power Delivery standby mode. - * @rmtoll CR3 UCPD1_STDBY LL_PWR_IsEnabledUSBStandByModePD + * @brief Check the USB Type-C and Power Delivery Standby mode memorization state. + * @rmtoll CR3 UCPD_STDBY LL_PWR_IsEnabledUCPDStandbyMode * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBStandByModePD(void) +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDStandbyMode(void) { - return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY) == (PWR_CR3_UCPD_STDBY))?1UL:0UL); + return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY) == (PWR_CR3_UCPD_STDBY)) ? 1UL : 0UL); } #endif /* PWR_CR3_UCPD_STDBY */ #if defined(PWR_CR3_UCPD_DBDIS) /** - * @brief Enable (write 0) USB Type-C dead battery pull-down behavior - * on UCPD1_CC1 and UCPD1_CC2 pins. - * @note After exiting reset, the USB Type-C “dead battery†behavior will be enabled, - * which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it - * in all cases, either to stop this pull-down or to hand over control to the UCPD1 - * (which should therefore be initialized before doing the disable). - * @rmtoll CR3 PWR_CR3_UCPD_DBDIS LL_PWR_EnableUSBDeadBattery + * @brief Enable the USB Type-C and power delivery dead battery pull-down behavior + * on UCPD CC1 and CC2 pins. + * @note After exiting reset, the USB Type-C dead battery behavior is enabled, + * which may have a pull-down effect on CC1 and CC2 pins. It is recommended + * to disable it in all cases, either to stop this pull-down or to hand over + * control to the UCPD (which should therefore be initialized before doing the disable). + * @rmtoll CR3 UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery * @retval None */ -__STATIC_INLINE void LL_PWR_EnableUSBDeadBattery(void) +__STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void) { CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); } /** - * @brief Disable (write 1) USB Type-C dead battery pull-down behavior - * on UCPD1_CC1 and UCPD1_CC2 pins. - * @note After exiting reset, the USB Type-C “dead battery†behavior will be enabled, - * which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it - * in all cases, either to stop this pull-down or to hand over control to the UCPD1 - * (which should therefore be initialized before doing the disable). - * @rmtoll CR3 PWR_CR3_UCPD_DBDIS LL_PWR_DisableUSBDeadBattery + * @brief Disable the USB Type-C and power delivery dead battery pull-down behavior + * on UCPD CC1 and CC2 pins. + * @note After exiting reset, the USB Type-C dead battery behavior is enabled, + * which may have a pull-down effect on CC1 and CC2 pins. It is recommended + * to disable it in all cases, either to stop this pull-down or to hand over + * control to the UCPD (which should therefore be initialized before doing the disable). + * @rmtoll CR3 UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery * @retval None */ -__STATIC_INLINE void LL_PWR_DisableUSBDeadBattery(void) +__STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void) { SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); } /** - * @brief Check USB Type-C dead battery pull-down behavior - * on UCPD1_CC1 and UCPD1_CC2 pins. - * @note After exiting reset, the USB Type-C “dead battery†behavior will be enabled, - * which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it - * in all cases, either to stop this pull-down or to hand over control to the UCPD1 - * (which should therefore be initialized before doing the disable). - * @rmtoll CR3 PWR_CR3_UCPD_DBDIS LL_PWR_IsEnabledUSBDeadBattery - * @retval State of bit. + * @brief Check the USB Type-C and power delivery dead battery pull-down behavior + * on UCPD CC1 and CC2 pins. + * @note After exiting reset, the USB Type-C dead battery behavior is enabled, + * which may have a pull-down effect on CC1 and CC2 pins. It is recommended + * to disable it in all cases, either to stop this pull-down or to hand over + * control to the UCPD (which should therefore be initialized before doing the disable). + * @rmtoll CR3 UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery + * @retval State of feature (1 : enabled; 0 : disabled). */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBDeadBattery(void) +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void) { - - return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS) == (PWR_CR3_UCPD_DBDIS))?1UL:0UL); - + return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS) == (PWR_CR3_UCPD_DBDIS)) ? 0UL : 1UL); } #endif /* PWR_CR3_UCPD_DBDIS */ @@ -598,7 +595,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) * @param PeriphVoltage This parameter can be one of the following values: * @arg @ref LL_PWR_PVM_VDDA_COMP (*) * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*) - * @arg @ref LL_PWR_PVM_VDDA_ADC + * @arg @ref LL_PWR_PVM_VDDA_ADC * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC * * (*) value not defined in all devices @@ -618,7 +615,7 @@ __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage) * @param PeriphVoltage This parameter can be one of the following values: * @arg @ref LL_PWR_PVM_VDDA_COMP (*) * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*) - * @arg @ref LL_PWR_PVM_VDDA_ADC + * @arg @ref LL_PWR_PVM_VDDA_ADC * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC * * (*) value not defined in all devices @@ -638,7 +635,7 @@ __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage) * @param PeriphVoltage This parameter can be one of the following values: * @arg @ref LL_PWR_PVM_VDDA_COMP (*) * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*) - * @arg @ref LL_PWR_PVM_VDDA_ADC + * @arg @ref LL_PWR_PVM_VDDA_ADC * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC * * (*) value not defined in all devices @@ -753,50 +750,6 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void) return ((READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF))?1UL:0UL); } -#if defined (PWR_CR3_UCPD_DBDIS) -/** - * @brief Enable USB Type-C and Power Delivery Dead Battery disable - * @rmtoll CR3 UCPD_DBDIS LL_PWR_EnableDeadBatteryPD - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableDeadBatteryPD(void) -{ - SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); -} - -/** - * @brief Disable USB Type-C and Power Delivery Dead Battery disable - * @rmtoll CR3 UCPD_DBDIS LL_PWR_DisableDeadBatteryPD - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableDeadBatteryPD(void) -{ - CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); -} -#endif /* PWR_CR3_UCPD_DBDIS */ - -#if defined(PWR_CR3_UCPD_STDBY) -/** - * @brief Enable USB Type-C and Power Delivery standby mode. - * @rmtoll CR3 UCPD_STDBY LL_PWR_EnableStandByModePD - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableStandByModePD(void) -{ - SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); -} - -/** - * @brief Disable USB Type-C and Power Delivery standby mode. - * @rmtoll CR3 UCPD_STDBY LL_PWR_DisableStandByModePD - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableStandByModePD(void) -{ - CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); -} -#endif /* PWR_CR3_UCPD_STDBY */ - /** * @brief Enable pull-up and pull-down configuration * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg @@ -1087,7 +1040,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) */ __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) { - SET_BIT(*((uint32_t *)GPIO), GPIONumber); + SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber); } /** @@ -1130,7 +1083,7 @@ __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) */ __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) { - CLEAR_BIT(*((uint32_t *)GPIO), GPIONumber); + CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber); } /** @@ -1173,10 +1126,7 @@ __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) { - uint32_t temp; - temp = READ_BIT(*((uint32_t *)(GPIO)), GPIONumber); - - return ((temp == (GPIONumber))?1U:0U); + return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL); } /** @@ -1219,8 +1169,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIO */ __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { - register uint32_t temp = (uint32_t)(GPIO) + 4U; - SET_BIT(*((uint32_t *)(temp)), GPIONumber); + SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber); } /** @@ -1263,8 +1212,7 @@ __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumbe */ __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { - register uint32_t temp = (uint32_t)(GPIO) + 4U; - CLEAR_BIT(*((uint32_t *)(temp)), GPIONumber); + CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber); } /** @@ -1307,12 +1255,7 @@ __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumb */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { - register uint32_t temp_reg = (uint32_t)(GPIO) + 4U; - uint32_t temp; - temp = READ_BIT(*((uint32_t *)(temp_reg)), GPIONumber); - - return ((temp == (GPIONumber))?1U:0U); - + return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL); } /** @@ -1623,6 +1566,16 @@ ErrorStatus LL_PWR_DeInit(void); /* Old functions name kept for legacy purpose, to be replaced by the */ /* current functions name. */ #define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS +#define LL_PWR_EnableUSBDeadBattery LL_PWR_EnableUCPDDeadBattery +#define LL_PWR_DisableUSBDeadBattery LL_PWR_DisableUCPDDeadBattery +#define LL_PWR_IsEnabledUSBDeadBattery LL_PWR_IsEnabledUCPDDeadBattery +#define LL_PWR_EnableDeadBatteryPD LL_PWR_EnableUCPDDeadBattery +#define LL_PWR_DisableDeadBatteryPD LL_PWR_DisableUCPDDeadBattery +#define LL_PWR_EnableUSBStandByModePD LL_PWR_EnableUCPDStandbyMode +#define LL_PWR_EnableStandByModePD LL_PWR_EnableUCPDStandbyMode +#define LL_PWR_DisableUSBStandByModePD LL_PWR_DisableUCPDStandbyMode +#define LL_PWR_DisableStandByModePD LL_PWR_DisableUCPDStandbyMode +#define LL_PWR_IsEnabledUSBStandByModePD LL_PWR_IsEnabledUCPDStandbyMode /** * @} */ @@ -1647,4 +1600,3 @@ ErrorStatus LL_PWR_DeInit(void); #endif /* STM32G4xx_LL_PWR_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h index 70ed4eb..4c18025 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -2396,6 +2394,16 @@ __STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC(void) CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); } +/** + * @brief Check if PLL output mapped on ADC domain clock is enabled + * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_ADC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_ADC(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL); +} + /** * @brief Enable PLL output mapped on 48MHz domain clock * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M @@ -2420,6 +2428,16 @@ __STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void) CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); } +/** + * @brief Check if PLL output mapped on 48MHz domain clock is enabled + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_48M + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_48M(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL); +} + /** * @brief Enable PLL output mapped on SYSCLK domain * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS @@ -2444,6 +2462,16 @@ __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void) CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN); } +/** + * @brief Check if PLL output mapped on SYSCLK domain clock is enabled + * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_IsEnabledDomain_SYS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN) == (RCC_PLLCFGR_PLLREN)) ? 1UL : 0UL); +} + /** * @} */ @@ -2968,4 +2996,3 @@ uint32_t LL_RCC_GetQUADSPIClockFreq(uint32_t QUADSPIxSource); #endif /* STM32G4xx_LL_RCC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h index 53dbe6e..2a8e877 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h @@ -3,6 +3,17 @@ * @file stm32g4xx_ll_system.h * @author MCD Application Team * @brief Header file of SYSTEM LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -17,17 +28,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -305,7 +305,7 @@ extern "C" { */ #define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREFBUF_OUT = 2.048V) */ #define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREFBUF_OUT = 2.5V) */ -#define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.8V) */ +#define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.9V) */ /** * @} */ @@ -1514,4 +1514,3 @@ __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void) #endif /* __STM32G4xx_LL_SYSTEM_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h deleted file mode 100644 index 0cdea09..0000000 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h +++ /dev/null @@ -1,6658 +0,0 @@ -/** - ****************************************************************************** - * @file stm32g4xx_ll_tim.h - * @author MCD Application Team - * @brief Header file of TIM LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32G4xx_LL_TIM_H -#define __STM32G4xx_LL_TIM_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32g4xx.h" - -/** @addtogroup STM32G4xx_LL_Driver - * @{ - */ - -#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM20) - -/** @defgroup TIM_LL TIM - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup TIM_LL_Private_Variables TIM Private Variables - * @{ - */ -static const uint8_t OFFSET_TAB_CCMRx[] = -{ - 0x00U, /* 0: TIMx_CH1 */ - 0x00U, /* 1: TIMx_CH1N */ - 0x00U, /* 2: TIMx_CH2 */ - 0x00U, /* 3: TIMx_CH2N */ - 0x04U, /* 4: TIMx_CH3 */ - 0x04U, /* 5: TIMx_CH3N */ - 0x04U, /* 6: TIMx_CH4 */ - 0x04U, /* 7: TIMx_CH4N */ - 0x38U, /* 8: TIMx_CH5 */ - 0x38U /* 9: TIMx_CH6 */ - -}; - -static const uint8_t SHIFT_TAB_OCxx[] = -{ - 0U, /* 0: OC1M, OC1FE, OC1PE */ - 0U, /* 1: - NA */ - 8U, /* 2: OC2M, OC2FE, OC2PE */ - 0U, /* 3: - NA */ - 0U, /* 4: OC3M, OC3FE, OC3PE */ - 0U, /* 5: - NA */ - 8U, /* 6: OC4M, OC4FE, OC4PE */ - 0U, /* 7: - NA */ - 0U, /* 8: OC5M, OC5FE, OC5PE */ - 8U /* 9: OC6M, OC6FE, OC6PE */ -}; - -static const uint8_t SHIFT_TAB_ICxx[] = -{ - 0U, /* 0: CC1S, IC1PSC, IC1F */ - 0U, /* 1: - NA */ - 8U, /* 2: CC2S, IC2PSC, IC2F */ - 0U, /* 3: - NA */ - 0U, /* 4: CC3S, IC3PSC, IC3F */ - 0U, /* 5: - NA */ - 8U, /* 6: CC4S, IC4PSC, IC4F */ - 0U, /* 7: - NA */ - 0U, /* 8: - NA */ - 0U /* 9: - NA */ -}; - -static const uint8_t SHIFT_TAB_CCxP[] = -{ - 0U, /* 0: CC1P */ - 2U, /* 1: CC1NP */ - 4U, /* 2: CC2P */ - 6U, /* 3: CC2NP */ - 8U, /* 4: CC3P */ - 10U, /* 5: CC3NP */ - 12U, /* 6: CC4P */ - 14U, /* 7: CC4NP */ - 16U, /* 8: CC5P */ - 20U /* 9: CC6P */ -}; - -static const uint8_t SHIFT_TAB_OISx[] = -{ - 0U, /* 0: OIS1 */ - 1U, /* 1: OIS1N */ - 2U, /* 2: OIS2 */ - 3U, /* 3: OIS2N */ - 4U, /* 4: OIS3 */ - 5U, /* 5: OIS3N */ - 6U, /* 6: OIS4 */ - 7U, /* 7: OIS4N */ - 8U, /* 8: OIS5 */ - 10U /* 9: OIS6 */ -}; -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup TIM_LL_Private_Constants TIM Private Constants - * @{ - */ - -/* Defines used for the bit position in the register and perform offsets */ -#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL) - -/* Generic bit definitions for TIMx_AF1 register */ -#define TIMx_AF1_BKINE TIM1_AF1_BKINE /*!< BRK BKIN input enable */ -#define TIMx_AF1_BKCOMP1E TIM1_AF1_BKCMP1E /*!< BRK COMP1 enable */ -#define TIMx_AF1_BKCOMP2E TIM1_AF1_BKCMP2E /*!< BRK COMP2 enable */ -#define TIMx_AF1_BKCOMP3E TIM1_AF1_BKCMP3E /*!< BRK COMP3 enable */ -#define TIMx_AF1_BKCOMP4E TIM1_AF1_BKCMP4E /*!< BRK COMP4 enable */ -#if defined(COMP5) -#define TIMx_AF1_BKCOMP5E TIM1_AF1_BKCMP5E /*!< BRK COMP5 enable */ -#endif /* COMP5 */ -#if defined(COMP6) -#define TIMx_AF1_BKCOMP6E TIM1_AF1_BKCMP6E /*!< BRK COMP6 enable */ -#endif /* COMP6 */ -#if defined(COMP7) -#define TIMx_AF1_BKCOMP7E TIM1_AF1_BKCMP7E /*!< BRK COMP7 enable */ -#endif /* COMP7 */ -#define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */ -#define TIMx_AF1_BKCOMP1P TIM1_AF1_BKCMP1P /*!< BRK COMP1 input polarity */ -#define TIMx_AF1_BKCOMP2P TIM1_AF1_BKCMP2P /*!< BRK COMP2 input polarity */ -#define TIMx_AF1_BKCOMP3P TIM1_AF1_BKCMP3P /*!< BRK COMP3 input polarity */ -#define TIMx_AF1_BKCOMP4P TIM1_AF1_BKCMP4P /*!< BRK COMP4 input polarity */ -#define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */ - -/* Generic bit definitions for TIMx_AF2 register */ -#define TIMx_AF2_BK2INE TIM1_AF2_BK2INE /*!< BRK2 BKIN2 input enable */ -#define TIMx_AF2_BK2COMP1E TIM1_AF2_BK2CMP1E /*!< BRK2 COMP1 enable */ -#define TIMx_AF2_BK2COMP2E TIM1_AF2_BK2CMP2E /*!< BRK2 COMP2 enable */ -#define TIMx_AF2_BK2COMP3E TIM1_AF2_BK2CMP3E /*!< BRK2 COMP3 enable */ -#define TIMx_AF2_BK2COMP4E TIM1_AF2_BK2CMP4E /*!< BRK2 COMP4 enable */ -#if defined(COMP5) -#define TIMx_AF2_BK2COMP5E TIM1_AF2_BK2CMP5E /*!< BRK2 COMP5 enable */ -#endif /* COMP5 */ -#if defined(COMP6) -#define TIMx_AF2_BK2COMP6E TIM1_AF2_BK2CMP6E /*!< BRK2 COMP6 enable */ -#endif /* COMP6 */ -#if defined(COMP7) -#define TIMx_AF2_BK2COMP7E TIM1_AF2_BK2CMP7E /*!< BRK2 COMP7 enable */ -#endif /* COMP7 */ -#define TIMx_AF2_BK2INP TIM1_AF2_BK2INP /*!< BRK2 BKIN2 input polarity */ -#define TIMx_AF2_BK2COMP1P TIM1_AF2_BK2CMP1P /*!< BRK2 COMP1 input polarity */ -#define TIMx_AF2_BK2COMP2P TIM1_AF2_BK2CMP2P /*!< BRK2 COMP2 input polarity */ -#define TIMx_AF2_BK2COMP3P TIM1_AF2_BK2CMP3P /*!< BRK2 COMP3 input polarity */ -#define TIMx_AF2_BK2COMP4P TIM1_AF2_BK2CMP4P /*!< BRK2 COMP4 input polarity */ - - -/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ -#define DT_DELAY_1 ((uint8_t)0x7F) -#define DT_DELAY_2 ((uint8_t)0x3F) -#define DT_DELAY_3 ((uint8_t)0x1F) -#define DT_DELAY_4 ((uint8_t)0x1F) - -/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ -#define DT_RANGE_1 ((uint8_t)0x00) -#define DT_RANGE_2 ((uint8_t)0x80) -#define DT_RANGE_3 ((uint8_t)0xC0) -#define DT_RANGE_4 ((uint8_t)0xE0) - -/** Legacy definitions for compatibility purpose -@cond 0 - */ -/** -@endcond - */ - -#define OCREF_CLEAR_SELECT_Pos (28U) -#define OCREF_CLEAR_SELECT_Msk (0x1U << OCREF_CLEAR_SELECT_Pos) /*!< 0x10000000 */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup TIM_LL_Private_Macros TIM Private Macros - * @{ - */ -/** @brief Convert channel id into channel index. - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH4N - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval none - */ -#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ - (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ - ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ - ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ - ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ - ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ - ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ - ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ - ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\ - ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U) - -/** @brief Calculate the deadtime sampling period(in ps). - * @param __TIMCLK__ timer input clock frequency (in Hz). - * @param __CKD__ This parameter can be one of the following values: - * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 - * @retval none - */ -#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ - (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ - ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ - ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) -/** - * @} - */ - - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure - * @{ - */ - -/** - * @brief TIM Time Base configuration structure definition. - */ -typedef struct -{ - uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - - This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/ - - uint32_t CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. - - This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/ - - uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF. - - This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/ - - uint32_t ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. - - This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ - - uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. - - This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ -} LL_TIM_InitTypeDef; - -/** - * @brief TIM Output Compare configuration structure definition. - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the output mode. - This parameter can be a value of @ref TIM_LL_EC_OCMODE. - - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/ - - uint32_t OCState; /*!< Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_LL_EC_OCSTATE. - - This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ - - uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. - This parameter can be a value of @ref TIM_LL_EC_OCSTATE. - - This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ - - uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - - This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. - - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ - - uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. - - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ - - - uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. - - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ - - uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. - - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ -} LL_TIM_OC_InitTypeDef; - -/** - * @brief TIM Input Capture configuration structure definition. - */ - -typedef struct -{ - - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ - - uint32_t ICActiveInput; /*!< Specifies the input. - This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ - - uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_LL_EC_ICPSC. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ -} LL_TIM_IC_InitTypeDef; - - -/** - * @brief TIM Encoder interface configuration structure definition. - */ -typedef struct -{ - uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). - This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. - - This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/ - - uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. - This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ - - uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source - This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ - - uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. - This parameter can be a value of @ref TIM_LL_EC_ICPSC. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ - - uint32_t IC1Filter; /*!< Specifies the TI1 input filter. - This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ - - uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. - This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ - - uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source - This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ - - uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. - This parameter can be a value of @ref TIM_LL_EC_ICPSC. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ - - uint32_t IC2Filter; /*!< Specifies the TI2 input filter. - This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ - -} LL_TIM_ENCODER_InitTypeDef; - -/** - * @brief TIM Hall sensor interface configuration structure definition. - */ -typedef struct -{ - - uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. - This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ - - uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. - Prescaler must be set to get a maximum counter period longer than the - time interval between 2 consecutive changes on the Hall inputs. - This parameter can be a value of @ref TIM_LL_EC_ICPSC. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ - - uint32_t IC1Filter; /*!< Specifies the TI1 input filter. - This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ - - uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. - A positive pulse (TRGO event) is generated with a programmable delay every time - a change occurs on the Hall inputs. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. - - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/ -} LL_TIM_HALLSENSOR_InitTypeDef; - -/** - * @brief BDTR (Break and Dead Time) structure definition - */ -typedef struct -{ - uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. - This parameter can be a value of @ref TIM_LL_EC_OSSR - - This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() - - @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ - - uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. - This parameter can be a value of @ref TIM_LL_EC_OSSI - - This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() - - @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ - - uint32_t LockLevel; /*!< Specifies the LOCK level parameters. - This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL - - @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register - has been written, their content is frozen until the next reset.*/ - - uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the - switching-on of the outputs. - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. - - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime() - - @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */ - - uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. - This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE - - This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() - - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ - - uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. - This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY - - This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() - - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ - - uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. - This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER - - This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() - - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ - - uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input. - This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE - - This feature can be modified afterwards using unitary functions @ref LL_TIM_ConfigBRK() - - @note Bidirectional break input is only supported by advanced timers instances. - - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ - - uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. - This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE - - This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() - - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ - - uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. - This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY - - This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() - - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ - - uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. - This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER - - This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() - - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ - - uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input. - This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE - - This feature can be modified afterwards using unitary functions @ref LL_TIM_ConfigBRK2() - - @note Bidirectional break input is only supported by advanced timers instances. - - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ - - uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. - This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE - - This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() - - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ -} LL_TIM_BDTR_InitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants - * @{ - */ - -/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_TIM_ReadReg function. - * @{ - */ -#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ -#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ -#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ -#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ -#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ -#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */ -#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */ -#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ -#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ -#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ -#define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */ -#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ -#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ -#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ -#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ -#define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */ -#define LL_TIM_SR_IDXF TIM_SR_IDXF /*!< Index interrupt flag */ -#define LL_TIM_SR_DIRF TIM_SR_DIRF /*!< Direction Change interrupt flag */ -#define LL_TIM_SR_IERRF TIM_SR_IERRF /*!< Index Error flag */ -#define LL_TIM_SR_TERRF TIM_SR_TERRF /*!< Transition Error flag */ -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable - * @{ - */ -#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ -#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ -/** - * @} - */ - -/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable - * @{ - */ -#define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ -#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ -/** - * @} - */ - -/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable - * @{ - */ -#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ -#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** @defgroup TIM_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. - * @{ - */ -#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ -#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ -#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ -#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ -#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ -#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ -#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ -#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ -#define LL_TIM_DIER_IDXIE TIM_DIER_IDXIE /*!< Index interrupt enable */ -#define LL_TIM_DIER_DIRIE TIM_DIER_DIRIE /*!< Direction Change interrupt enable */ -#define LL_TIM_DIER_IERRIE TIM_DIER_IERRIE /*!< Index Error interrupt enable */ -#define LL_TIM_DIER_TERRIE TIM_DIER_TERRIE /*!< Transition Error interrupt enable */ -/** - * @} - */ - -/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source - * @{ - */ -#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ -#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ -/** - * @} - */ - -/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode - * @{ - */ -#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ -#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */ -/** - * @} - */ - -/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode - * @{ - */ -#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!TIMx_CCRy else active.*/ -#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/ -#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!__REG__, (__VALUE__)) - -/** - * @brief Read a value in TIM register. - * @param __INSTANCE__ TIM Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) -/** - * @} - */ - -/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros - * @{ - */ - -/** - * @brief HELPER macro retrieving the UIFCPY flag from the counter value. - * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); - * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied - * to TIMx_CNT register bit 31) - * @param __CNT__ Counter value - * @retval UIF status bit - */ -#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ - (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) - -/** - * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. - * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __CKD__ This parameter can be one of the following values: - * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 - * @param __DT__ deadtime duration (in ns) - * @retval DTG[0:7] - */ -#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ - ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ - (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ - (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ - (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ - 0U) - -/** - * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. - * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __CNTCLK__ counter clock frequency (in Hz) - * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) - */ -#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ - (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U) - -/** - * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. - * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __PSC__ prescaler - * @param __FREQ__ output signal frequency (in Hz) - * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) - */ -#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ - ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) - -/** - * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required output signal frequency. - * @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10000); - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __PSC__ prescaler - * @param __FREQ__ output signal frequency (in Hz) - * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) - */ -#define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \ - ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (uint32_t)((((uint64_t)(__TIMCLK__) * 16U/((__FREQ__) * ((__PSC__) + 1U))) - 16U)) : 0U) - -/** - * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. - * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __PSC__ prescaler - * @param __DELAY__ timer output compare active/inactive delay (in us) - * @retval Compare value (between Min_Data=0 and Max_Data=65535) - */ -#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ - ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ - / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) - -/** - * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer output compare active/inactive delay. - * @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10); - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __PSC__ prescaler - * @param __DELAY__ timer output compare active/inactive delay (in us) - * @retval Compare value (between Min_Data=0 and Max_Data=65535) - */ -#define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__) \ - ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \ - / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) - -/** - * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). - * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __PSC__ prescaler - * @param __DELAY__ timer output compare active/inactive delay (in us) - * @param __PULSE__ pulse duration (in us) - * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) - */ -#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ - ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ - + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) - -/** - * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required pulse duration (when the timer operates in one pulse mode). - * @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __PSC__ prescaler - * @param __DELAY__ timer output compare active/inactive delay (in us) - * @param __PULSE__ pulse duration (in us) - * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) - */ -#define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ - ((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \ - + __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__DELAY__)))) - -/** - * @brief HELPER macro retrieving the ratio of the input capture prescaler - * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); - * @param __ICPSC__ This parameter can be one of the following values: - * @arg @ref LL_TIM_ICPSC_DIV1 - * @arg @ref LL_TIM_ICPSC_DIV2 - * @arg @ref LL_TIM_ICPSC_DIV4 - * @arg @ref LL_TIM_ICPSC_DIV8 - * @retval Input capture prescaler ratio (1, 2, 4 or 8) - */ -#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ - ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) - - -/** - * @} - */ - - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions - * @{ - */ - -/** @defgroup TIM_LL_EF_Time_Base Time Base configuration - * @{ - */ -/** - * @brief Enable timer counter. - * @rmtoll CR1 CEN LL_TIM_EnableCounter - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->CR1, TIM_CR1_CEN); -} - -/** - * @brief Disable timer counter. - * @rmtoll CR1 CEN LL_TIM_DisableCounter - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); -} - -/** - * @brief Indicates whether the timer counter is enabled. - * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); -} - -/** - * @brief Enable update event generation. - * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); -} - -/** - * @brief Disable update event generation. - * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->CR1, TIM_CR1_UDIS); -} - -/** - * @brief Indicates whether update event generation is enabled. - * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent - * @param TIMx Timer instance - * @retval Inverted state of bit (0 or 1). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); -} - -/** - * @brief Set update event source - * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events - * generate an update interrupt or DMA request if enabled: - * - Counter overflow/underflow - * - Setting the UG bit - * - Update generation through the slave mode controller - * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter - * overflow/underflow generates an update interrupt or DMA request if enabled. - * @rmtoll CR1 URS LL_TIM_SetUpdateSource - * @param TIMx Timer instance - * @param UpdateSource This parameter can be one of the following values: - * @arg @ref LL_TIM_UPDATESOURCE_REGULAR - * @arg @ref LL_TIM_UPDATESOURCE_COUNTER - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) -{ - MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); -} - -/** - * @brief Get actual event update source - * @rmtoll CR1 URS LL_TIM_GetUpdateSource - * @param TIMx Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_UPDATESOURCE_REGULAR - * @arg @ref LL_TIM_UPDATESOURCE_COUNTER - */ -__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); -} - -/** - * @brief Set one pulse mode (one shot v.s. repetitive). - * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode - * @param TIMx Timer instance - * @param OnePulseMode This parameter can be one of the following values: - * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE - * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) -{ - MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); -} - -/** - * @brief Get actual one pulse mode. - * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode - * @param TIMx Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE - * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE - */ -__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); -} - -/** - * @brief Set the timer counter counting mode. - * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to - * check whether or not the counter mode selection feature is supported - * by a timer instance. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n - * CR1 CMS LL_TIM_SetCounterMode - * @param TIMx Timer instance - * @param CounterMode This parameter can be one of the following values: - * @arg @ref LL_TIM_COUNTERMODE_UP - * @arg @ref LL_TIM_COUNTERMODE_DOWN - * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP - * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN - * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) -{ - MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); -} - -/** - * @brief Get actual counter mode. - * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to - * check whether or not the counter mode selection feature is supported - * by a timer instance. - * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n - * CR1 CMS LL_TIM_GetCounterMode - * @param TIMx Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_COUNTERMODE_UP - * @arg @ref LL_TIM_COUNTERMODE_DOWN - * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP - * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN - * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN - */ -__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS)); -} - -/** - * @brief Enable auto-reload (ARR) preload. - * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->CR1, TIM_CR1_ARPE); -} - -/** - * @brief Disable auto-reload (ARR) preload. - * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); -} - -/** - * @brief Indicates whether auto-reload (ARR) preload is enabled. - * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); -} - -/** - * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. - * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check - * whether or not the clock division feature is supported by the timer - * instance. - * @rmtoll CR1 CKD LL_TIM_SetClockDivision - * @param TIMx Timer instance - * @param ClockDivision This parameter can be one of the following values: - * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) -{ - MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); -} - -/** - * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. - * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check - * whether or not the clock division feature is supported by the timer - * instance. - * @rmtoll CR1 CKD LL_TIM_GetClockDivision - * @param TIMx Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 - */ -__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); -} - -/** - * @brief Set the counter value. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note If dithering is activated, pay attention to the Counter value interpretation - * @rmtoll CNT CNT LL_TIM_SetCounter - * @param TIMx Timer instance - * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) -{ - WRITE_REG(TIMx->CNT, Counter); -} - -/** - * @brief Get the counter value. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note If dithering is activated, pay attention to the Counter value interpretation - * @rmtoll CNT CNT LL_TIM_GetCounter - * @param TIMx Timer instance - * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) - */ -__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CNT)); -} - -/** - * @brief Get the current direction of the counter - * @rmtoll CR1 DIR LL_TIM_GetDirection - * @param TIMx Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_COUNTERDIRECTION_UP - * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN - */ -__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); -} - -/** - * @brief Set the prescaler value. - * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). - * @note The prescaler can be changed on the fly as this control register is buffered. The new - * prescaler ratio is taken into account at the next update event. - * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter - * @rmtoll PSC PSC LL_TIM_SetPrescaler - * @param TIMx Timer instance - * @param Prescaler between Min_Data=0 and Max_Data=65535 - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) -{ - WRITE_REG(TIMx->PSC, Prescaler); -} - -/** - * @brief Get the prescaler value. - * @rmtoll PSC PSC LL_TIM_GetPrescaler - * @param TIMx Timer instance - * @retval Prescaler value between Min_Data=0 and Max_Data=65535 - */ -__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->PSC)); -} - -/** - * @brief Set the auto-reload value. - * @note The counter is blocked while the auto-reload value is null. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter - * In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload parameter. - * @rmtoll ARR ARR LL_TIM_SetAutoReload - * @param TIMx Timer instance - * @param AutoReload between Min_Data=0 and Max_Data=65535 - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) -{ - WRITE_REG(TIMx->ARR, AutoReload); -} - -/** - * @brief Get the auto-reload value. - * @rmtoll ARR ARR LL_TIM_GetAutoReload - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note If dithering is activated, pay attention to the returned value interpretation - * @param TIMx Timer instance - * @retval Auto-reload value - */ -__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->ARR)); -} - -/** - * @brief Set the repetition counter value. - * @note For advanced timer instances RepetitionCounter can be up to 65535. - * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a repetition counter. - * @rmtoll RCR REP LL_TIM_SetRepetitionCounter - * @param TIMx Timer instance - * @param RepetitionCounter between Min_Data=0 and Max_Data=255 - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) -{ - WRITE_REG(TIMx->RCR, RepetitionCounter); -} - -/** - * @brief Get the repetition counter value. - * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a repetition counter. - * @rmtoll RCR REP LL_TIM_GetRepetitionCounter - * @param TIMx Timer instance - * @retval Repetition counter value - */ -__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->RCR)); -} - -/** - * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). - * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. - * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); -} - -/** - * @brief Disable update interrupt flag (UIF) remapping. - * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); -} - -/** - * @brief Enable dithering. - * @note Macro @ref IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides dithering. - * @rmtoll CR1 DITHEN LL_TIM_EnableDithering - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->CR1, TIM_CR1_DITHEN); -} - -/** - * @brief Disable dithering. - * @note Macro @ref IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides dithering. - * @rmtoll CR1 DITHEN LL_TIM_DisableDithering - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN); -} - -/** - * @brief Indicates whether dithering is activated. - * @note Macro @ref IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides dithering. - * @rmtoll CR1 DITHEN LL_TIM_IsEnabledDithering - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration - * @{ - */ -/** - * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. - * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, - * they are updated only when a commutation event (COM) occurs. - * @note Only on channels that have a complementary output. - * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check - * whether or not a timer instance is able to generate a commutation event. - * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->CR2, TIM_CR2_CCPC); -} - -/** - * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. - * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check - * whether or not a timer instance is able to generate a commutation event. - * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); -} - -/** - * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). - * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check - * whether or not a timer instance is able to generate a commutation event. - * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate - * @param TIMx Timer instance - * @param CCUpdateSource This parameter can be one of the following values: - * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY - * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI - * @retval None - */ -__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) -{ - MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); -} - -/** - * @brief Set the trigger of the capture/compare DMA request. - * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger - * @param TIMx Timer instance - * @param DMAReqTrigger This parameter can be one of the following values: - * @arg @ref LL_TIM_CCDMAREQUEST_CC - * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE - * @retval None - */ -__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) -{ - MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); -} - -/** - * @brief Get actual trigger of the capture/compare DMA request. - * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger - * @param TIMx Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_CCDMAREQUEST_CC - * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE - */ -__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); -} - -/** - * @brief Set the lock level to freeze the - * configuration of several capture/compare parameters. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * the lock mechanism is supported by a timer instance. - * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel - * @param TIMx Timer instance - * @param LockLevel This parameter can be one of the following values: - * @arg @ref LL_TIM_LOCKLEVEL_OFF - * @arg @ref LL_TIM_LOCKLEVEL_1 - * @arg @ref LL_TIM_LOCKLEVEL_2 - * @arg @ref LL_TIM_LOCKLEVEL_3 - * @retval None - */ -__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) -{ - MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); -} - -/** - * @brief Enable capture/compare channels. - * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n - * CCER CC1NE LL_TIM_CC_EnableChannel\n - * CCER CC2E LL_TIM_CC_EnableChannel\n - * CCER CC2NE LL_TIM_CC_EnableChannel\n - * CCER CC3E LL_TIM_CC_EnableChannel\n - * CCER CC3NE LL_TIM_CC_EnableChannel\n - * CCER CC4E LL_TIM_CC_EnableChannel\n - * CCER CC4NE LL_TIM_CC_EnableChannel\n - * CCER CC5E LL_TIM_CC_EnableChannel\n - * CCER CC6E LL_TIM_CC_EnableChannel - * @param TIMx Timer instance - * @param Channels This parameter can be a combination of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH4N - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval None - */ -__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) -{ - SET_BIT(TIMx->CCER, Channels); -} - -/** - * @brief Disable capture/compare channels. - * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n - * CCER CC1NE LL_TIM_CC_DisableChannel\n - * CCER CC2E LL_TIM_CC_DisableChannel\n - * CCER CC2NE LL_TIM_CC_DisableChannel\n - * CCER CC3E LL_TIM_CC_DisableChannel\n - * CCER CC3NE LL_TIM_CC_DisableChannel\n - * CCER CC4E LL_TIM_CC_DisableChannel\n - * CCER CC4NE LL_TIM_CC_DisableChannel\n - * CCER CC5E LL_TIM_CC_DisableChannel\n - * CCER CC6E LL_TIM_CC_DisableChannel - * @param TIMx Timer instance - * @param Channels This parameter can be a combination of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH4N - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval None - */ -__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) -{ - CLEAR_BIT(TIMx->CCER, Channels); -} - -/** - * @brief Indicate whether channel(s) is(are) enabled. - * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n - * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n - * CCER CC2E LL_TIM_CC_IsEnabledChannel\n - * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n - * CCER CC3E LL_TIM_CC_IsEnabledChannel\n - * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n - * CCER CC4E LL_TIM_CC_IsEnabledChannel\n - * CCER CC4NE LL_TIM_CC_IsEnabledChannel\n - * CCER CC5E LL_TIM_CC_IsEnabledChannel\n - * CCER CC6E LL_TIM_CC_IsEnabledChannel - * @param TIMx Timer instance - * @param Channels This parameter can be a combination of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH4N - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) -{ - return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration - * @{ - */ -/** - * @brief Configure an output channel. - * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n - * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n - * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n - * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n - * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n - * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n - * CCER CC1P LL_TIM_OC_ConfigOutput\n - * CCER CC2P LL_TIM_OC_ConfigOutput\n - * CCER CC3P LL_TIM_OC_ConfigOutput\n - * CCER CC4P LL_TIM_OC_ConfigOutput\n - * CCER CC5P LL_TIM_OC_ConfigOutput\n - * CCER CC6P LL_TIM_OC_ConfigOutput\n - * CR2 OIS1 LL_TIM_OC_ConfigOutput\n - * CR2 OIS2 LL_TIM_OC_ConfigOutput\n - * CR2 OIS3 LL_TIM_OC_ConfigOutput\n - * CR2 OIS4 LL_TIM_OC_ConfigOutput\n - * CR2 OIS5 LL_TIM_OC_ConfigOutput\n - * CR2 OIS6 LL_TIM_OC_ConfigOutput - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @param Configuration This parameter must be a combination of all the following values: - * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW - * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); - MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), - (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); - MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), - (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); -} - -/** - * @brief Define the behavior of the output reference signal OCxREF from which - * OCx and OCxN (when relevant) are derived. - * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n - * CCMR1 OC2M LL_TIM_OC_SetMode\n - * CCMR2 OC3M LL_TIM_OC_SetMode\n - * CCMR2 OC4M LL_TIM_OC_SetMode\n - * CCMR3 OC5M LL_TIM_OC_SetMode\n - * CCMR3 OC6M LL_TIM_OC_SetMode - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_TIM_OCMODE_FROZEN - * @arg @ref LL_TIM_OCMODE_ACTIVE - * @arg @ref LL_TIM_OCMODE_INACTIVE - * @arg @ref LL_TIM_OCMODE_TOGGLE - * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE - * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE - * @arg @ref LL_TIM_OCMODE_PWM1 - * @arg @ref LL_TIM_OCMODE_PWM2 - * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 - * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 - * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 - * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 - * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only) - * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only) - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); -} - -/** - * @brief Get the output compare mode of an output channel. - * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n - * CCMR1 OC2M LL_TIM_OC_GetMode\n - * CCMR2 OC3M LL_TIM_OC_GetMode\n - * CCMR2 OC4M LL_TIM_OC_GetMode\n - * CCMR3 OC5M LL_TIM_OC_GetMode\n - * CCMR3 OC6M LL_TIM_OC_GetMode - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_OCMODE_FROZEN - * @arg @ref LL_TIM_OCMODE_ACTIVE - * @arg @ref LL_TIM_OCMODE_INACTIVE - * @arg @ref LL_TIM_OCMODE_TOGGLE - * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE - * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE - * @arg @ref LL_TIM_OCMODE_PWM1 - * @arg @ref LL_TIM_OCMODE_PWM2 - * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 - * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 - * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 - * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 - * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only) - * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only) - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); -} - -/** - * @brief Set the polarity of an output channel. - * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n - * CCER CC1NP LL_TIM_OC_SetPolarity\n - * CCER CC2P LL_TIM_OC_SetPolarity\n - * CCER CC2NP LL_TIM_OC_SetPolarity\n - * CCER CC3P LL_TIM_OC_SetPolarity\n - * CCER CC3NP LL_TIM_OC_SetPolarity\n - * CCER CC4P LL_TIM_OC_SetPolarity\n - * CCER CC4NP LL_TIM_OC_SetPolarity\n - * CCER CC5P LL_TIM_OC_SetPolarity\n - * CCER CC6P LL_TIM_OC_SetPolarity - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH4N - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_TIM_OCPOLARITY_HIGH - * @arg @ref LL_TIM_OCPOLARITY_LOW - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); -} - -/** - * @brief Get the polarity of an output channel. - * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n - * CCER CC1NP LL_TIM_OC_GetPolarity\n - * CCER CC2P LL_TIM_OC_GetPolarity\n - * CCER CC2NP LL_TIM_OC_GetPolarity\n - * CCER CC3P LL_TIM_OC_GetPolarity\n - * CCER CC3NP LL_TIM_OC_GetPolarity\n - * CCER CC4P LL_TIM_OC_GetPolarity\n - * CCER CC4NP LL_TIM_OC_GetPolarity\n - * CCER CC5P LL_TIM_OC_GetPolarity\n - * CCER CC6P LL_TIM_OC_GetPolarity - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH4N - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_OCPOLARITY_HIGH - * @arg @ref LL_TIM_OCPOLARITY_LOW - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); -} - -/** - * @brief Set the IDLE state of an output channel - * @note This function is significant only for the timer instances - * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) - * can be used to check whether or not a timer instance provides - * a break input. - * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n - * CR2 OIS2N LL_TIM_OC_SetIdleState\n - * CR2 OIS2 LL_TIM_OC_SetIdleState\n - * CR2 OIS2N LL_TIM_OC_SetIdleState\n - * CR2 OIS3 LL_TIM_OC_SetIdleState\n - * CR2 OIS3N LL_TIM_OC_SetIdleState\n - * CR2 OIS4 LL_TIM_OC_SetIdleState\n - * CR2 OIS4N LL_TIM_OC_SetIdleState\n - * CR2 OIS5 LL_TIM_OC_SetIdleState\n - * CR2 OIS6 LL_TIM_OC_SetIdleState - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH4N - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @param IdleState This parameter can be one of the following values: - * @arg @ref LL_TIM_OCIDLESTATE_LOW - * @arg @ref LL_TIM_OCIDLESTATE_HIGH - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); -} - -/** - * @brief Get the IDLE state of an output channel - * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n - * CR2 OIS2N LL_TIM_OC_GetIdleState\n - * CR2 OIS2 LL_TIM_OC_GetIdleState\n - * CR2 OIS2N LL_TIM_OC_GetIdleState\n - * CR2 OIS3 LL_TIM_OC_GetIdleState\n - * CR2 OIS3N LL_TIM_OC_GetIdleState\n - * CR2 OIS4 LL_TIM_OC_GetIdleState\n - * CR2 OIS4N LL_TIM_OC_GetIdleState\n - * CR2 OIS5 LL_TIM_OC_GetIdleState\n - * CR2 OIS6 LL_TIM_OC_GetIdleState - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH4N - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_OCIDLESTATE_LOW - * @arg @ref LL_TIM_OCIDLESTATE_HIGH - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); -} - -/** - * @brief Enable fast mode for the output channel. - * @note Acts only if the channel is configured in PWM1 or PWM2 mode. - * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n - * CCMR1 OC2FE LL_TIM_OC_EnableFast\n - * CCMR2 OC3FE LL_TIM_OC_EnableFast\n - * CCMR2 OC4FE LL_TIM_OC_EnableFast\n - * CCMR3 OC5FE LL_TIM_OC_EnableFast\n - * CCMR3 OC6FE LL_TIM_OC_EnableFast - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); - -} - -/** - * @brief Disable fast mode for the output channel. - * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n - * CCMR1 OC2FE LL_TIM_OC_DisableFast\n - * CCMR2 OC3FE LL_TIM_OC_DisableFast\n - * CCMR2 OC4FE LL_TIM_OC_DisableFast\n - * CCMR3 OC5FE LL_TIM_OC_DisableFast\n - * CCMR3 OC6FE LL_TIM_OC_DisableFast - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); - -} - -/** - * @brief Indicates whether fast mode is enabled for the output channel. - * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n - * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n - * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n - * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n - * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n - * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; - return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); -} - -/** - * @brief Enable compare register (TIMx_CCRx) preload for the output channel. - * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n - * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n - * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n - * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n - * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n - * CCMR3 OC6PE LL_TIM_OC_EnablePreload - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); -} - -/** - * @brief Disable compare register (TIMx_CCRx) preload for the output channel. - * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n - * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n - * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n - * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n - * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n - * CCMR3 OC6PE LL_TIM_OC_DisablePreload - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); -} - -/** - * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. - * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n - * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n - * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n - * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n - * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n - * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; - return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); -} - -/** - * @brief Enable clearing the output channel on an external event. - * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. - * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether - * or not a timer instance can clear the OCxREF signal on an external event. - * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n - * CCMR1 OC2CE LL_TIM_OC_EnableClear\n - * CCMR2 OC3CE LL_TIM_OC_EnableClear\n - * CCMR2 OC4CE LL_TIM_OC_EnableClear\n - * CCMR3 OC5CE LL_TIM_OC_EnableClear\n - * CCMR3 OC6CE LL_TIM_OC_EnableClear - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); -} - -/** - * @brief Disable clearing the output channel on an external event. - * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether - * or not a timer instance can clear the OCxREF signal on an external event. - * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n - * CCMR1 OC2CE LL_TIM_OC_DisableClear\n - * CCMR2 OC3CE LL_TIM_OC_DisableClear\n - * CCMR2 OC4CE LL_TIM_OC_DisableClear\n - * CCMR3 OC5CE LL_TIM_OC_DisableClear\n - * CCMR3 OC6CE LL_TIM_OC_DisableClear - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); -} - -/** - * @brief Indicates clearing the output channel on an external event is enabled for the output channel. - * @note This function enables clearing the output channel on an external event. - * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. - * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether - * or not a timer instance can clear the OCxREF signal on an external event. - * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n - * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n - * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n - * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n - * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n - * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; - return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); -} - -/** - * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals). - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * dead-time insertion feature is supported by a timer instance. - * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter - * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime - * @param TIMx Timer instance - * @param DeadTime between Min_Data=0 and Max_Data=255 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) -{ - MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); -} - -/** - * @brief Set compare value for output channel 1 (TIMx_CCR1). - * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not - * output channel 1 is supported by a timer instance. - * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . - * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 - * @param TIMx Timer instance - * @param CompareValue between Min_Data=0 and Max_Data=65535 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) -{ - WRITE_REG(TIMx->CCR1, CompareValue); -} - -/** - * @brief Set compare value for output channel 2 (TIMx_CCR2). - * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not - * output channel 2 is supported by a timer instance. - * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . - * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 - * @param TIMx Timer instance - * @param CompareValue between Min_Data=0 and Max_Data=65535 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) -{ - WRITE_REG(TIMx->CCR2, CompareValue); -} - -/** - * @brief Set compare value for output channel 3 (TIMx_CCR3). - * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not - * output channel is supported by a timer instance. - * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . - * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 - * @param TIMx Timer instance - * @param CompareValue between Min_Data=0 and Max_Data=65535 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) -{ - WRITE_REG(TIMx->CCR3, CompareValue); -} - -/** - * @brief Set compare value for output channel 4 (TIMx_CCR4). - * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not - * output channel 4 is supported by a timer instance. - * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . - * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 - * @param TIMx Timer instance - * @param CompareValue between Min_Data=0 and Max_Data=65535 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) -{ - WRITE_REG(TIMx->CCR4, CompareValue); -} - -/** - * @brief Set compare value for output channel 5 (TIMx_CCR5). - * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not - * output channel 5 is supported by a timer instance. - * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . - * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 - * @param TIMx Timer instance - * @param CompareValue between Min_Data=0 and Max_Data=65535 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) -{ - MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); -} - -/** - * @brief Set compare value for output channel 6 (TIMx_CCR6). - * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not - * output channel 6 is supported by a timer instance. - * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . - * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 - * @param TIMx Timer instance - * @param CompareValue between Min_Data=0 and Max_Data=65535 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) -{ - WRITE_REG(TIMx->CCR6, CompareValue); -} - -/** - * @brief Get compare value (TIMx_CCR1) set for output channel 1. - * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not - * output channel 1 is supported by a timer instance. - * @note If dithering is activated, pay attention to the returned value interpretation. - * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 - * @param TIMx Timer instance - * @retval CompareValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR1)); -} - -/** - * @brief Get compare value (TIMx_CCR2) set for output channel 2. - * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not - * output channel 2 is supported by a timer instance. - * @note If dithering is activated, pay attention to the returned value interpretation. - * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 - * @param TIMx Timer instance - * @retval CompareValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR2)); -} - -/** - * @brief Get compare value (TIMx_CCR3) set for output channel 3. - * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not - * output channel 3 is supported by a timer instance. - * @note If dithering is activated, pay attention to the returned value interpretation. - * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 - * @param TIMx Timer instance - * @retval CompareValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR3)); -} - -/** - * @brief Get compare value (TIMx_CCR4) set for output channel 4. - * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not - * output channel 4 is supported by a timer instance. - * @note If dithering is activated, pay attention to the returned value interpretation. - * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 - * @param TIMx Timer instance - * @retval CompareValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR4)); -} - -/** - * @brief Get compare value (TIMx_CCR5) set for output channel 5. - * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not - * output channel 5 is supported by a timer instance. - * @note If dithering is activated, pay attention to the returned value interpretation. - * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 - * @param TIMx Timer instance - * @retval CompareValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); -} - -/** - * @brief Get compare value (TIMx_CCR6) set for output channel 6. - * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not - * output channel 6 is supported by a timer instance. - * @note If dithering is activated, pay attention to the returned value interpretation. - * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 - * @param TIMx Timer instance - * @retval CompareValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR6)); -} - -/** - * @brief Select on which reference signal the OC5REF is combined to. - * @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports the combined 3-phase PWM mode. - * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n - * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n - * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels - * @param TIMx Timer instance - * @param GroupCH5 This parameter can be a combination of the following values: - * @arg @ref LL_TIM_GROUPCH5_NONE - * @arg @ref LL_TIM_GROUPCH5_OC1REFC - * @arg @ref LL_TIM_GROUPCH5_OC2REFC - * @arg @ref LL_TIM_GROUPCH5_OC3REFC - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) -{ - MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); -} - -/** - * @brief Set the pulse on compare pulse width prescaler. - * @note Macro @ref IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check - * whether or not the pulse on compare feature is supported by the timer - * instance. - * @rmtoll ECR PWPRSC LL_TIM_OC_SetPulseWidthPrescaler - * @param TIMx Timer instance - * @param PulseWidthPrescaler This parameter can be one of the following values: - * @arg @ref LL_TIM_PWPRSC_X1 - * @arg @ref LL_TIM_PWPRSC_X2 - * @arg @ref LL_TIM_PWPRSC_X4 - * @arg @ref LL_TIM_PWPRSC_X8 - * @arg @ref LL_TIM_PWPRSC_X16 - * @arg @ref LL_TIM_PWPRSC_X32 - * @arg @ref LL_TIM_PWPRSC_X64 - * @arg @ref LL_TIM_PWPRSC_X128 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler) -{ - MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler); -} - -/** - * @brief Get the pulse on compare pulse width prescaler. - * @note Macro @ref IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check - * whether or not the pulse on compare feature is supported by the timer - * instance. - * @rmtoll ECR PWPRSC LL_TIM_OC_GetPulseWidthPrescaler - * @param TIMx Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_PWPRSC_X1 - * @arg @ref LL_TIM_PWPRSC_X2 - * @arg @ref LL_TIM_PWPRSC_X4 - * @arg @ref LL_TIM_PWPRSC_X8 - * @arg @ref LL_TIM_PWPRSC_X16 - * @arg @ref LL_TIM_PWPRSC_X32 - * @arg @ref LL_TIM_PWPRSC_X64 - * @arg @ref LL_TIM_PWPRSC_X128 - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC)); -} - -/** - * @brief Set the pulse on compare pulse width duration. - * @note Macro @ref IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check - * whether or not the pulse on compare feature is supported by the timer - * instance. - * @rmtoll ECR PW LL_TIM_OC_SetPulseWidth - * @param TIMx Timer instance - * @param PulseWidth This parameter can be between Min_Data=0 and Max_Data=255 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWidth) -{ - MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth); -} - -/** - * @brief Get the pulse on compare pulse width duration. - * @note Macro @ref IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check - * whether or not the pulse on compare feature is supported by the timer - * instance. - * @rmtoll ECR PW LL_TIM_OC_GetPulseWidth - * @param TIMx Timer instance - * @retval Returned value can be between Min_Data=0 and Max_Data=255: - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW)); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration - * @{ - */ -/** - * @brief Configure input channel. - * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n - * CCMR1 IC1PSC LL_TIM_IC_Config\n - * CCMR1 IC1F LL_TIM_IC_Config\n - * CCMR1 CC2S LL_TIM_IC_Config\n - * CCMR1 IC2PSC LL_TIM_IC_Config\n - * CCMR1 IC2F LL_TIM_IC_Config\n - * CCMR2 CC3S LL_TIM_IC_Config\n - * CCMR2 IC3PSC LL_TIM_IC_Config\n - * CCMR2 IC3F LL_TIM_IC_Config\n - * CCMR2 CC4S LL_TIM_IC_Config\n - * CCMR2 IC4PSC LL_TIM_IC_Config\n - * CCMR2 IC4F LL_TIM_IC_Config\n - * CCER CC1P LL_TIM_IC_Config\n - * CCER CC1NP LL_TIM_IC_Config\n - * CCER CC2P LL_TIM_IC_Config\n - * CCER CC2NP LL_TIM_IC_Config\n - * CCER CC3P LL_TIM_IC_Config\n - * CCER CC3NP LL_TIM_IC_Config\n - * CCER CC4P LL_TIM_IC_Config\n - * CCER CC4NP LL_TIM_IC_Config - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @param Configuration This parameter must be a combination of all the following values: - * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC - * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 - * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 - * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE - * @retval None - */ -__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), - ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); - MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), - (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); -} - -/** - * @brief Set the active input. - * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n - * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n - * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n - * CCMR2 CC4S LL_TIM_IC_SetActiveInput - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @param ICActiveInput This parameter can be one of the following values: - * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI - * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI - * @arg @ref LL_TIM_ACTIVEINPUT_TRC - * @retval None - */ -__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); -} - -/** - * @brief Get the current active input. - * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n - * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n - * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n - * CCMR2 CC4S LL_TIM_IC_GetActiveInput - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI - * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI - * @arg @ref LL_TIM_ACTIVEINPUT_TRC - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); -} - -/** - * @brief Set the prescaler of input channel. - * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n - * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n - * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n - * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @param ICPrescaler This parameter can be one of the following values: - * @arg @ref LL_TIM_ICPSC_DIV1 - * @arg @ref LL_TIM_ICPSC_DIV2 - * @arg @ref LL_TIM_ICPSC_DIV4 - * @arg @ref LL_TIM_ICPSC_DIV8 - * @retval None - */ -__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); -} - -/** - * @brief Get the current prescaler value acting on an input channel. - * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n - * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n - * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n - * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_ICPSC_DIV1 - * @arg @ref LL_TIM_ICPSC_DIV2 - * @arg @ref LL_TIM_ICPSC_DIV4 - * @arg @ref LL_TIM_ICPSC_DIV8 - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); -} - -/** - * @brief Set the input filter duration. - * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n - * CCMR1 IC2F LL_TIM_IC_SetFilter\n - * CCMR2 IC3F LL_TIM_IC_SetFilter\n - * CCMR2 IC4F LL_TIM_IC_SetFilter - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @param ICFilter This parameter can be one of the following values: - * @arg @ref LL_TIM_IC_FILTER_FDIV1 - * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 - * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 - * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 - * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 - * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 - * @retval None - */ -__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); -} - -/** - * @brief Get the input filter duration. - * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n - * CCMR1 IC2F LL_TIM_IC_GetFilter\n - * CCMR2 IC3F LL_TIM_IC_GetFilter\n - * CCMR2 IC4F LL_TIM_IC_GetFilter - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_IC_FILTER_FDIV1 - * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 - * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 - * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 - * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 - * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); -} - -/** - * @brief Set the input channel polarity. - * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n - * CCER CC1NP LL_TIM_IC_SetPolarity\n - * CCER CC2P LL_TIM_IC_SetPolarity\n - * CCER CC2NP LL_TIM_IC_SetPolarity\n - * CCER CC3P LL_TIM_IC_SetPolarity\n - * CCER CC3NP LL_TIM_IC_SetPolarity\n - * CCER CC4P LL_TIM_IC_SetPolarity\n - * CCER CC4NP LL_TIM_IC_SetPolarity - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @param ICPolarity This parameter can be one of the following values: - * @arg @ref LL_TIM_IC_POLARITY_RISING - * @arg @ref LL_TIM_IC_POLARITY_FALLING - * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE - * @retval None - */ -__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), - ICPolarity << SHIFT_TAB_CCxP[iChannel]); -} - -/** - * @brief Get the current input channel polarity. - * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n - * CCER CC1NP LL_TIM_IC_GetPolarity\n - * CCER CC2P LL_TIM_IC_GetPolarity\n - * CCER CC2NP LL_TIM_IC_GetPolarity\n - * CCER CC3P LL_TIM_IC_GetPolarity\n - * CCER CC3NP LL_TIM_IC_GetPolarity\n - * CCER CC4P LL_TIM_IC_GetPolarity\n - * CCER CC4NP LL_TIM_IC_GetPolarity - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_IC_POLARITY_RISING - * @arg @ref LL_TIM_IC_POLARITY_FALLING - * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> - SHIFT_TAB_CCxP[iChannel]); -} - -/** - * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). - * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides an XOR input. - * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->CR2, TIM_CR2_TI1S); -} - -/** - * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. - * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides an XOR input. - * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); -} - -/** - * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. - * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides an XOR input. - * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); -} - -/** - * @brief Get captured value for input channel 1. - * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not - * input channel 1 is supported by a timer instance. - * @note If dithering is activated, pay attention to the returned value interpretation. - * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 - * @param TIMx Timer instance - * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR1)); -} - -/** - * @brief Get captured value for input channel 2. - * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not - * input channel 2 is supported by a timer instance. - * @note If dithering is activated, pay attention to the returned value interpretation. - * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 - * @param TIMx Timer instance - * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR2)); -} - -/** - * @brief Get captured value for input channel 3. - * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not - * input channel 3 is supported by a timer instance. - * @note If dithering is activated, pay attention to the returned value interpretation. - * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 - * @param TIMx Timer instance - * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR3)); -} - -/** - * @brief Get captured value for input channel 4. - * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not - * input channel 4 is supported by a timer instance. - * @note If dithering is activated, pay attention to the returned value interpretation. - * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 - * @param TIMx Timer instance - * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR4)); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection - * @{ - */ -/** - * @brief Enable external clock mode 2. - * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports external clock mode2. - * @rmtoll SMCR ECE LL_TIM_EnableExternalClock - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); -} - -/** - * @brief Disable external clock mode 2. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports external clock mode2. - * @rmtoll SMCR ECE LL_TIM_DisableExternalClock - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); -} - -/** - * @brief Indicate whether external clock mode 2 is enabled. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports external clock mode2. - * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); -} - -/** - * @brief Set the clock source of the counter clock. - * @note when selected clock source is external clock mode 1, the timer input - * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() - * function. This timer input must be configured by calling - * the @ref LL_TIM_IC_Config() function. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports external clock mode1. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports external clock mode2. - * @rmtoll SMCR SMS LL_TIM_SetClockSource\n - * SMCR ECE LL_TIM_SetClockSource - * @param TIMx Timer instance - * @param ClockSource This parameter can be one of the following values: - * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL - * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 - * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) -{ - MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); -} - -/** - * @brief Set the encoder interface mode. - * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports the encoder mode. - * @rmtoll SMCR SMS LL_TIM_SetEncoderMode - * @param TIMx Timer instance - * @param EncoderMode This parameter can be one of the following values: - * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 - * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 - * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 - * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 - * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 - * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 - * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 - * @arg @ref LL_TIM_ENCODERMODE_X1_TI1 - * @arg @ref LL_TIM_ENCODERMODE_X1_TI2 - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) -{ - MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration - * @{ - */ -/** - * @brief Set the trigger output (TRGO) used for timer synchronization . - * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance can operate as a master timer. - * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput - * @param TIMx Timer instance - * @param TimerSynchronization This parameter can be one of the following values: - * @arg @ref LL_TIM_TRGO_RESET - * @arg @ref LL_TIM_TRGO_ENABLE - * @arg @ref LL_TIM_TRGO_UPDATE - * @arg @ref LL_TIM_TRGO_CC1IF - * @arg @ref LL_TIM_TRGO_OC1REF - * @arg @ref LL_TIM_TRGO_OC2REF - * @arg @ref LL_TIM_TRGO_OC3REF - * @arg @ref LL_TIM_TRGO_OC4REF - * @arg @ref LL_TIM_TRGO_ENCODERCLK - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) -{ - MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); -} - -/** - * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . - * @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check - * whether or not a timer instance can be used for ADC synchronization. - * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 - * @param TIMx Timer Instance - * @param ADCSynchronization This parameter can be one of the following values: - * @arg @ref LL_TIM_TRGO2_RESET - * @arg @ref LL_TIM_TRGO2_ENABLE - * @arg @ref LL_TIM_TRGO2_UPDATE - * @arg @ref LL_TIM_TRGO2_CC1F - * @arg @ref LL_TIM_TRGO2_OC1 - * @arg @ref LL_TIM_TRGO2_OC2 - * @arg @ref LL_TIM_TRGO2_OC3 - * @arg @ref LL_TIM_TRGO2_OC4 - * @arg @ref LL_TIM_TRGO2_OC5 - * @arg @ref LL_TIM_TRGO2_OC6 - * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING - * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING - * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING - * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING - * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING - * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) -{ - MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); -} - -/** - * @brief Set the synchronization mode of a slave timer. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not - * a timer instance can operate as a slave timer. - * @rmtoll SMCR SMS LL_TIM_SetSlaveMode - * @param TIMx Timer instance - * @param SlaveMode This parameter can be one of the following values: - * @arg @ref LL_TIM_SLAVEMODE_DISABLED - * @arg @ref LL_TIM_SLAVEMODE_RESET - * @arg @ref LL_TIM_SLAVEMODE_GATED - * @arg @ref LL_TIM_SLAVEMODE_TRIGGER - * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER - * @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) -{ - MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); -} - -/** - * @brief Set the selects the trigger input to be used to synchronize the counter. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not - * a timer instance can operate as a slave timer. - * @rmtoll SMCR TS LL_TIM_SetTriggerInput - * @param TIMx Timer instance - * @param TriggerInput This parameter can be one of the following values: - * @arg @ref LL_TIM_TS_ITR0 - * @arg @ref LL_TIM_TS_ITR1 - * @arg @ref LL_TIM_TS_ITR2 - * @arg @ref LL_TIM_TS_ITR3 - * @arg @ref LL_TIM_TS_TI1F_ED - * @arg @ref LL_TIM_TS_TI1FP1 - * @arg @ref LL_TIM_TS_TI2FP2 - * @arg @ref LL_TIM_TS_ETRF - * @arg @ref LL_TIM_TS_ITR4 - * @arg @ref LL_TIM_TS_ITR5 - * @arg @ref LL_TIM_TS_ITR6 - * @arg @ref LL_TIM_TS_ITR7 - * @arg @ref LL_TIM_TS_ITR8 - * @arg @ref LL_TIM_TS_ITR9 - * @arg @ref LL_TIM_TS_ITR10 - * @arg @ref LL_TIM_TS_ITR11 - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) -{ - MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); -} - -/** - * @brief Enable the Master/Slave mode. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not - * a timer instance can operate as a slave timer. - * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); -} - -/** - * @brief Disable the Master/Slave mode. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not - * a timer instance can operate as a slave timer. - * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); -} - -/** - * @brief Indicates whether the Master/Slave mode is enabled. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not - * a timer instance can operate as a slave timer. - * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); -} - -/** - * @brief Configure the external trigger (ETR) input. - * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides an external trigger input. - * @rmtoll SMCR ETP LL_TIM_ConfigETR\n - * SMCR ETPS LL_TIM_ConfigETR\n - * SMCR ETF LL_TIM_ConfigETR - * @param TIMx Timer instance - * @param ETRPolarity This parameter can be one of the following values: - * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED - * @arg @ref LL_TIM_ETR_POLARITY_INVERTED - * @param ETRPrescaler This parameter can be one of the following values: - * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 - * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 - * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 - * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 - * @param ETRFilter This parameter can be one of the following values: - * @arg @ref LL_TIM_ETR_FILTER_FDIV1 - * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 - * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 - * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 - * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 - * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 - * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 - * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 - * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 - * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 - * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 - * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 - * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 - * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 - * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 - * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 - * @retval None - */ -__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, - uint32_t ETRFilter) -{ - MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); -} - -/** - * @brief Select the external trigger (ETR) input source. - * @note Macro @ref IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or - * not a timer instance supports ETR source selection. - * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource - * @param TIMx Timer instance - * @param ETRSource This parameter can be one of the following values: - * - * TIM1: any combination of ETR_RMP where - * - * @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO - * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1 - * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP2 - * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP3 - * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP4 - * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP5 (*) - * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP6 (*) - * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP7 (*) - * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 - * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 - * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 - * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 (*) - * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 (*) - * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 (*) - * - * TIM2: any combination of ETR_RMP where - * - * @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO - * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1 - * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP2 - * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP3 - * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP4 - * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP5 (*) - * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP6 (*) - * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP7 (*) - * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR - * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR - * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (*) - * @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE - * - * TIM3: any combination of ETR_RMP where - * - * @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO - * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1 - * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP2 - * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP3 - * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP4 - * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP5 (*) - * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP6 (*) - * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP7 (*) - * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR - * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR - * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1 - * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2 - * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3 - * - * TIM4: any combination of ETR_RMP where - * - * @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO - * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP1 - * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP2 - * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP3 - * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP4 - * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP5 (*) - * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP6 (*) - * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP7 (*) - * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR - * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR (*) - * - * TIM5: any combination of ETR_RMP where (**) - * - * @arg @ref LL_TIM_TIM5_ETRSOURCE_GPIO (*) - * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP1 (*) - * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP2 (*) - * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP3 (*) - * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP4 (*) - * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP5 (*) - * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP6 (*) - * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP7 (*) - * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR (*) - * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR (*) - * - * TIM8: any combination of ETR_RMP where - * - * . . ETR_RMP can be one of the following values - * @arg @ref LL_TIM_TIM8_ETRSOURCE_GPIO - * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP1 - * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP2 - * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP3 - * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP4 - * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP5 (*) - * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP6 (*) - * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP7 (*) - * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 - * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 - * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 - * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (*) - * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (*) - * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 (*) - * - * TIM20: any combination of ETR_RMP where (**) - * - * . . ETR_RMP can be one of the following values - * @arg @ref LL_TIM_TIM20_ETRSOURCE_GPIO (*) - * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP1 (*) - * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP2 (*) - * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP3 (*) - * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP4 (*) - * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP5 (*) - * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP6 (*) - * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP7 (*) - * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD1 (*) - * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD2 (*) - * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD3 (*) - * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD1 (*) - * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD2 (*) - * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD3 (*) - * - * (*) Value not defined in all devices. \n - * (**) Register not available in all devices. - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource) -{ - - MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource); -} - -/** - * @brief Enable SMS preload. - * @note Macro @ref IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports the preload of SMS field in SMCR register. - * @rmtoll SMCR SMSPE LL_TIM_EnableSMSPreload - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE); -} - -/** - * @brief Disable SMS preload. - * @note Macro @ref IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports the preload of SMS field in SMCR register. - * @rmtoll SMCR SMSPE LL_TIM_DisableSMSPreload - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE); -} - -/** - * @brief Indicate whether SMS preload is enabled. - * @note Macro @ref IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports the preload of SMS field in SMCR register. - * @rmtoll SMCR SMSPE LL_TIM_IsEnabledSMSPreload - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL); -} - -/** - * @brief Set the preload source of SMS. - * @note Macro @ref IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports the preload of SMS field in SMCR register. - * @rmtoll SMCR SMSPS LL_TIM_SetSMSPreloadSource\n - * @param TIMx Timer instance - * @param PreloadSource This parameter can be one of the following values: - * @arg @ref LL_TIM_SMSPS_TIMUPDATE - * @arg @ref LL_TIM_SMSPS_INDEX - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t PreloadSource) -{ - MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource); -} - -/** - * @brief Get the preload source of SMS. - * @note Macro @ref IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports the preload of SMS field in SMCR register. - * @rmtoll SMCR SMSPS LL_TIM_GetSMSPreloadSource\n - * @param TIMx Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_SMSPS_TIMUPDATE - * @arg @ref LL_TIM_SMSPS_INDEX - */ -__STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS)); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_Break_Function Break function configuration - * @{ - */ -/** - * @brief Enable the break function. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR BKE LL_TIM_EnableBRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); -} - -/** - * @brief Disable the break function. - * @rmtoll BDTR BKE LL_TIM_DisableBRK - * @param TIMx Timer instance - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); -} - -/** - * @brief Configure the break input. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @note Bidirectional mode is only supported by advanced timer instances. - * Macro @ref IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not - * a timer instance is an advanced-control timer. - * @note In bidirectional mode (BKBID bit set), the Break input is configured both - * in input mode and in open drain output mode. Any active Break event will - * assert a low logic level on the Break input to indicate an internal break - * event to external devices. - * @note When bidirectional mode isn't supported, BreakAFMode must be set to - * LL_TIM_BREAK_AFMODE_INPUT. - * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n - * BDTR BKF LL_TIM_ConfigBRK\n - * BDTR BKBID LL_TIM_ConfigBRK - * @param TIMx Timer instance - * @param BreakPolarity This parameter can be one of the following values: - * @arg @ref LL_TIM_BREAK_POLARITY_LOW - * @arg @ref LL_TIM_BREAK_POLARITY_HIGH - * @param BreakFilter This parameter can be one of the following values: - * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 - * @param BreakAFMode This parameter can be one of the following values: - * @arg @ref LL_TIM_BREAK_AFMODE_INPUT - * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL - * @retval None - */ -__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter, - uint32_t BreakAFMode) -{ - MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode); -} - -/** - * @brief Disarm the break input (when it operates in bidirectional mode). - * @note The break input can be disarmed only when it is configured in - * bidirectional mode and when when MOE is reset. - * @note Purpose is to be able to have the input voltage back to high-state, - * whatever the time constant on the output . - * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); -} - -/** - * @brief Re-arm the break input (when it operates in bidirectional mode). - * @note The Break input is automatically armed as soon as MOE bit is set. - * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); -} - -/** - * @brief Enable the break 2 function. - * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a second break input. - * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); -} - -/** - * @brief Disable the break 2 function. - * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a second break input. - * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); -} - -/** - * @brief Configure the break 2 input. - * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a second break input. - * @note Bidirectional mode is only supported by advanced timer instances. - * Macro @ref IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not - * a timer instance is an advanced-control timer. - * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both - * in input mode and in open drain output mode. Any active Break event will - * assert a low logic level on the Break 2 input to indicate an internal break - * event to external devices. - * @note When bidirectional mode isn't supported, Break2AFMode must be set to - * LL_TIM_BREAK2_AFMODE_INPUT. - * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n - * BDTR BK2F LL_TIM_ConfigBRK2\n - * BDTR BK2BID LL_TIM_ConfigBRK2 - * @param TIMx Timer instance - * @param Break2Polarity This parameter can be one of the following values: - * @arg @ref LL_TIM_BREAK2_POLARITY_LOW - * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH - * @param Break2Filter This parameter can be one of the following values: - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 - * @param Break2AFMode This parameter can be one of the following values: - * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT - * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL - * @retval None - */ -__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter, - uint32_t Break2AFMode) -{ - MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode); -} - -/** - * @brief Disarm the break 2 input (when it operates in bidirectional mode). - * @note The break 2 input can be disarmed only when it is configured in - * bidirectional mode and when when MOE is reset. - * @note Purpose is to be able to have the input voltage back to high-state, - * whatever the time constant on the output. - * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); -} - -/** - * @brief Re-arm the break 2 input (when it operates in bidirectional mode). - * @note The Break 2 input is automatically armed as soon as MOE bit is set. - * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); -} - -/** - * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n - * BDTR OSSR LL_TIM_SetOffStates - * @param TIMx Timer instance - * @param OffStateIdle This parameter can be one of the following values: - * @arg @ref LL_TIM_OSSI_DISABLE - * @arg @ref LL_TIM_OSSI_ENABLE - * @param OffStateRun This parameter can be one of the following values: - * @arg @ref LL_TIM_OSSR_DISABLE - * @arg @ref LL_TIM_OSSR_ENABLE - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) -{ - MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); -} - -/** - * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); -} - -/** - * @brief Disable automatic output (MOE can be set only by software). - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); -} - -/** - * @brief Indicate whether automatic output is enabled. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); -} - -/** - * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). - * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by - * software and is reset in case of break or break2 event - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); -} - -/** - * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). - * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by - * software and is reset in case of break or break2 event. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); -} - -/** - * @brief Indicates whether outputs are enabled. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); -} - -/** - * @brief Enable the signals connected to the designated timer break input. - * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether - * or not a timer instance allows for break input selection. - * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n - * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n - * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n - * AF1 BKCMP3E LL_TIM_EnableBreakInputSource\n - * AF1 BKCMP4E LL_TIM_EnableBreakInputSource\n - * AF1 BKCMP5E LL_TIM_EnableBreakInputSource\n - * AF1 BKCMP6E LL_TIM_EnableBreakInputSource\n - * AF1 BKCMP7E LL_TIM_EnableBreakInputSource\n - * AF2 BK2NE LL_TIM_EnableBreakInputSource\n - * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n - * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n - * AF2 BK2CMP3E LL_TIM_EnableBreakInputSource\n - * AF2 BK2CMP4E LL_TIM_EnableBreakInputSource\n - * AF2 BK2CMP5E LL_TIM_EnableBreakInputSource\n - * AF2 BK2CMP6E LL_TIM_EnableBreakInputSource\n - * AF2 BK2CMP7E LL_TIM_EnableBreakInputSource - * @param TIMx Timer instance - * @param BreakInput This parameter can be one of the following values: - * @arg @ref LL_TIM_BREAK_INPUT_BKIN - * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 - * @param Source This parameter can be one of the following values: - * @arg @ref LL_TIM_BKIN_SOURCE_BKIN - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3 - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4 - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP5 (*) - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP6 (*) - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP7 (*) - * - * (*) Value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) -{ - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); - SET_BIT(*pReg, Source); -} - -/** - * @brief Disable the signals connected to the designated timer break input. - * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether - * or not a timer instance allows for break input selection. - * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n - * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n - * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n - * AF1 BKCMP3E LL_TIM_DisableBreakInputSource\n - * AF1 BKCMP4E LL_TIM_DisableBreakInputSource\n - * AF1 BKCMP5E LL_TIM_DisableBreakInputSource\n - * AF1 BKCMP6E LL_TIM_DisableBreakInputSource\n - * AF1 BKCMP7E LL_TIM_DisableBreakInputSource\n - * AF2 BKINE LL_TIM_DisableBreakInputSource\n - * AF2 BKCMP1E LL_TIM_DisableBreakInputSource\n - * AF2 BKCMP2E LL_TIM_DisableBreakInputSource\n - * AF2 BKCMP3E LL_TIM_DisableBreakInputSource\n - * AF2 BKCMP4E LL_TIM_DisableBreakInputSource\n - * AF2 BKCMP5E LL_TIM_DisableBreakInputSource\n - * AF2 BKCMP6E LL_TIM_DisableBreakInputSource\n - * AF2 BKCMP7E LL_TIM_DisableBreakInputSource - * @param TIMx Timer instance - * @param BreakInput This parameter can be one of the following values: - * @arg @ref LL_TIM_BREAK_INPUT_BKIN - * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 - * @param Source This parameter can be one of the following values: - * @arg @ref LL_TIM_BKIN_SOURCE_BKIN - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3 - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4 - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP5 (*) - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP6 (*) - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP7 (*) - * - * (*) Value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) -{ - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); - CLEAR_BIT(*pReg, Source); -} - -/** - * @brief Set the polarity of the break signal for the timer break input. - * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether - * or not a timer instance allows for break input selection. - * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n - * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n - * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n - * AF1 BKCMP3P LL_TIM_SetBreakInputSourcePolarity\n - * AF1 BKCMP4P LL_TIM_SetBreakInputSourcePolarity\n - * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n - * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n - * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity\n - * AF2 BK2CMP3P LL_TIM_SetBreakInputSourcePolarity\n - * AF2 BK2CMP4P LL_TIM_SetBreakInputSourcePolarity - * @param TIMx Timer instance - * @param BreakInput This parameter can be one of the following values: - * @arg @ref LL_TIM_BREAK_INPUT_BKIN - * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 - * @param Source This parameter can be one of the following values: - * @arg @ref LL_TIM_BKIN_SOURCE_BKIN - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3 - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4 - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_TIM_BKIN_POLARITY_LOW - * @arg @ref LL_TIM_BKIN_POLARITY_HIGH - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, - uint32_t Polarity) -{ - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); - MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE)); -} -/** - * @brief Enable asymmetrical deadtime. - * @note Macro @ref IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides asymmetrical deadtime. - * @rmtoll DTR2 DTAE LL_TIM_EnableAsymmetricalDeadTime - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE); -} - -/** - * @brief Disable asymmetrical dead-time. - * @note Macro @ref IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides asymmetrical deadtime. - * @rmtoll DTR2 DTAE LL_TIM_DisableAsymmetricalDeadTime - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE); -} - -/** - * @brief Indicates whether asymmetrical deadtime is activated. - * @note Macro @ref IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides asymmetrical deadtime. - * @rmtoll DTR2 DTAE LL_TIM_IsEnabledAsymmetricalDeadTime - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); -} - -/** - * @brief Set the falling egde dead-time delay (delay inserted between the falling edge of the OCxREF signal and the rising edge of OCxN signals). - * @note Macro @ref IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not - * asymmetrical dead-time insertion feature is supported by a timer instance. - * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter - * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed - * (LOCK bits in TIMx_BDTR register). - * @rmtoll DTR2 DTGF LL_TIM_SetFallingDeadTime - * @param TIMx Timer instance - * @param DeadTime between Min_Data=0 and Max_Data=255 - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) -{ - MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime); -} - -/** - * @brief Get the falling egde dead-time delay (delay inserted between the falling edge of the OCxREF signal and the rising edge of OCxN signals). - * @note Macro @ref IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not - * asymmetrical dead-time insertion feature is supported by a timer instance. - * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed - * (LOCK bits in TIMx_BDTR register). - * @rmtoll DTR2 DTGF LL_TIM_GetFallingDeadTime - * @param TIMx Timer instance - * @retval Returned value can be between Min_Data=0 and Max_Data=255: - */ -__STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF)); -} - -/** - * @brief Enable deadtime preload. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides deadtime preload. - * @rmtoll DTR2 DTPE LL_TIM_EnableDeadTimePreload - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE); -} - -/** - * @brief Disable dead-time preload. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides deadtime preload. - * @rmtoll DTR2 DTPE LL_TIM_DisableDeadTimePreload - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE); -} - -/** - * @brief Indicates whether deadtime preload is activated. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides deadtime preload. - * @rmtoll DTR2 DTPE LL_TIM_IsEnabledDeadTimePreload - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration - * @{ - */ -/** - * @brief Configures the timer DMA burst feature. - * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or - * not a timer instance supports the DMA burst mode. - * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n - * DCR DBA LL_TIM_ConfigDMABurst - * @param TIMx Timer instance - * @param DMABurstBaseAddress This parameter can be one of the following values: - * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 - * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR - * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER - * @arg @ref LL_TIM_DMABURST_BASEADDR_SR - * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER - * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT - * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC - * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR - * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 - * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 - * @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2 - * @arg @ref LL_TIM_DMABURST_BASEADDR_ECR - * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL - * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 - * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 - * @arg @ref LL_TIM_DMABURST_BASEADDR_OR - * @param DMABurstLength This parameter can be one of the following values: - * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER - * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS - * @retval None - */ -__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) -{ - MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_Encoder Encoder configuration - * @{ - */ - -/** - * @brief Enable encoder index. - * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides an index input. - * @rmtoll ECR IE LL_TIM_EnableEncoderIndex - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->ECR, TIM_ECR_IE); -} - -/** - * @brief Disable encoder index. - * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides an index input. - * @rmtoll ECR IE LL_TIM_DisableEncoderIndex - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->ECR, TIM_ECR_IE); -} - -/** - * @brief Indicate whether encoder index is enabled. - * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides an index input. - * @rmtoll ECR IE LL_TIM_IsEnabledEncoderIndex - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U); -} - -/** - * @brief Set index direction - * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides an index input. - * @rmtoll ECR IDIR LL_TIM_SetIndexDirection - * @param TIMx Timer instance - * @param IndexDirection This parameter can be one of the following values: - * @arg @ref LL_TIM_INDEX_UP_DOWN - * @arg @ref LL_TIM_INDEX_UP - * @arg @ref LL_TIM_INDEX_DOWN - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexDirection) -{ - MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection); -} - -/** - * @brief Get actual index direction - * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides an index input. - * @rmtoll ECR IDIR LL_TIM_GetIndexDirection - * @param TIMx Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_INDEX_UP_DOWN - * @arg @ref LL_TIM_INDEX_UP - * @arg @ref LL_TIM_INDEX_DOWN - */ -__STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR)); -} - -/** - * @brief Enable first index. - * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides an index input. - * @rmtoll ECR FIDX LL_TIM_EnableFirstIndex - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->ECR, TIM_ECR_FIDX); -} - -/** - * @brief Disable first index. - * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides an index input. - * @rmtoll ECR FIDX LL_TIM_DisableFirstIndex - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX); -} - -/** - * @brief Indicates whether first index is enabled. - * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides an index input. - * @rmtoll ECR FIDX LL_TIM_IsEnabledFirstIndex - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL); -} - -/** - * @brief Set index positionning - * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides an index input. - * @rmtoll ECR IPOS LL_TIM_SetIndexPositionning - * @param TIMx Timer instance - * @param IndexPositionning This parameter can be one of the following values: - * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN - * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP - * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN - * @arg @ref LL_TIM_INDEX_POSITION_UP_UP - * @arg @ref LL_TIM_INDEX_POSITION_DOWN - * @arg @ref LL_TIM_INDEX_POSITION_UP - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t IndexPositionning) -{ - MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning); -} - -/** - * @brief Get actual index positionning - * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides an index input. - * @rmtoll ECR IPOS LL_TIM_GetIndexPositionning - * @param TIMx Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN - * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP - * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN - * @arg @ref LL_TIM_INDEX_POSITION_UP_UP - * @arg @ref LL_TIM_INDEX_POSITION_DOWN - * @arg @ref LL_TIM_INDEX_POSITION_UP - */ -__STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS)); -} - -/** - * @brief Configure encoder index. - * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides an index input. - * @rmtoll ECR IDIR LL_TIM_ConfigIDX\n - * ECR FIDX LL_TIM_ConfigIDX\n - * ECR IPOS LL_TIM_ConfigIDX - * @param TIMx Timer instance - * @param Configuration This parameter must be a combination of all the following values: - * @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref LL_TIM_INDEX_UP_DOWN - * @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY - * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref LL_TIM_INDEX_POSITION_UP - * @retval None - */ -__STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration) -{ - MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping - * @{ - */ -/** - * @brief Remap TIM inputs (input channel, internal/external triggers). - * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not - * a some timer inputs can be remapped. - * @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n - * TIM2_TISEL TI1SEL LL_TIM_SetRemap\n - * TIM2_TISEL TI2SEL LL_TIM_SetRemap\n - * TIM2_TISEL TI3SEL LL_TIM_SetRemap\n - * TIM2_TISEL TI4SEL LL_TIM_SetRemap\n - * TIM3_TISEL TI1SEL LL_TIM_SetRemap\n - * TIM3_TISEL TI2SEL LL_TIM_SetRemap\n - * TIM3_TISEL TI3SEL LL_TIM_SetRemap\n - * TIM4_TISEL TI1SEL LL_TIM_SetRemap\n - * TIM4_TISEL TI2SEL LL_TIM_SetRemap\n - * TIM4_TISEL TI3SEL LL_TIM_SetRemap\n - * TIM4_TISEL TI4SEL LL_TIM_SetRemap\n - * TIM5_TISEL TI1SEL LL_TIM_SetRemap\n - * TIM5_TISEL TI2SEL LL_TIM_SetRemap\n - * TIM8_TISEL TI1SEL LL_TIM_SetRemap\n - * TIM15_TISEL TI1SEL LL_TIM_SetRemap\n - * TIM15_TISEL TI2SEL LL_TIM_SetRemap\n - * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n - * TIM17_TISEL TI1SEL LL_TIM_SetRemap\n - * TIM20_TISEL TI1SEL LL_TIM_SetRemap - * @param TIMx Timer instance - * @param Remap Remap param depends on the TIMx. Description available only - * in CHM version of the User Manual (not in .pdf). - * Otherwise see Reference Manual description of TISEL registers. - * - * Below description summarizes "Timer Instance" and "Remap" param combinations: - * - * TIM1: one of the following values - * - * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO - * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1 - * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP2 - * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP3 - * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP4 - * - * TIM2: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where - * - * . . TI1_RMP can be one of the following values - * @arg @ref LL_TIM_TIM2_TI1_RMP_GPIO - * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP1 - * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP2 - * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP3 - * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP4 - * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP5 (*) - * - * . . TI2_RMP can be one of the following values - * @arg @ref LL_TIM_TIM2_TI2_RMP_GPIO - * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP1 - * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP2 - * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP3 - * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP4 - * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP6 (*) - * - * . . TI3_RMP can be one of the following values - * @arg @ref LL_TIM_TIM2_TI3_RMP_GPIO - * @arg @ref LL_TIM_TIM2_TI3_RMP_COMP4 - * - * . . TI4_RMP can be one of the following values - * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO - * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1 - * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2 - * - * TIM3: any combination of TI1_RMP and TI2_RMP where - * - * . . TI1_RMP can be one of the following values - * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO - * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1 - * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2 - * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP3 - * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP4 - * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP5 (*) - * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP6 (*) - * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP7 (*) - * - * . . TI2_RMP can be one of the following values - * @arg @ref LL_TIM_TIM3_TI2_RMP_GPIO - * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP1 - * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP2 - * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP3 - * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP4 - * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP5 (*) - * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP6 (*) - * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP7 (*) - * - * . . TI3_RMP can be one of the following values - * @arg @ref LL_TIM_TIM3_TI3_RMP_GPIO - * @arg @ref LL_TIM_TIM3_TI3_RMP_COMP3 - * - * TIM4: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where - * - * . . TI1_RMP can be one of the following values - * @arg @ref LL_TIM_TIM4_TI1_RMP_GPIO - * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP1 - * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP2 - * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP3 - * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP4 - * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP5 (*) - * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP6 (*) - * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP7 (*) - * - * . . TI2_RMP can be one of the following values - * @arg @ref LL_TIM_TIM4_TI2_RMP_GPIO - * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP1 - * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP2 - * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP3 - * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP4 - * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP5 (*) - * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP6 (*) - * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP7 (*) - * - * . . TI3_RMP can be one of the following values - * @arg @ref LL_TIM_TIM4_TI3_RMP_GPIO - * @arg @ref LL_TIM_TIM4_TI3_RMP_COMP5 (*) - * - * . . TI4_RMP can be one of the following values - * @arg @ref LL_TIM_TIM4_TI4_RMP_GPIO - * @arg @ref LL_TIM_TIM4_TI4_RMP_COMP6 (*) - * - * TIM5: any combination of TI1_RMP and TI2_RMP where (**) - * - * . . TI1_RMP can be one of the following values - * @arg @ref LL_TIM_TIM5_TI1_RMP_GPIO (*) - * @arg @ref LL_TIM_TIM5_TI1_RMP_LSI (*) - * @arg @ref LL_TIM_TIM5_TI1_RMP_LSE (*) - * @arg @ref LL_TIM_TIM5_TI1_RMP_RTC_WK (*) - * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP1 (*) - * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP2 (*) - * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP3 (*) - * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP4 (*) - * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP5 (*) - * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP6 (*) - * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP7 (*) - * - * . . TI2_RMP can be one of the following values - * @arg @ref LL_TIM_TIM5_TI2_RMP_GPIO (*) - * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP1 (*) - * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP2 (*) - * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP3 (*) - * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP4 (*) - * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP5 (*) - * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP6 (*) - * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP7 (*) - * - * TIM8: one of the following values - * - * @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO - * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP1 - * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2 - * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP3 - * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP4 - * - * TIM15: any combination of TI1_RMP and TI2_RMP where - * - * . . TI1_RMP can be one of the following values - * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO - * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE - * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP1 - * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP2 - * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP5 (*) - * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP7 (*) - * - * . . TI2_RMP can be one of the following values - * @arg @ref LL_TIM_TIM15_TI2_RMP_GPIO - * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP2 - * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP3 - * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP6 (*) - * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP7 (*) - * - * TIM16: one of the following values - * - * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO - * @arg @ref LL_TIM_TIM16_TI1_RMP_COMP6 (*) - * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO - * @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32 - * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC_WK - * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE - * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI - * - * TIM17: one of the following values - * - * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO - * @arg @ref LL_TIM_TIM17_TI1_RMP_COMP5 (*) - * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO - * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32 - * @arg @ref LL_TIM_TIM17_TI1_RMP_RTC_WK - * @arg @ref LL_TIM_TIM17_TI1_RMP_LSE - * @arg @ref LL_TIM_TIM17_TI1_RMP_LSI - * - * TIM20: one of the following values (**) - * - * @arg @ref LL_TIM_TIM20_TI1_RMP_GPIO (*) - * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP1 (*) - * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP2 (*) - * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP3 (*) - * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP4 (*) - * - * (*) Value not defined in all devices. \n - * (**) Register not available in all devices. - * - * - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) -{ - MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap); -} - -/** - * @brief Enable request for HSE/32 clock used for TISEL remap. - * @note Only TIM16 and TIM17 support HSE/32 remap - * @rmtoll OR HSE32EN LL_TIM_EnableHSE32 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableHSE32(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->OR, TIM_OR_HSE32EN); -} - -/** - * @brief Disable request for HSE/32 clock used for TISEL remap. - * @note Only TIM16 and TIM17 support HSE/32 remap - * @rmtoll OR HSE32EN LL_TIM_DisableHSE32 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableHSE32(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->OR, TIM_OR_HSE32EN); -} - -/** - * @brief Indicate whether request for HSE/32 clock is enabled. - * @note Only TIM16 and TIM17 support HSE/32 remap - * @rmtoll OR HSE32EN LL_TIM_IsEnabledHSE32 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledHSE32(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->OR, TIM_OR_HSE32EN) == (TIM_OR_HSE32EN)) ? 1UL : 0UL); -} -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management - * @{ - */ -/** - * @brief Set the OCREF clear input source - * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT - * @note This function can only be used in Output compare and PWM modes. - * @note Macro @ref IS_TIM_OCCS_INSTANCE(TIMx) can be used to check whether - * or not a timer instance can configure OCREF clear input source. - * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource - * @rmtoll AF2 OCRSEL LL_TIM_SetOCRefClearInputSource - * @param TIMx Timer instance - * @param OCRefClearInputSource This parameter can be one of the following values: - * @arg @ref LL_TIM_OCREF_CLR_INT_ETR - * @arg @ref LL_TIM_OCREF_CLR_INT_COMP1 - * @arg @ref LL_TIM_OCREF_CLR_INT_COMP2 - * @arg @ref LL_TIM_OCREF_CLR_INT_COMP3 - * @arg @ref LL_TIM_OCREF_CLR_INT_COMP4 - * @arg @ref LL_TIM_OCREF_CLR_INT_COMP5 (*) - * @arg @ref LL_TIM_OCREF_CLR_INT_COMP6 (*) - * @arg @ref LL_TIM_OCREF_CLR_INT_COMP7 (*) - * - * (*) Value not defined in all devices. \n - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource) -{ - MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, - ((OCRefClearInputSource & OCREF_CLEAR_SELECT_Msk) >> OCREF_CLEAR_SELECT_Pos) << TIM_SMCR_OCCS_Pos); - MODIFY_REG(TIMx->AF2, TIM1_AF2_OCRSEL, OCRefClearInputSource); -} -/** - * @} - */ - -/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management - * @{ - */ -/** - * @brief Clear the update interrupt flag (UIF). - * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); -} - -/** - * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). - * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). - * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); -} - -/** - * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). - * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). - * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); -} - -/** - * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). - * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). - * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); -} - -/** - * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). - * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). - * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); -} - -/** - * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). - * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). - * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); -} - -/** - * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending). - * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). - * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); -} - -/** - * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending). - * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the commutation interrupt flag (COMIF). - * @rmtoll SR COMIF LL_TIM_ClearFlag_COM - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); -} - -/** - * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). - * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the trigger interrupt flag (TIF). - * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); -} - -/** - * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). - * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the break interrupt flag (BIF). - * @rmtoll SR BIF LL_TIM_ClearFlag_BRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); -} - -/** - * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). - * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the break 2 interrupt flag (B2IF). - * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); -} - -/** - * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). - * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). - * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); -} - -/** - * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending). - * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). - * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); -} - -/** - * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending). - * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). - * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); -} - -/** - * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending). - * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). - * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); -} - -/** - * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending). - * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the system break interrupt flag (SBIF). - * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); -} - -/** - * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending). - * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the transition error interrupt flag (TERRF). - * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides encoder error management. - * @rmtoll SR TERRF LL_TIM_ClearFlag_TERR - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF)); -} - -/** - * @brief Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending). - * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides encoder error management. - * @rmtoll SR TERRF LL_TIM_IsActiveFlag_TERR - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the index error interrupt flag (IERRF). - * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides encoder error management. - * @rmtoll SR IERRF LL_TIM_ClearFlag_IERR - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF)); -} - -/** - * @brief Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending). - * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides encoder error management. - * @rmtoll SR IERRF LL_TIM_IsActiveFlag_IERR - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the direction change interrupt flag (DIRF). - * @note Macro @ref IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides encoder interrupt management. - * @rmtoll SR DIRF LL_TIM_ClearFlag_DIR - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF)); -} - -/** - * @brief Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending). - * @note Macro @ref IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides encoder interrupt management. - * @rmtoll SR DIRF LL_TIM_IsActiveFlag_DIR - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the index interrupt flag (IDXF). - * @note Macro @ref IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides encoder interrupt management. - * @rmtoll SR IDXF LL_TIM_ClearFlag_IDX - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF)); -} - -/** - * @brief Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending). - * @note Macro @ref IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides encoder interrupt management. - * @rmtoll SR IDXF LL_TIM_IsActiveFlag_IDX - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL); -} -/** - * @} - */ - -/** @defgroup TIM_LL_EF_IT_Management IT-Management - * @{ - */ -/** - * @brief Enable update interrupt (UIE). - * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_UIE); -} - -/** - * @brief Disable update interrupt (UIE). - * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); -} - -/** - * @brief Indicates whether the update interrupt (UIE) is enabled. - * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 1 interrupt (CC1IE). - * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); -} - -/** - * @brief Disable capture/compare 1 interrupt (CC1IE). - * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); -} - -/** - * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. - * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 2 interrupt (CC2IE). - * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); -} - -/** - * @brief Disable capture/compare 2 interrupt (CC2IE). - * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); -} - -/** - * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. - * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 3 interrupt (CC3IE). - * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); -} - -/** - * @brief Disable capture/compare 3 interrupt (CC3IE). - * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); -} - -/** - * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. - * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 4 interrupt (CC4IE). - * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); -} - -/** - * @brief Disable capture/compare 4 interrupt (CC4IE). - * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); -} - -/** - * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. - * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); -} - -/** - * @brief Enable commutation interrupt (COMIE). - * @rmtoll DIER COMIE LL_TIM_EnableIT_COM - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_COMIE); -} - -/** - * @brief Disable commutation interrupt (COMIE). - * @rmtoll DIER COMIE LL_TIM_DisableIT_COM - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); -} - -/** - * @brief Indicates whether the commutation interrupt (COMIE) is enabled. - * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable trigger interrupt (TIE). - * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_TIE); -} - -/** - * @brief Disable trigger interrupt (TIE). - * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); -} - -/** - * @brief Indicates whether the trigger interrupt (TIE) is enabled. - * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable break interrupt (BIE). - * @rmtoll DIER BIE LL_TIM_EnableIT_BRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_BIE); -} - -/** - * @brief Disable break interrupt (BIE). - * @rmtoll DIER BIE LL_TIM_DisableIT_BRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); -} - -/** - * @brief Indicates whether the break interrupt (BIE) is enabled. - * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable transition error interrupt (TERRIE). - * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides encoder error management. - * @rmtoll DIER TERRIE LL_TIM_EnableIT_TERR - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_TERRIE); -} - -/** - * @brief Disable transition error interrupt (TERRIE). - * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides encoder error management. - * @rmtoll DIER TERRIE LL_TIM_DisableIT_TERR - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE); -} - -/** - * @brief Indicates whether the transition error interrupt (TERRIE) is enabled. - * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides encoder error management. - * @rmtoll DIER TERRIE LL_TIM_IsEnabledIT_TERR - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable index error interrupt (IERRIE). - * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides encoder error management. - * @rmtoll DIER IERRIE LL_TIM_EnableIT_IERR - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_IERRIE); -} - -/** - * @brief Disable index error interrupt (IERRIE). - * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides encoder error management. - * @rmtoll DIER IERRIE LL_TIM_DisableIT_IERR - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE); -} - -/** - * @brief Indicates whether the index error interrupt (IERRIE) is enabled. - * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides encoder error management. - * @rmtoll DIER IERRIE LL_TIM_IsEnabledIT_IERR - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable direction change interrupt (DIRIE). - * @note Macro @ref IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides encoder interrupt management. - * @rmtoll DIER DIRIE LL_TIM_EnableIT_DIR - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_DIRIE); -} - -/** - * @brief Disable direction change interrupt (DIRIE). - * @note Macro @ref IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides encoder interrupt management. - * @rmtoll DIER DIRIE LL_TIM_DisableIT_DIR - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE); -} - -/** - * @brief Indicates whether the direction change interrupt (DIRIE) is enabled. - * @note Macro @ref IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides encoder interrupt management. - * @rmtoll DIER DIRIE LL_TIM_IsEnabledIT_DIR - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable index interrupt (IDXIE). - * @note Macro @ref IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides encoder interrupt management. - * @rmtoll DIER IDXIE LL_TIM_EnableIT_IDX - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_IDXIE); -} - -/** - * @brief Disable index interrupt (IDXIE). - * @note Macro @ref IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides encoder interrupt management. - * @rmtoll DIER IDXIE LL_TIM_DisableIT_IDX - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE); -} - -/** - * @brief Indicates whether the index interrupt (IDXIE) is enabled. - * @note Macro @ref IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides encoder interrupt management. - * @rmtoll DIER IDXIE LL_TIM_IsEnabledIT_IDX - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_DMA_Management DMA-Management - * @{ - */ -/** - * @brief Enable update DMA request (UDE). - * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_UDE); -} - -/** - * @brief Disable update DMA request (UDE). - * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); -} - -/** - * @brief Indicates whether the update DMA request (UDE) is enabled. - * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 1 DMA request (CC1DE). - * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); -} - -/** - * @brief Disable capture/compare 1 DMA request (CC1DE). - * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); -} - -/** - * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. - * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 2 DMA request (CC2DE). - * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); -} - -/** - * @brief Disable capture/compare 2 DMA request (CC2DE). - * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); -} - -/** - * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. - * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 3 DMA request (CC3DE). - * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); -} - -/** - * @brief Disable capture/compare 3 DMA request (CC3DE). - * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); -} - -/** - * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. - * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 4 DMA request (CC4DE). - * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); -} - -/** - * @brief Disable capture/compare 4 DMA request (CC4DE). - * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); -} - -/** - * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. - * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); -} - -/** - * @brief Enable commutation DMA request (COMDE). - * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_COMDE); -} - -/** - * @brief Disable commutation DMA request (COMDE). - * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); -} - -/** - * @brief Indicates whether the commutation DMA request (COMDE) is enabled. - * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); -} - -/** - * @brief Enable trigger interrupt (TDE). - * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_TDE); -} - -/** - * @brief Disable trigger interrupt (TDE). - * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); -} - -/** - * @brief Indicates whether the trigger interrupt (TDE) is enabled. - * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management - * @{ - */ -/** - * @brief Generate an update event. - * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_UG); -} - -/** - * @brief Generate Capture/Compare 1 event. - * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_CC1G); -} - -/** - * @brief Generate Capture/Compare 2 event. - * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_CC2G); -} - -/** - * @brief Generate Capture/Compare 3 event. - * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_CC3G); -} - -/** - * @brief Generate Capture/Compare 4 event. - * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_CC4G); -} - -/** - * @brief Generate commutation event. - * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_COMG); -} - -/** - * @brief Generate trigger event. - * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_TG); -} - -/** - * @brief Generate break event. - * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_BG); -} - -/** - * @brief Generate break 2 event. - * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_B2G); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions - * @{ - */ - -ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); -void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); -ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); -void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); -ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); -void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); -void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); -ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); -void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); -ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); -void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); -ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM15 || TIM16 || TIM17 || TIM20 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32G4xx_LL_TIM_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_ucpd.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_ucpd.h index 17f49eb..472dc93 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_ucpd.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_ucpd.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -53,24 +52,30 @@ extern "C" { */ typedef struct { - uint32_t psc_ucpdclk; /*!< Specifies the prescaler for the ucpd clock. + uint32_t psc_ucpdclk; /*!< Specify the prescaler for the UCPD clock. This parameter can be a value of @ref UCPD_LL_EC_PSC. - This feature can be modified afterwards using unitary function @ref LL_UCPD_SetPSCClk().*/ + This feature can be modified afterwards using function @ref LL_UCPD_SetPSCClk(). + */ - uint32_t transwin; /*!< Specifies the number of cycles (minus 1) of the half bit clock (see HBITCLKDIV) to achieve a legal - tTransitionWindow (set according to peripheral clock to define an interval of between 12 and 20 us). + uint32_t transwin; /*!< Specify the number of cycles (minus 1) of the half bit clock (see HBITCLKDIV) + to achieve a legal tTransitionWindow (set according to peripheral clock to define + an interval of between 12 and 20 us). This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F - This value can be modified afterwards using unitary function @ref LL_UCPD_SetTransWin().*/ + This value can be modified afterwards using function @ref LL_UCPD_SetTransWin(). + */ - uint32_t IfrGap; /*!< Specifies the definition of the clock divider (minus 1) in order to generate tInterframeGap - from the peripheral clock. + uint32_t IfrGap; /*!< Specify the definition of the clock divider (minus 1) in order to generate + tInterframeGap from the peripheral clock. This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F - This feature can be modified afterwards using unitary function @ref LL_UCPD_SetIfrGap().*/ + This feature can be modified afterwards using function @ref LL_UCPD_SetIfrGap(). + */ - uint32_t HbitClockDiv; /*!< Specifies the number of cycles (minus one) at UCPD peripheral for a half bit clock e.g. program 3 - for a bit clock that takes 8 cycles of the peripheral clock "UCPD1_CLK".. + uint32_t HbitClockDiv; /*!< Specify the number of cycles (minus one) at UCPD peripheral for a half bit clock + e.g. program 3 for a bit clock that takes 8 cycles of the peripheral clock : + "UCPD1_CLK". This parameter can be a value between Min_Data=0x0 and Max_Data=0x3F. - This feature can be modified afterwards using unitary function @ref LL_UCPD_SetHbitClockDiv().*/ + This feature can be modified using function @ref LL_UCPD_SetHbitClockDiv(). + */ } LL_UCPD_InitTypeDef; @@ -88,24 +93,24 @@ typedef struct * @brief Flags defines which can be used with LL_ucpd_ReadReg function * @{ */ -#define LL_UCPD_SR_TXIS UCPD_SR_TXIS /*!< Transmit interrupt status */ -#define LL_UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC /*!< Transmit message discarded interrupt */ -#define LL_UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT /*!< Transmit message sent interrupt */ -#define LL_UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT /*!< Transmit message abort interrupt */ -#define LL_UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC /*!< HRST discarded interrupt */ -#define LL_UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT /*!< HRST sent interrupt */ -#define LL_UCPD_SR_TXUND UCPD_SR_TXUND /*!< Tx data underrun condition interrupt */ -#define LL_UCPD_SR_RXNE UCPD_SR_RXNE /*!< Receive data register not empty interrupt */ -#define LL_UCPD_SR_RXORDDET UCPD_SR_RXORDDET /*!< Rx ordered set (4 K-codes) detected interrupt */ -#define LL_UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET /*!< Rx Hard Reset detect interrupt */ -#define LL_UCPD_SR_RXOVR UCPD_SR_RXOVR /*!< Rx data overflow interrupt */ -#define LL_UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND /*!< Rx message received */ -#define LL_UCPD_SR_RXERR UCPD_SR_RXERR /*!< Rx error */ -#define LL_UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1 /*!< Type C voltage level event on CC1 */ -#define LL_UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2 /*!< Type C voltage level event on CC2 */ -#define LL_UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1 /*!CFG1, UCPD_CFG1_UCPDEN) == (UCPD_CFG1_UCPDEN)) ? 1UL : 0UL); } @@ -670,7 +675,7 @@ __STATIC_INLINE void LL_UCPD_SetSRCRole(UCPD_TypeDef *UCPDx) * @arg @ref LL_UCPD_ROLE_SNK * @arg @ref LL_UCPD_ROLE_SRC */ -__STATIC_INLINE uint32_t LL_UCPD_GetRole(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_GetRole(UCPD_TypeDef const *const UCPDx) { return (uint32_t)(READ_BIT(UCPDx->CR, UCPD_CR_ANAMODE)); } @@ -1122,7 +1127,7 @@ __STATIC_INLINE void LL_UCPD_DisableIT_TxIS(UCPD_TypeDef *UCPDx) * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_FRS(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_FRS(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE) == UCPD_IMR_FRSEVTIE) ? 1UL : 0UL); } @@ -1133,7 +1138,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_FRS(UCPD_TypeDef const * const UCPDx * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC2(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC2(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE) == UCPD_IMR_TYPECEVT2IE) ? 1UL : 0UL); } @@ -1144,7 +1149,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC2(UCPD_TypeDef const * c * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC1(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC1(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE) == UCPD_IMR_TYPECEVT1IE) ? 1UL : 0UL); } @@ -1155,7 +1160,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC1(UCPD_TypeDef const * c * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxMsgEnd(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxMsgEnd(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE) == UCPD_IMR_RXMSGENDIE) ? 1UL : 0UL); } @@ -1166,7 +1171,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxMsgEnd(UCPD_TypeDef const * const * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE) == UCPD_IMR_RXOVRIE) ? 1UL : 0UL); } @@ -1177,7 +1182,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const * const UCP * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxHRST(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxHRST(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE) == UCPD_IMR_RXHRSTDETIE) ? 1UL : 0UL); } @@ -1188,7 +1193,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxHRST(UCPD_TypeDef const * const UC * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOrderSet(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOrderSet(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE) == UCPD_IMR_RXORDDETIE) ? 1UL : 0UL); } @@ -1199,7 +1204,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOrderSet(UCPD_TypeDef const * cons * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxNE(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxNE(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE) == UCPD_IMR_RXNEIE) ? 1UL : 0UL); } @@ -1210,7 +1215,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxNE(UCPD_TypeDef const * const UCPD * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxUND(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxUND(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE) == UCPD_IMR_TXUNDIE) ? 1UL : 0UL); } @@ -1221,7 +1226,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxUND(UCPD_TypeDef const * const UCP * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTSENT(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTSENT(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE) == UCPD_IMR_HRSTSENTIE) ? 1UL : 0UL); } @@ -1232,7 +1237,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTSENT(UCPD_TypeDef const * cons * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTDISC(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTDISC(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE) == UCPD_IMR_HRSTDISCIE) ? 1UL : 0UL); } @@ -1243,7 +1248,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTDISC(UCPD_TypeDef const * cons * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGABT(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGABT(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE) == UCPD_IMR_TXMSGABTIE) ? 1UL : 0UL); } @@ -1254,7 +1259,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGABT(UCPD_TypeDef const * const * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGSENT(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGSENT(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE) == UCPD_IMR_TXMSGSENTIE) ? 1UL : 0UL); } @@ -1265,7 +1270,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGSENT(UCPD_TypeDef const * const * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGDISC(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGDISC(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE) == UCPD_IMR_TXMSGDISCIE) ? 1UL : 0UL); } @@ -1276,7 +1281,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGDISC(UCPD_TypeDef const * const * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxIS(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxIS(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXISIE) == UCPD_IMR_TXISIE) ? 1UL : 0UL); } @@ -1288,6 +1293,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxIS(UCPD_TypeDef const * const UCPD /** @defgroup UCPD_LL_EF_IT_Clear Interrupt Clear * @{ */ + /** * @brief Clear FRS interrupt * @rmtoll ICR FRSEVTIE LL_UCPD_ClearFlag_FRS @@ -1445,7 +1451,7 @@ __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef *UCPDx) * @param UCPDx UCPD Instance * @retval None */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->SR, UCPD_SR_FRSEVT) == UCPD_SR_FRSEVT) ? 1UL : 0UL); } @@ -1456,7 +1462,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const * const UCP * @param UCPDx UCPD Instance * @retval None */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT2) == UCPD_SR_TYPECEVT2) ? 1UL : 0UL); } @@ -1467,7 +1473,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const * * @param UCPDx UCPD Instance * @retval None */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT1) == UCPD_SR_TYPECEVT1) ? 1UL : 0UL); } @@ -1478,7 +1484,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const * * @param UCPDx UCPD Instance * @retval None */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->SR, UCPD_SR_RXMSGEND) == UCPD_SR_RXMSGEND) ? 1UL : 0UL); } @@ -1489,7 +1495,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const * cons * @param UCPDx UCPD Instance * @retval None */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->SR, UCPD_SR_RXOVR) == UCPD_SR_RXOVR) ? 1UL : 0UL); } @@ -1500,7 +1506,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const * const U * @param UCPDx UCPD Instance * @retval None */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->SR, UCPD_SR_RXHRSTDET) == UCPD_SR_RXHRSTDET) ? 1UL : 0UL); } @@ -1511,7 +1517,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const * const * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->SR, UCPD_SR_RXORDDET) == UCPD_SR_RXORDDET) ? 1UL : 0UL); } @@ -1522,7 +1528,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const * co * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->SR, UCPD_SR_RXNE) == UCPD_SR_RXNE) ? 1UL : 0UL); } @@ -1533,7 +1539,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const * const UC * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->SR, UCPD_SR_TXUND) == UCPD_SR_TXUND) ? 1UL : 0UL); } @@ -1544,7 +1550,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const * const U * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTSENT) == UCPD_SR_HRSTSENT) ? 1UL : 0UL); } @@ -1555,7 +1561,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const * co * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTDISC) == UCPD_SR_HRSTDISC) ? 1UL : 0UL); } @@ -1566,7 +1572,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const * co * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGABT) == UCPD_SR_TXMSGABT) ? 1UL : 0UL); } @@ -1577,7 +1583,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const * cons * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGSENT) == UCPD_SR_TXMSGSENT) ? 1UL : 0UL); } @@ -1588,7 +1594,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const * con * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGDISC) == UCPD_SR_TXMSGDISC) ? 1UL : 0UL); } @@ -1599,7 +1605,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const * con * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxIS(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxIS(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->SR, UCPD_SR_TXIS) == UCPD_SR_TXIS) ? 1UL : 0UL); } @@ -1610,7 +1616,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxIS(UCPD_TypeDef const * const UC * @param UCPDx UCPD Instance * @retval val */ -__STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC2(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC2(UCPD_TypeDef const *const UCPDx) { return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC2; } @@ -1621,7 +1627,7 @@ __STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC2(UCPD_TypeDef const * const UC * @param UCPDx UCPD Instance * @retval val */ -__STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC1(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC1(UCPD_TypeDef const *const UCPDx) { return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC1; } @@ -1685,7 +1691,7 @@ __STATIC_INLINE void LL_UCPD_TxDMADisable(UCPD_TypeDef *UCPDx) * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnabledTxDMA(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsEnabledTxDMA(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN) == (UCPD_CFG1_TXDMAEN)) ? 1UL : 0UL); } @@ -1696,7 +1702,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnabledTxDMA(UCPD_TypeDef const * const UCPDx * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnabledRxDMA(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_IsEnabledRxDMA(UCPD_TypeDef const *const UCPDx) { return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN) == (UCPD_CFG1_RXDMAEN)) ? 1UL : 0UL); } @@ -1766,7 +1772,7 @@ __STATIC_INLINE void LL_UCPD_WriteData(UCPD_TypeDef *UCPDx, uint8_t Data) * @arg @ref LL_UCPD_RXORDSET_SOPEXT1 * @arg @ref LL_UCPD_RXORDSET_SOPEXT2 */ -__STATIC_INLINE uint32_t LL_UCPD_ReadRxOrderSet(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_ReadRxOrderSet(UCPD_TypeDef const *const UCPDx) { return READ_BIT(UCPDx->RX_ORDSET, UCPD_RX_ORDSET_RXORDSET); } @@ -1777,7 +1783,7 @@ __STATIC_INLINE uint32_t LL_UCPD_ReadRxOrderSet(UCPD_TypeDef const * const UCPDx * @param UCPDx UCPD Instance * @retval RXPaysize. */ -__STATIC_INLINE uint32_t LL_UCPD_ReadRxPaySize(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_ReadRxPaySize(UCPD_TypeDef const *const UCPDx) { return READ_BIT(UCPDx->TX_PAYSZ, UCPD_RX_PAYSZ_RXPAYSZ); } @@ -1788,7 +1794,7 @@ __STATIC_INLINE uint32_t LL_UCPD_ReadRxPaySize(UCPD_TypeDef const * const UCPDx) * @param UCPDx UCPD Instance * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_UCPD_ReadData(UCPD_TypeDef const * const UCPDx) +__STATIC_INLINE uint32_t LL_UCPD_ReadData(UCPD_TypeDef const *const UCPDx) { return READ_REG(UCPDx->RXDR); } @@ -1855,4 +1861,3 @@ void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct); #endif /* STM32G4xx_LL_UCPD_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h index 493e946..1675cc6 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -23,7 +22,7 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /* __cplusplus */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" @@ -60,12 +59,13 @@ typedef struct This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref USB_Core_Speed */ + This parameter can be any value of @ref PCD_Speed/HCD_Speed + (HCD_SPEED_xxx, HCD_SPEED_xxx) */ uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref USB_Core_PHY */ + This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ @@ -118,6 +118,10 @@ typedef struct uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ + uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */ + + uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */ + } USB_EPTypeDef; @@ -131,10 +135,10 @@ typedef struct /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ -#define DEP0CTL_MPS_64 0U -#define DEP0CTL_MPS_32 1U -#define DEP0CTL_MPS_16 2U -#define DEP0CTL_MPS_8 3U +#define EP_MPS_64 0U +#define EP_MPS_32 1U +#define EP_MPS_16 2U +#define EP_MPS_8 3U /** * @} */ @@ -151,10 +155,22 @@ typedef struct * @} */ +/** @defgroup USB_LL Device Speed + * @{ + */ +#define USBD_FS_SPEED 2U +/** + * @} + */ + #define BTABLE_ADDRESS 0x000U #define PMA_ACCESS 1U #define EP_ADDR_MSK 0x7U + +#ifndef USE_USB_DOUBLE_BUFFER +#define USE_USB_DOUBLE_BUFFER 1U +#endif /* USE_USB_DOUBLE_BUFFER */ /** * @} */ @@ -175,32 +191,28 @@ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg); HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx); HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode); -HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed); -HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx); -HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num); + +#if defined (HAL_PCD_MODULE_ENABLED) HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep); HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep); -HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len); -void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len); HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep); HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep); +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ + HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address); HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx); HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx); -HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup); uint32_t USB_ReadInterrupts(USB_TypeDef *USBx); -uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx); -uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum); -uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx); -uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum); -void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt); - HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx); -void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); -void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); + +void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, + uint16_t wPMABufAddr, uint16_t wNBytes); + +void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, + uint16_t wPMABufAddr, uint16_t wNBytes); /** * @} @@ -221,9 +233,7 @@ void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui #ifdef __cplusplus } -#endif +#endif /* __cplusplus */ #endif /* STM32G4xx_LL_USB_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h index ed6eb43..6a12eb7 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h @@ -3,6 +3,17 @@ * @file stm32g4xx_ll_utils.h * @author MCD Application Team * @brief Header file of UTILS LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -15,18 +26,6 @@ (+) PLL configuration functions @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -288,6 +287,7 @@ void LL_mDelay(uint32_t Delay); */ void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency); ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, @@ -315,4 +315,3 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa #endif /* STM32G4xx_LL_UTILS_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/LICENSE.txt b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/LICENSE.txt new file mode 100644 index 0000000..b40364c --- /dev/null +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the BSD-3-Clause license shall apply. +You may obtain a copy of the BSD-3-Clause at: +https://opensource.org/licenses/BSD-3-Clause diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c index 69785e3..3d9e92f 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c @@ -4,7 +4,17 @@ * @author MCD Application Team * @brief HAL module driver. * This is the common part of the HAL initialization + ****************************************************************************** + * @attention * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -19,17 +29,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -49,11 +48,11 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** - * @brief STM32G4xx HAL Driver version number $VERSION$ + * @brief STM32G4xx HAL Driver version number V1.2.2 */ #define __STM32G4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32G4xx_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ -#define __STM32G4xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32G4xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ +#define __STM32G4xx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */ #define __STM32G4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32G4xx_HAL_VERSION ((__STM32G4xx_HAL_VERSION_MAIN << 24U)\ |(__STM32G4xx_HAL_VERSION_SUB1 << 16U)\ @@ -347,19 +346,31 @@ uint32_t HAL_GetTickPrio(void) /** * @brief Set new tick Freq. - * @retval Status + * @retval status */ HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq) { HAL_StatusTypeDef status = HAL_OK; + uint32_t prevTickFreq; + assert_param(IS_TICKFREQ(Freq)); if (uwTickFreq != Freq) { + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ uwTickFreq = Freq; /* Apply the new tick Freq */ status = HAL_InitTick(uwTickPrio); + + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } } return status; @@ -759,4 +770,3 @@ void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c index 1fae7f6..47bfcbc 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c @@ -3,22 +3,25 @@ * @file stm32g4xx_hal_adc.c * @author MCD Application Team * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) + * functionalities of the Analog to Digital Converter (ADC) * peripheral: * + Initialization and de-initialization functions - * ++ Initialization and Configuration of ADC - * + Operation functions - * ++ Start, stop, get result of conversions of regular - * group, using 3 possible modes: polling, interruption or DMA. - * + Control functions - * ++ Channels configuration on regular group - * ++ Analog Watchdog configuration - * + State functions - * ++ ADC state machine management - * ++ Interrupts and flags management + * + Peripheral Control functions + * + Peripheral State functions * Other functions (extended functions) are available in file * "stm32g4xx_hal_adc_ex.c". * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### ADC peripheral features ##### @@ -219,11 +222,11 @@ The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_ADC_RegisterCallback() + Use Functions HAL_ADC_RegisterCallback() to register an interrupt callback. [..] - Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: + Function HAL_ADC_RegisterCallback() allows to register following callbacks: (+) ConvCpltCallback : ADC conversion complete callback (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback @@ -239,11 +242,11 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default + Use function HAL_ADC_UnRegisterCallback to reset a callback to the default weak function. [..] - @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) ConvCpltCallback : ADC conversion complete callback @@ -259,27 +262,27 @@ (+) MspDeInitCallback : ADC Msp DeInit callback [..] - By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET + By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). + examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when + reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when these callbacks are null (not registered beforehand). [..] - If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() + If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, + in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. [..] Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() - or @ref HAL_ADC_Init() function. + using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit() + or HAL_ADC_Init() function. [..] When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or @@ -288,17 +291,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -325,9 +317,8 @@ #define ADC_CFGR_FIELDS_1 ((ADC_CFGR_RES | ADC_CFGR_ALIGN |\ ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\ - ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated - when no regular conversion is on-going */ - + ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */ + /* Timeout values for ADC operations (enable settling time, */ /* disable settling time, ...). */ /* Values defined to be higher than worst cases: low clock frequency, */ @@ -501,7 +492,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; @@ -874,31 +865,28 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() ) */ ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc); - } - /* DeInit the low level hardware. - - For example: - __HAL_RCC_ADC_FORCE_RESET(); - __HAL_RCC_ADC_RELEASE_RESET(); - __HAL_RCC_ADC_CLK_DISABLE(); - - Keep in mind that all ADCs use the same clock: disabling - the clock will reset all ADCs. - - */ + /* ========== Hard reset ADC peripheral ========== */ + /* Performs a global reset of the entire ADC peripherals instances */ + /* sharing the same common ADC instance: ADC state is forced to */ + /* a similar state as after device power-on. */ + /* Note: A possible implementation is to add RCC bus reset of ADC */ + /* (for example, using macro */ + /* __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */ + /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - if (hadc->MspDeInitCallback == NULL) - { - hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ - } + if (hadc->MspDeInitCallback == NULL) + { + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + } - /* DeInit the low level hardware: RCC clock, NVIC */ - hadc->MspDeInitCallback(hadc); + /* DeInit the low level hardware */ + hadc->MspDeInitCallback(hadc); #else - /* DeInit the low level hardware: RCC clock, NVIC */ - HAL_ADC_MspDeInit(hadc); + /* DeInit the low level hardware */ + HAL_ADC_MspDeInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); @@ -973,7 +961,8 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, + pADC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -1499,13 +1488,17 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + /* Process unlocked */ + __HAL_UNLOCK(hadc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } } @@ -1615,13 +1608,17 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventTy { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + /* Process unlocked */ + __HAL_UNLOCK(hadc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } } @@ -2020,11 +2017,12 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui #if defined(ADC_MULTIMODE_SUPPORT) /* Ensure that multimode regular conversions are not enabled. */ /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */ - if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + if ((ADC_IS_INDEPENDENT(hadc) != RESET) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) ) -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ { /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); @@ -2158,7 +2156,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { - /* Disable ADC DMA (ADC DMA configuration of continous requests is kept) */ + /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); /* Disable the DMA channel (in case of DMA in circular mode or stop */ @@ -2404,7 +2402,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */ /* to determine if conversion has been triggered from EOC or EOS, */ /* possibility to use: */ - /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ + /* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else @@ -2459,44 +2457,46 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) /* group having no further conversion upcoming (same conditions as */ /* regular group interruption disabling above), */ /* and if injected scan sequence is completed. */ - if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) || - ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) && - ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && - (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))) + if (tmp_adc_inj_is_trigger_source_sw_start != 0UL) { - /* If End of Sequence is reached, disable interrupts */ - if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) + if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) || + ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && + (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))) { - /* Particular case if injected contexts queue is enabled: */ - /* when the last context has been fully processed, JSQR is reset */ - /* by the hardware. Even if no injected conversion is planned to come */ - /* (queue empty, triggers are ignored), it can start again */ - /* immediately after setting a new context (JADSTART is still set). */ - /* Therefore, state of HAL ADC injected group is kept to busy. */ - if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) + /* If End of Sequence is reached, disable interrupts */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) { - /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ - /* JADSTART==0 (no conversion on going) */ - if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) + /* Particular case if injected contexts queue is enabled: */ + /* when the last context has been fully processed, JSQR is reset */ + /* by the hardware. Even if no injected conversion is planned to come */ + /* (queue empty, triggers are ignored), it can start again */ + /* immediately after setting a new context (JADSTART is still set). */ + /* Therefore, state of HAL ADC injected group is kept to busy. */ + if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) { - /* Disable ADC end of sequence conversion interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); - - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - - if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) + /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ + /* JADSTART==0 (no conversion on going) */ + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* Disable ADC end of sequence conversion interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + + if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } } } } @@ -2504,8 +2504,8 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) /* Injected Conversion complete callback */ /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to - if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or - if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether + if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or + if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether interruption has been triggered by end of conversion or end of sequence. */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) @@ -2760,7 +2760,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpOffsetShifted; uint32_t tmp_config_internal_channel; - __IO uint32_t wait_loop_index = 0; + __IO uint32_t wait_loop_index = 0UL; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; @@ -2849,19 +2849,23 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf { /* Scan each offset register to check if the selected channel is targeted. */ /* If this is the case, the corresponding offset number is disabled. */ - if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); } - if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); } - if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); } - if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); } @@ -2913,7 +2917,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; @@ -2972,7 +2976,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_AnalogWDGConfTypeDef". - * @note On this STM32 serie, analog watchdog thresholds can be modified + * @note On this STM32 series, analog watchdog thresholds can be modified * while ADC conversion is on going. * In this case, some constraints must be taken into account: * the programmed threshold values are effective from the next @@ -3388,13 +3392,17 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t Conversio { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - return HAL_ERROR; + return HAL_ERROR; + } } } @@ -3404,8 +3412,6 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t Conversio return HAL_OK; } - - /** * @brief Enable the selected ADC. * @note Prerequisite condition to use this function: ADC must be disabled @@ -3424,7 +3430,8 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { /* Check if conditions to enable the ADC are fulfilled */ - if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) + if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART + | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); @@ -3458,13 +3465,17 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -3518,13 +3529,17 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -3665,5 +3680,3 @@ void ADC_DMAError(DMA_HandleTypeDef *hdma) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c index 1796ac6..c45adc4 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c @@ -3,22 +3,23 @@ * @file stm32g4xx_hal_adc_ex.c * @author MCD Application Team * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) + * functionalities of the Analog to Digital Converter (ADC) * peripheral: - * + Operation functions - * ++ Start, stop, get result of conversions of ADC group injected, - * using 2 possible modes: polling, interruption. - * ++ Calibration - * +++ ADC automatic self-calibration - * +++ Calibration factors get or set - * ++ Multimode feature when available - * + Control functions - * ++ Channels configuration on ADC group injected - * + State functions - * ++ ADC group injected contexts queue management + * + Peripheral Control functions * Other functions (generic functions) are available in file * "stm32g4xx_hal_adc.c". * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim [..] (@) Sections "ADC peripheral features" and "How to use this driver" are @@ -26,17 +27,6 @@ [..] @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -62,8 +52,7 @@ #define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\ ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\ - ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime - once the ADC is enabled */ + ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled */ /* Fixed timeout value for ADC calibration. */ /* Values defined to be higher than worst cases: low clock frequency, */ @@ -227,7 +216,8 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t Single * @param CalibrationFactor Calibration factor (coded on 7 bits maximum) * @retval HAL state */ -HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor) +HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, + uint32_t CalibrationFactor) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmp_adc_is_conversion_on_going_regular; @@ -523,13 +513,17 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, u { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + /* Process unlocked */ + __HAL_UNLOCK(hadc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } } @@ -885,6 +879,10 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t /* Process locked */ __HAL_LOCK(hadc); + /* Temporary handle minimum initialization */ + __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); + ADC_CLEAR_ERRORCODE(&tmphadcSlave); + /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); @@ -1000,6 +998,10 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { + /* Temporary handle minimum initialization */ + __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); + ADC_CLEAR_ERRORCODE(&tmphadcSlave); + /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); @@ -1027,13 +1029,20 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); + if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) + || (tmphadcSlave_conversion_on_going == 1UL) + ) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + /* Process unlocked */ + __HAL_UNLOCK(hadc); - return HAL_ERROR; + return HAL_ERROR; + } } tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); @@ -1484,6 +1493,10 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) /* Clear HAL_ADC_STATE_REG_BUSY bit */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + /* Temporary handle minimum initialization */ + __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); + ADC_CLEAR_ERRORCODE(&tmphadcSlave); + /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); @@ -1511,13 +1524,20 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); + if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) + || (tmphadcSlave_conversion_on_going == 1UL) + ) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + /* Process unlocked */ + __HAL_UNLOCK(hadc); - return HAL_ERROR; + return HAL_ERROR; + } } tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); @@ -1957,19 +1977,23 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I { /* Scan each offset register to check if the selected channel is targeted. */ /* If this is the case, the corresponding offset number is disabled. */ - if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); } - if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); } - if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); } - if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); } @@ -1990,7 +2014,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED) { /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel) + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime); + LL_ADC_SetChannelSamplingTime(hadc->Instance, + (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel) + + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime); } } @@ -2021,7 +2047,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (((SystemCoreClock / (100000UL * 2UL)) + 1UL) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; @@ -2080,7 +2106,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_ { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_Common_TypeDef *tmpADC_Common; - ADC_HandleTypeDef tmphadcSlave; + ADC_HandleTypeDef tmphadcSlave; uint32_t tmphadcSlave_conversion_on_going; /* Check the parameters */ @@ -2095,6 +2121,10 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_ /* Process locked */ __HAL_LOCK(hadc); + /* Temporary handle minimum initialization */ + __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); + ADC_CLEAR_ERRORCODE(&tmphadcSlave); + ADC_MULTI_SLAVE(hadc, &tmphadcSlave); if (tmphadcSlave.Instance == NULL) @@ -2341,5 +2371,3 @@ HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c index 05800d1..d53ee2c 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c @@ -8,6 +8,17 @@ * + Initialization and Configuration functions * + Peripheral Control functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -87,18 +98,6 @@ | | | 0 bit for subpriority ========================================================================================================================== - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -516,4 +515,3 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c index 52a084f..a96558e 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c @@ -8,6 +8,18 @@ * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -72,18 +84,6 @@ (@) You can refer to the DMA HAL driver header file for more useful macros @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -826,7 +826,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) * @brief Register callbacks * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param CallbackID User Callback identifer + * @param CallbackID User Callback identifier * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @param pCallback pointer to private callbacsk function which has pointer to * a DMA_HandleTypeDef structure as parameter. @@ -879,7 +879,7 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call * @brief UnRegister callbacks * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param CallbackID User Callback identifer + * @param CallbackID User Callback identifier * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @retval HAL status */ @@ -1057,7 +1057,7 @@ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) else { /* DMA2 */ -#if defined (STM32G474xx) || defined (STM32G473xx) || defined (STM32G471xx) || defined (STM32G484xx) +#if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G483xx) || defined (STM32G484xx) || defined (STM32G491xx) || defined (STM32G4A1xx) DMAMUX1_ChannelBase = DMAMUX1_Channel8; #elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB) DMAMUX1_ChannelBase = DMAMUX1_Channel6; @@ -1108,4 +1108,3 @@ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c index 701039b..cb44db8 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c @@ -7,6 +7,17 @@ * functionalities of the DMA Extension peripheral: * + Extended features functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -26,18 +37,6 @@ (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator) @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -297,4 +296,3 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c index 8094c9e..94af4cc 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c @@ -9,6 +9,17 @@ * + Initialization and de-initialization functions * + IO operation functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### EXTI Peripheral features ##### @@ -70,18 +81,6 @@ (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -317,6 +316,10 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT pExtiConfig->Mode |= EXTI_MODE_EVENT; } + /* Get default Trigger and GPIOSel configuration */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + /* 2] Get trigger for configurable lines : rising */ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) { @@ -328,10 +331,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT { pExtiConfig->Trigger = EXTI_TRIGGER_RISING; } - else - { - pExtiConfig->Trigger = EXTI_TRIGGER_NONE; - } /* Get falling configuration */ regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); @@ -351,15 +350,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT regval = SYSCFG->EXTICR[linepos >> 2u]; pExtiConfig->GPIOSel = ((regval >> (SYSCFG_EXTICR1_EXTI1_Pos * ((linepos & 0x03u))))); } - else - { - pExtiConfig->GPIOSel = 0x00u; - } - } - else - { - pExtiConfig->Trigger = EXTI_TRIGGER_NONE; - pExtiConfig->GPIOSel = 0x00u; } return HAL_OK; @@ -647,4 +637,3 @@ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c index bc84080..9139817 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c @@ -75,13 +75,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -767,4 +766,3 @@ static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c index 74c85bf..fd64b10 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c @@ -58,13 +58,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -157,9 +156,6 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /* Deactivate the cache if they are activated to avoid data misbehavior */ if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) { - /* Disable instruction cache */ - __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); - if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ @@ -253,9 +249,6 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) /* Deactivate the cache if they are activated to avoid data misbehavior */ if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) { - /* Disable instruction cache */ - __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); - if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ @@ -625,6 +618,8 @@ void FLASH_FlushCaches(void) if ((cache == FLASH_CACHE_ICACHE_ENABLED) || (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED)) { + /* Disable instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); /* Reset instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_RESET(); /* Enable instruction cache */ @@ -1417,4 +1412,3 @@ static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, u * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c index 38f6d79..f12a1a8 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c @@ -36,13 +36,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -130,7 +129,7 @@ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void) */ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig) { - register uint32_t count, reg; + uint32_t count, reg; HAL_StatusTypeDef status = HAL_ERROR; /* Process Locked */ @@ -250,6 +249,5 @@ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig) */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c index 532165f..b735929 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c @@ -8,6 +8,17 @@ * + Initialization and de-initialization functions * + IO operation functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### GPIO Peripheral features ##### @@ -89,17 +100,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -122,18 +122,10 @@ #ifdef HAL_GPIO_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ -/* Private defines ------------------------------------------------------------*/ -/** @defgroup GPIO_Private_Constants GPIO Private Constants +/* Private defines -----------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Constants GPIO Private Constants * @{ */ -#define GPIO_MODE (0x00000003U) -#define EXTI_MODE (0x10000000U) -#define GPIO_MODE_IT (0x00010000U) -#define GPIO_MODE_EVT (0x00020000U) -#define RISING_EDGE (0x00100000U) -#define FALLING_EDGE (0x00200000U) -#define GPIO_OUTPUT_TYPE (0x00000010U) - #define GPIO_NUMBER (16U) /** * @} @@ -177,7 +169,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); - assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0U) @@ -188,8 +179,39 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) if (iocurrent != 0x00u) { /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + temp |= (GPIO_Init->Speed << (position * 2U)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + temp &= ~(GPIO_OTYPER_OT0 << position) ; + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + GPIOx->OTYPER = temp; + } + + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + temp |= ((GPIO_Init->Pull) << (position * 2U)); + GPIOx->PUPDR = temp; + } + /* In case of Alternate function mode selection */ - if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); @@ -208,34 +230,9 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); GPIOx->MODER = temp; - /* In case of Output or Alternate function mode selection */ - if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || - (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Speed parameter */ - assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); - /* Configure the IO Speed */ - temp = GPIOx->OSPEEDR; - temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); - temp |= (GPIO_Init->Speed << (position * 2U)); - GPIOx->OSPEEDR = temp; - - /* Configure the IO Output Type */ - temp = GPIOx->OTYPER; - temp &= ~(GPIO_OTYPER_OT0 << position) ; - temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); - GPIOx->OTYPER = temp; - } - - /* Activate the Pull-up or Pull down resistor for the current IO */ - temp = GPIOx->PUPDR; - temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); - temp |= ((GPIO_Init->Pull) << (position * 2U)); - GPIOx->PUPDR = temp; - /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ - if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); @@ -245,27 +242,10 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); SYSCFG->EXTICR[position >> 2U] = temp; - /* Clear EXTI line configuration */ - temp = EXTI->IMR1; - temp &= ~(iocurrent); - if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) - { - temp |= iocurrent; - } - EXTI->IMR1 = temp; - - temp = EXTI->EMR1; - temp &= ~(iocurrent); - if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) - { - temp |= iocurrent; - } - EXTI->EMR1 = temp; - /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; temp &= ~(iocurrent); - if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) { temp |= iocurrent; } @@ -273,11 +253,28 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp = EXTI->FTSR1; temp &= ~(iocurrent); - if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) { temp |= iocurrent; } EXTI->FTSR1 = temp; + + temp = EXTI->EMR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) + { + temp |= iocurrent; + } + EXTI->EMR1 = temp; + + /* Clear EXTI line configuration */ + temp = EXTI->IMR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) + { + temp |= iocurrent; + } + EXTI->IMR1 = temp; } } @@ -317,16 +314,16 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) tmp &= (0x0FUL << (4U * (position & 0x03U))); if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) { - tmp = 0x0FUL << (4U * (position & 0x03U)); - SYSCFG->EXTICR[position >> 2U] &= ~tmp; - /* Clear EXTI line configuration */ EXTI->IMR1 &= ~(iocurrent); EXTI->EMR1 &= ~(iocurrent); /* Clear Rising Falling edge configuration */ - EXTI->RTSR1 &= ~(iocurrent); EXTI->FTSR1 &= ~(iocurrent); + EXTI->RTSR1 &= ~(iocurrent); + + tmp = 0x0FUL << (4U * (position & 0x03U)); + SYSCFG->EXTICR[position >> 2U] &= ~tmp; } /*------------------------- GPIO Mode Configuration --------------------*/ @@ -334,16 +331,16 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u)); /* Configure the default Alternate Function in current IO */ - GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ; - - /* Configure the default value for IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); - - /* Configure the default value IO Output Type */ - GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; + GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)); /* Deactivate the Pull-up and Pull-down resistor for the current IO */ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position); + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); } position++; @@ -432,17 +429,16 @@ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { + uint32_t odr; + /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); - if ((GPIOx->ODR & GPIO_Pin) != 0x00u) - { - GPIOx->BRR = (uint32_t)GPIO_Pin; - } - else - { - GPIOx->BSRR = (uint32_t)GPIO_Pin; - } + /* get current Output Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); } /** @@ -534,4 +530,3 @@ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c index 9b22628..54c8246 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c @@ -9,6 +9,17 @@ * + IO operation functions * + Peripheral State and Errors functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -19,7 +30,7 @@ (#) Declare a I2C_HandleTypeDef handle structure, for example: I2C_HandleTypeDef hi2c; - (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API: + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: (##) Enable the I2Cx interface clock (##) I2C pins configuration (+++) Enable the clock for the I2C GPIOs @@ -28,7 +39,8 @@ (+++) Configure the I2Cx interrupt priority (+++) Enable the NVIC I2C IRQ Channel (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel + (+++) Declare a DMA_HandleTypeDef handle structure for + the transmit or receive channel (+++) Enable the DMAx interface clock using (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx channel @@ -39,49 +51,49 @@ (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. - (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API. + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. - (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady() + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : *** Polling mode IO operation *** ================================= [..] - (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit() - (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive() - (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit() - (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive() + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() *** Polling mode IO MEM operation *** ===================================== [..] - (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write() - (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read() + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() *** Interrupt mode IO operation *** =================================== [..] - (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT() - (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT() - (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT() - (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT() - (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() - (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. @@ -92,120 +104,135 @@ when a direction change during transfer [..] (+) A specific option field manage the different steps of a sequential transfer - (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: - (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode + (+) Option field values are defined through I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in + no sequential mode (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition - (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address - and data to transfer without a final stop condition, an then permit a call the same master sequential interface - several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT() - or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA()) + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with + start condition, address and data to transfer without a final stop condition, + an then permit a call the same master sequential interface several times + (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT() + or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA()) (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer + and with new data to transfer if the direction change or manage only the new data to + transfer if no direction change and without a final stop condition in both cases (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer + and with new data to transfer if the direction change or manage only the new data to + transfer if no direction change and with a final stop condition in both cases - (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential - interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). - Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) - or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) - or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) - or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). - Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition + after several call of the same master sequential interface several times + (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME. + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or + Receive sequence permit to call the opposite interface Receive or Transmit without stopping the communication and so generate a restart condition. - (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential + (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after + each call of the same master sequential interface. - Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) - or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) - or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) - or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). - Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. + Usage can, transfer several bytes one by one with a restart with slave address between + each bytes using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_FRAME then I2C_OTHER_FRAME. + Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic + generation of STOP condition. - (+) Differents sequential I2C interfaces are listed below: - (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT() - or using @ref HAL_I2C_Master_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() - (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT() - or using @ref HAL_I2C_Master_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() - (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() - (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() - (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT() - (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can - add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). - (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback() - (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT() - or using @ref HAL_I2C_Slave_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() - (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT() - or using @ref HAL_I2C_Slave_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() - (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() - (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + (+) Different sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() + HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction request by master + (Write/Read). + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. *** Interrupt mode IO MEM operation *** ======================================= [..] (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using - @ref HAL_I2C_Mem_Write_IT() - (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using - @ref HAL_I2C_Mem_Read_IT() - (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() *** DMA mode IO operation *** ============================== [..] (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Master_Transmit_DMA() - (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() (+) Receive in master mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Master_Receive_DMA() - (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Slave_Transmit_DMA() - (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Slave_Receive_DMA() - (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() - (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. *** DMA mode IO MEM operation *** ================================= [..] (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using - @ref HAL_I2C_Mem_Write_DMA() - (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using - @ref HAL_I2C_Mem_Read_DMA() - (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() *** I2C HAL driver macros list *** @@ -213,23 +240,23 @@ [..] Below the list of most used macros in I2C HAL driver. - (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral - (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral - (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode - (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not - (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag - (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt - (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt *** Callback registration *** ============================================= - + [..] The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() + Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() to register an interrupt callback. - - Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: + [..] + Function HAL_I2C_RegisterCallback() allows to register following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer. (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. @@ -243,12 +270,12 @@ (+) MspDeInitCallback : callback for Msp DeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - - For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback(). - - Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default + [..] + For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback(). + [..] + Use function HAL_I2C_UnRegisterCallback to reset a callback to the default weak function. - @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. @@ -262,26 +289,26 @@ (+) AbortCpltCallback : callback for abort completion process. (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. - - For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback(). - - By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET + [..] + For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). + [..] + By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). + examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when + reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() + If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. - - Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. + [..] + Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, + in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() - or @ref HAL_I2C_Init() function. - + using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() + or HAL_I2C_Init() function. + [..] When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @@ -290,18 +317,6 @@ (@) You can refer to the I2C HAL driver header file for more useful macros @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -336,28 +351,48 @@ #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ #define MAX_NBYTE_SIZE 255U -#define SlaveAddr_SHIFT 7U -#define SlaveAddr_MSK 0x06U +#define SLAVE_ADDR_SHIFT 7U +#define SLAVE_ADDR_MSK 0x06U /* Private define for @ref PreviousState usage */ -#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ -#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ -#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \ + (uint32_t)HAL_I2C_STATE_BUSY_RX) & \ + (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) +/*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) +/*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy RX, combinaison of State LSB and Mode enum */ /* Private define to centralize the enable/disable of Interrupts */ -#define I2C_XFER_TX_IT (0x00000001U) -#define I2C_XFER_RX_IT (0x00000002U) -#define I2C_XFER_LISTEN_IT (0x00000004U) +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT + and @ref I2C_XFER_RX_IT */ -#define I2C_XFER_ERROR_IT (0x00000011U) -#define I2C_XFER_CPLT_IT (0x00000012U) -#define I2C_XFER_RELOAD_IT (0x00000012U) +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error + and NACK treatment */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */ /* Private define Sequential Transfer Options default/reset value */ #define I2C_NO_OPTION_FRAME (0xFFFF0000U) @@ -366,6 +401,9 @@ */ /* Private macro -------------------------------------------------------------*/ +/* Macro to get remaining data to transfer on DMA side */ +#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__) + /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -390,31 +428,48 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); /* Private functions to handle IT transfer */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); /* Private functions for I2C transfer IRQ handler */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); /* Private functions to handle flags during polling transfer */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); /* Private functions to centralize the enable/disable of Interrupts */ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +/* Private function to treat different error callback */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + /* Private function to flush TXDR register */ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); /* Private function to handle start, restart or stop a transfer */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request); /* Private function to Convert Specific options */ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); @@ -429,8 +484,8 @@ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); */ /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -552,7 +607,8 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; /* Configure I2Cx: Dual mode and Own Address2 */ - hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8)); + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + (hi2c->Init.OwnAddress2Masks << 8)); /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ @@ -669,7 +725,8 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -974,8 +1031,8 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) */ /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -1057,7 +1114,8 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -1088,12 +1146,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_WRITE); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); } while (hi2c->XferCount > 0U) @@ -1123,12 +1183,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); } } } @@ -1171,7 +1233,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -1202,12 +1265,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); } while (hi2c->XferCount > 0U) @@ -1238,12 +1303,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); } } } @@ -1284,7 +1351,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; @@ -1366,22 +1434,27 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->XferCount--; } + /* Wait until AF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + /* Wait until STOP flag is set */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Normal use case for Transmitter mode */ - /* A NACK is generated to confirm the end of transfer */ - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } - else - { - return HAL_ERROR; - } + return HAL_ERROR; } /* Clear STOP flag */ @@ -1421,7 +1494,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; @@ -1445,6 +1519,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; hi2c->XferISR = NULL; /* Enable Address Acknowledge */ @@ -1487,6 +1562,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, hi2c->pBuffPtr++; hi2c->XferCount--; + hi2c->XferSize--; } return HAL_ERROR; @@ -1499,6 +1575,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, hi2c->pBuffPtr++; hi2c->XferCount--; + hi2c->XferSize--; } /* Wait until STOP flag is set */ @@ -1547,7 +1624,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) { uint32_t xfermode; @@ -1595,7 +1673,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; @@ -1616,7 +1695,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) { uint32_t xfermode; @@ -1664,7 +1744,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); return HAL_OK; @@ -1713,7 +1794,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); return HAL_OK; @@ -1762,7 +1844,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); return HAL_OK; @@ -1783,7 +1866,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) { uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; @@ -1834,7 +1918,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); } else { @@ -1894,7 +1979,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1904,7 +1990,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } @@ -1926,7 +2013,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) { uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; @@ -1977,7 +2065,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); } else { @@ -2037,7 +2126,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2047,7 +2137,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } @@ -2105,7 +2196,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); } else { @@ -2208,7 +2300,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); } else { @@ -2277,7 +2370,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -2360,17 +2454,18 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); } } - } - while (hi2c->XferCount > 0U); + } while (hi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ @@ -2412,7 +2507,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -2460,12 +2556,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); } do @@ -2496,16 +2594,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); } } - } - while (hi2c->XferCount > 0U); + } while (hi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ @@ -2545,7 +2644,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; @@ -2594,7 +2694,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) + != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2613,7 +2714,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; @@ -2636,7 +2738,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; @@ -2704,7 +2807,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); return HAL_OK; @@ -2726,7 +2830,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; @@ -2776,7 +2881,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd } /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) + != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2797,7 +2903,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); } else { @@ -2870,7 +2977,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd * @param Size Amount of data to be read * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; @@ -2940,7 +3048,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); } else { @@ -3011,7 +3120,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout) { uint32_t tickstart; @@ -3121,8 +3231,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Increment Trials */ I2C_Trials++; - } - while (I2C_Trials < Trials); + } while (I2C_Trials < Trials); /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; @@ -3153,7 +3262,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_WRITE; @@ -3188,9 +3298,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 xfermode = hi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3200,7 +3312,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3237,7 +3349,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_WRITE; @@ -3273,9 +3386,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 xfermode = hi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3285,7 +3400,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3306,7 +3421,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); } else { @@ -3365,7 +3481,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3375,7 +3492,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } @@ -3399,7 +3517,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_READ; @@ -3434,9 +3553,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_ xfermode = hi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3446,7 +3567,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_ I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3483,7 +3604,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_READ; @@ -3519,9 +3641,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 xfermode = hi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3531,7 +3655,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3552,7 +3676,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); } else { @@ -3611,7 +3736,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3621,7 +3747,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } @@ -3643,7 +3770,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3738,7 +3866,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { HAL_StatusTypeDef dmaxferstatus; @@ -3840,7 +3969,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); } else { @@ -3890,15 +4020,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ /* Process Unlocked */ __HAL_UNLOCK(hi2c); + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR, STOP, NACK, ADDR interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - return HAL_OK; } else @@ -3917,7 +4047,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -4012,7 +4143,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { HAL_StatusTypeDef dmaxferstatus; @@ -4114,7 +4246,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, + (uint32_t)pData, hi2c->XferSize); } else { @@ -4164,15 +4297,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t /* Process Unlocked */ __HAL_UNLOCK(hi2c); + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* REnable ADDR interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - return HAL_OK; } else @@ -4251,9 +4384,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Process Locked */ __HAL_LOCK(hi2c); - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } /* Set State at HAL_I2C_STATE_ABORT */ hi2c->State = HAL_I2C_STATE_ABORT; @@ -4285,8 +4430,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA */ /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ + * @{ + */ /** * @brief This function handles I2C event interrupt request. @@ -4320,7 +4465,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) uint32_t tmperror; /* I2C Bus error interrupt occurred ------------------------------------*/ - if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; @@ -4329,7 +4475,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; @@ -4338,7 +4485,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; @@ -4524,8 +4672,8 @@ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) */ /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions - * @brief Peripheral State, Mode and Error functions - * + * @brief Peripheral State, Mode and Error functions + * @verbatim =============================================================================== ##### Peripheral State, Mode and Error functions ##### @@ -4562,11 +4710,11 @@ HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) } /** -* @brief Return the I2C error code. + * @brief Return the I2C error code. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. -* @retval I2C Error Code -*/ + * @retval I2C Error Code + */ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) { return hi2c->ErrorCode; @@ -4592,7 +4740,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) { uint16_t devaddress; uint32_t tmpITFlags = ITFlags; @@ -4600,7 +4749,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Process Locked */ __HAL_LOCK(hi2c); - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -4613,7 +4763,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) { /* Remove RXNE flag on temporary variable as read done */ tmpITFlags &= ~I2C_FLAG_RXNE; @@ -4627,7 +4778,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin hi2c->XferSize--; hi2c->XferCount--; } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) { /* Write data to TXDR */ hi2c->Instance->TXDR = *hi2c->pBuffPtr; @@ -4638,7 +4790,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin hi2c->XferSize--; hi2c->XferCount--; } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) { @@ -4654,11 +4807,13 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin hi2c->XferSize = hi2c->XferCount; if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { - I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + hi2c->XferOptions, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } } @@ -4678,7 +4833,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin } } } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { if (hi2c->XferCount == 0U) { @@ -4709,7 +4865,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Nothing to do */ } - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, tmpITFlags); @@ -4729,7 +4886,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) { uint32_t tmpoptions = hi2c->XferOptions; uint32_t tmpITFlags = ITFlags; @@ -4737,7 +4895,16 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* Process locked */ __HAL_LOCK(hi2c); - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, tmpITFlags); + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -4745,7 +4912,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* So clear Flag NACKF only */ if (hi2c->XferCount == 0U) { - if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); @@ -4784,13 +4953,11 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint } } } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) { if (hi2c->XferCount > 0U) { - /* Remove RXNE flag on temporary variable as read done */ - tmpITFlags &= ~I2C_FLAG_RXNE; - /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; @@ -4808,15 +4975,17 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint I2C_ITSlaveSeqCplt(hi2c); } } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) { I2C_ITAddrCplt(hi2c, tmpITFlags); } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ - /* Check if all Datas have already been sent */ + /* Check if all Data have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ if (hi2c->XferCount > 0U) { @@ -4844,13 +5013,6 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* Nothing to do */ } - /* Check if STOPF is set */ - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) - { - /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, tmpITFlags); - } - /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -4865,7 +5027,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) { uint16_t devaddress; uint32_t xfermode; @@ -4873,7 +5036,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Process Locked */ __HAL_LOCK(hi2c); - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -4889,7 +5053,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { /* Disable TC interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); @@ -4950,7 +5115,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui } } } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { if (hi2c->XferCount == 0U) { @@ -4976,7 +5142,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); } } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); @@ -5000,15 +5167,26 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) { uint32_t tmpoptions = hi2c->XferOptions; uint32_t treatdmanack = 0U; + HAL_I2C_StateTypeDef tmpstate; /* Process locked */ __HAL_LOCK(hi2c); - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); + } + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -5022,7 +5200,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin { if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) { - if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) { treatdmanack = 1U; } @@ -5034,7 +5212,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin { if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) { - if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U) + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) { treatdmanack = 1U; } @@ -5043,7 +5221,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin if (treatdmanack == 1U) { - if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); @@ -5075,8 +5255,24 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ + tmpstate = hi2c->State; + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) { + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); } @@ -5088,15 +5284,11 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); } } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) { I2C_ITAddrCplt(hi2c, ITFlags); } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) - { - /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, ITFlags); - } else { /* Nothing to do */ @@ -5120,7 +5312,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) { I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); @@ -5173,7 +5367,9 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) { I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); @@ -5241,7 +5437,7 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* If 10bits addressing mode is selected */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { - if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) + if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) { slaveaddrcode = ownadd1code; hi2c->AddrEventCount++; @@ -5370,9 +5566,27 @@ static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) */ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) { + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + else + { + /* Do nothing */ + } + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ @@ -5427,19 +5641,36 @@ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmperror; + uint32_t tmpITFlags = ITFlags; + __IO uint32_t tmpreg; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); /* Reset handle parameters */ - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = NULL; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -5448,12 +5679,17 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } + /* Fetch Last receive data if any */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + tmpreg = (uint8_t)hi2c->Instance->RXDR; + UNUSED(tmpreg); + } + /* Flush TX register */ I2C_Flush_TXDR(hi2c); - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); - /* Store current volatile hi2c->ErrorCode, misra rule */ tmperror = hi2c->ErrorCode; @@ -5467,6 +5703,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; if (hi2c->Mode == HAL_I2C_MODE_MEM) { @@ -5501,6 +5738,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; if (hi2c->Mode == HAL_I2C_MODE_MEM) { @@ -5547,12 +5785,26 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); uint32_t tmpITFlags = ITFlags; + HAL_I2C_StateTypeDef tmpstate = hi2c->State; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Disable all interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + /* Disable Interrupts and Store Previous state */ + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -5566,16 +5818,22 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + if (hi2c->hdmatx != NULL) { - hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx); + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx); } } else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + if (hi2c->hdmarx != NULL) { - hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx); + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx); } } else @@ -5609,7 +5867,6 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } - hi2c->PreviousState = I2C_STATE_NONE; hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; @@ -5627,11 +5884,12 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) } else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { - /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */ + /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */ I2C_ITSlaveSeqCplt(hi2c); hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5647,6 +5905,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5661,6 +5920,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5734,6 +5994,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { HAL_I2C_StateTypeDef tmpstate = hi2c->State; + uint32_t tmppreviousstate; /* Reset handle parameters */ hi2c->Mode = HAL_I2C_MODE_NONE; @@ -5753,7 +6014,6 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* keep HAL_I2C_STATE_LISTEN if set */ hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = I2C_Slave_ISR_IT; } else @@ -5761,23 +6021,27 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - /* If state is an abort treatment on goind, don't change state */ + /* If state is an abort treatment on going, don't change state */ /* This change will be do later */ if (hi2c->State != HAL_I2C_STATE_ABORT) { /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; } - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = NULL; } /* Abort DMA TX transfer if any */ - if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + tmppreviousstate = hi2c->PreviousState; + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) { - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } - if (hi2c->hdmatx != NULL) + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ @@ -5793,13 +6057,21 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); } } + else + { + I2C_TreatErrorCallback(hi2c); + } } /* Abort DMA RX transfer if any */ - else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) { - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } - if (hi2c->hdmarx != NULL) + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ @@ -5815,10 +6087,28 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); } } + else + { + I2C_TreatErrorCallback(hi2c); + } } - else if (hi2c->State == HAL_I2C_STATE_ABORT) + else + { + I2C_TreatErrorCallback(hi2c); + } +} + +/** + * @brief I2C Error callback treatment. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_ABORT) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5832,6 +6122,8 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) } else { + hi2c->PreviousState = I2C_STATE_NONE; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5872,7 +6164,8 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; @@ -5900,7 +6193,8 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) } /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK) + if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize) != HAL_OK) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); @@ -5920,7 +6214,8 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tmpoptions = hi2c->XferOptions; if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) @@ -5947,7 +6242,8 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; @@ -5975,7 +6271,8 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) } /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK) + if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, + hi2c->XferSize) != HAL_OK) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); @@ -5995,10 +6292,11 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tmpoptions = hi2c->XferOptions; - if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \ + if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \ (tmpoptions != I2C_NO_OPTION_FRAME)) { /* Disable DMA Request */ @@ -6022,7 +6320,8 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMAError(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -6039,46 +6338,35 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) */ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Reset AbortCpltCallback */ - hi2c->hdmatx->XferAbortCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Check if come from abort from user */ - if (hi2c->State == HAL_I2C_STATE_ABORT) + if (hi2c->hdmatx != NULL) { - hi2c->State = HAL_I2C_STATE_READY; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->AbortCpltCallback(hi2c); -#else - HAL_I2C_AbortCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + hi2c->hdmatx->XferAbortCallback = NULL; } - else + if (hi2c->hdmarx != NULL) { - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->ErrorCallback(hi2c); -#else - HAL_I2C_ErrorCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + hi2c->hdmarx->XferAbortCallback = NULL; } + + I2C_TreatErrorCallback(hi2c); } /** - * @brief This function handles I2C Communication Timeout. + * @brief This function handles I2C Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param Flag Specifies the I2C flag to check. - * @param Status The new Flag status (SET or RESET). + * @param Status The actual Flag status (SET or RESET). * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { @@ -6108,12 +6396,13 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -6145,12 +6434,13 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -6179,12 +6469,13 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -6202,13 +6493,22 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, } else { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + } + else + { + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; @@ -6235,60 +6535,136 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, } /** - * @brief This function handles Acknowledge failed detection during an I2C Communication. + * @brief This function handles errors detection during an I2C Communication. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + HAL_StatusTypeDef status = HAL_OK; + uint32_t itflag = hi2c->Instance->ISR; + uint32_t error_code = 0; + uint32_t tickstart = Tickstart; + uint32_t tmp1; + HAL_I2C_ModeTypeDef tmp2; + + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF)) { - /* Wait until STOP Flag is reset */ + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until STOP Flag is set or timeout occurred */ /* AutoEnd should be initiate after AF */ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP); + tmp2 = hi2c->Mode; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + /* In case of I2C still busy, try to regenerate a STOP manually */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \ + (tmp1 != I2C_CR2_STOP) && \ + (tmp2 != HAL_I2C_MODE_SLAVE)) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + + /* Update Tick with new reference */ + tickstart = HAL_GetTick(); + } + + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + status = HAL_ERROR; + } + } } } } - /* Clear NACKF Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + /* In case STOP Flag is detected, clear it */ + if (status == HAL_OK) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + error_code |= HAL_I2C_ERROR_AF; + status = HAL_ERROR; + } + + /* Refresh Content of Status register */ + itflag = hi2c->Instance->ISR; + + /* Then verify if an additional errors occurs */ + /* Check if a Bus error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR)) + { + error_code |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + + status = HAL_ERROR; + } + + /* Check if an Over-Run/Under-Run error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR)) + { + error_code |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + + status = HAL_ERROR; + } + + /* Check if an Arbitration Loss error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO)) + { + error_code |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + + status = HAL_ERROR; + } + + if (status != HAL_OK) + { /* Flush TX register */ I2C_Flush_TXDR(hi2c); /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + hi2c->ErrorCode |= error_code; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); - - return HAL_ERROR; } - return HAL_OK; + + return status; } /** @@ -6310,16 +6686,24 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request) { /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + /* update CR2 register */ - MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \ - (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); + MODIFY_REG(hi2c->Instance->CR2, \ + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP)), tmp); } /** @@ -6342,19 +6726,19 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if (InterruptRequest == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); } - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + if (InterruptRequest == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; @@ -6380,7 +6764,7 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; @@ -6434,19 +6818,19 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if (InterruptRequest == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + if (InterruptRequest == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; @@ -6459,7 +6843,7 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) } /** - * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions. + * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. * @param hi2c I2C handle. * @retval None */ @@ -6498,5 +6882,3 @@ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c index b388a0f..b2e51cf 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c @@ -5,8 +5,21 @@ * @brief I2C Extended HAL module driver. * This file provides firmware functions to manage the following * functionalities of I2C Extended peripheral: - * + Extended features functions + * + Filter Mode Functions + * + WakeUp Mode Functions + * + FastModePlus Functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### I2C peripheral Extended features ##### @@ -32,18 +45,6 @@ (++) HAL_I2CEx_EnableFastModePlus() (++) HAL_I2CEx_DisableFastModePlus() @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -71,17 +72,15 @@ * @{ */ -/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * +/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @brief Filter Mode Functions + * @verbatim =============================================================================== - ##### Extended features functions ##### + ##### Filter Mode Functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure Noise Filters - (+) Configure Wake Up Feature - (+) Configure Fast Mode Plus @endverbatim * @{ @@ -182,6 +181,23 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ return HAL_BUSY; } } +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @brief WakeUp Mode Functions + * +@verbatim + =============================================================================== + ##### WakeUp Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Wake Up Feature + +@endverbatim + * @{ + */ /** * @brief Enable I2C wakeup from Stop mode(s). @@ -260,6 +276,23 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) return HAL_BUSY; } } +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions + * +@verbatim + =============================================================================== + ##### Fast Mode Plus Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ /** * @brief Enable the I2C fast mode plus driving capability. @@ -318,11 +351,9 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) /* Disable fast mode plus driving capability for selected pin */ CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); } - /** * @} */ - /** * @} */ @@ -335,5 +366,3 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c index eaf20a7..4bc9bef 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -40,17 +51,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -88,6 +88,10 @@ */ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); +#if (USE_USB_DOUBLE_BUFFER == 1U) +static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal); +static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal); +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ /** * @} @@ -99,8 +103,8 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); */ /** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -198,13 +202,13 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->USB_Address = 0U; hpcd->State = HAL_PCD_STATE_READY; - + /* Activate LPM */ if (hpcd->Init.lpm_enable == 1U) { (void)HAL_PCDEx_ActivateLPM(hpcd); } - + return HAL_OK; } @@ -224,7 +228,10 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) hpcd->State = HAL_PCD_STATE_BUSY; /* Stop Device */ - (void)HAL_PCD_Stop(hpcd); + if (USB_StopDevice(hpcd->Instance) != HAL_OK) + { + return HAL_ERROR; + } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) if (hpcd->MspDeInitCallback == NULL) @@ -293,7 +300,9 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, + HAL_PCD_CallbackIDTypeDef CallbackID, + pPCD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -503,7 +512,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_Ca * @param pCallback pointer to the USB PCD Data OUT Stage Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataOutStageCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -538,7 +548,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, } /** - * @brief UnRegister the USB PCD Data OUT Stage Callback + * @brief Unregister the USB PCD Data OUT Stage Callback * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -576,7 +586,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd * @param pCallback pointer to the USB PCD Data IN Stage Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataInStageCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -611,7 +622,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, p } /** - * @brief UnRegister the USB PCD Data IN Stage Callback + * @brief Unregister the USB PCD Data IN Stage Callback * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -649,7 +660,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) * @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoOutIncpltCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -684,8 +696,9 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, } /** - * @brief UnRegister the USB PCD Iso OUT incomplete Callback - * USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback + * @brief Unregister the USB PCD Iso OUT incomplete Callback + * USB PCD Iso OUT incomplete Callback is redirected + * to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback * @param hpcd PCD handle * @retval HAL status */ @@ -722,7 +735,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd * @param pCallback pointer to the USB PCD Iso IN incomplete Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoInIncpltCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -757,8 +771,9 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, p } /** - * @brief UnRegister the USB PCD Iso IN incomplete Callback - * USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback + * @brief Unregister the USB PCD Iso IN incomplete Callback + * USB PCD Iso IN incomplete Callback is redirected + * to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback * @param hpcd PCD handle * @retval HAL status */ @@ -830,7 +845,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdC } /** - * @brief UnRegister the USB PCD BCD Callback + * @brief Unregister the USB PCD BCD Callback * USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -903,7 +918,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmC } /** - * @brief UnRegister the USB PCD LPM Callback + * @brief Unregister the USB PCD LPM Callback * USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -940,8 +955,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) */ /** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -962,9 +977,10 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { __HAL_LOCK(hpcd); - (void)USB_DevConnect(hpcd->Instance); __HAL_PCD_ENABLE(hpcd); + (void)USB_DevConnect(hpcd->Instance); __HAL_UNLOCK(hpcd); + return HAL_OK; } @@ -977,9 +993,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) { __HAL_LOCK(hpcd); __HAL_PCD_DISABLE(hpcd); - - (void)USB_StopDevice(hpcd->Instance); - + (void)USB_DevDisconnect(hpcd->Instance); __HAL_UNLOCK(hpcd); return HAL_OK; @@ -993,14 +1007,18 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { - if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_CTR)) + uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance); + + if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR) { /* servicing of the endpoint correct transfer interrupt */ /* clear of the CTR flag into the sub */ (void)PCD_EP_ISR_Handler(hpcd); + + return; } - if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_RESET)) + if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET) { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); @@ -1011,19 +1029,25 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ (void)HAL_PCD_SetAddress(hpcd, 0U); + + return; } - if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_PMAOVR)) + if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR) { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); + + return; } - if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ERR)) + if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR) { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); + + return; } - if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP)) + if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP) { hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE); hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP); @@ -1045,37 +1069,38 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); + + return; } - if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SUSP)) + if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP) { /* Force low-power mode in the macrocell */ - hpcd->Instance->CNTR |= USB_CNTR_FSUSP; + hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP; /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); - hpcd->Instance->CNTR |= USB_CNTR_LPMODE; + hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE; - if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP) == 0U) - { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->SuspendCallback(hpcd); + hpcd->SuspendCallback(hpcd); #else - HAL_PCD_SuspendCallback(hpcd); + HAL_PCD_SuspendCallback(hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } + + return; } /* Handle LPM Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_L1REQ)) + if ((wIstr & USB_ISTR_L1REQ) == USB_ISTR_L1REQ) { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ); if (hpcd->LPM_State == LPM_L0) { /* Force suspend and low-power mode before going to L1 state*/ - hpcd->Instance->CNTR |= USB_CNTR_LPMODE; - hpcd->Instance->CNTR |= USB_CNTR_FSUSP; + hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE; + hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP; hpcd->LPM_State = LPM_L1; hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2; @@ -1093,9 +1118,11 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) HAL_PCD_SuspendCallback(hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } + + return; } - if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SOF)) + if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF) { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); @@ -1104,12 +1131,16 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) #else HAL_PCD_SOFCallback(hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + return; } - if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ESOF)) + if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF) { /* clear ESOF flag in ISTR */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); + + return; } } @@ -1291,8 +1322,8 @@ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) */ /** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions - * + * @brief management functions + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -1315,6 +1346,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) __HAL_LOCK(hpcd); (void)USB_DevConnect(hpcd->Instance); __HAL_UNLOCK(hpcd); + return HAL_OK; } @@ -1328,6 +1360,7 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) __HAL_LOCK(hpcd); (void)USB_DevDisconnect(hpcd->Instance); __HAL_UNLOCK(hpcd); + return HAL_OK; } @@ -1343,6 +1376,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) hpcd->USB_Address = address; (void)USB_SetDevAddress(hpcd->Instance, address); __HAL_UNLOCK(hpcd); + return HAL_OK; } /** @@ -1353,7 +1387,8 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) * @param ep_type endpoint type * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint16_t ep_mps, uint8_t ep_type) { HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; @@ -1480,6 +1515,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, /*setup and start the Xfer */ ep->xfer_buff = pBuf; ep->xfer_len = len; + ep->xfer_fill_db = 1U; + ep->xfer_len_db = len; ep->xfer_count = 0U; ep->is_in = 1U; ep->num = ep_addr & EP_ADDR_MSK; @@ -1528,10 +1565,7 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) __HAL_LOCK(hpcd); (void)USB_EPSetStall(hpcd->Instance, ep); - if ((ep_addr & EP_ADDR_MSK) == 0U) - { - (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup); - } + __HAL_UNLOCK(hpcd); return HAL_OK; @@ -1613,8 +1647,8 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) */ /** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim =============================================================================== ##### Peripheral State functions ##### @@ -1662,12 +1696,14 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) uint16_t count; uint16_t wIstr; uint16_t wEPVal; + uint16_t TxPctSize; uint8_t epindex; /* stay in loop while pending interrupts */ while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) { wIstr = hpcd->Instance->ISTR; + /* extract highest priority endpoint number */ epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); @@ -1680,8 +1716,8 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { /* DIR = 0 */ - /* DIR = 0 => IN int */ - /* DIR = 0 implies that (EP_CTR_TX = 1) always */ + /* DIR = 0 => IN int */ + /* DIR = 0 implies that (EP_CTR_TX = 1) always */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); ep = &hpcd->IN_ep[0]; @@ -1705,17 +1741,20 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { /* DIR = 1 */ - /* DIR = 1 & CTR_RX => SETUP or OUT int */ + /* DIR = 1 & CTR_RX => SETUP or OUT int */ /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ ep = &hpcd->OUT_ep[0]; wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); if ((wEPVal & USB_EP_SETUP) != 0U) { - /* Get SETUP Packet*/ + /* Get SETUP Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, ep->pmaadress, (uint16_t)ep->xfer_count); - /* SETUP bit kept frozen while CTR_RX = 1*/ + + USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, + ep->pmaadress, (uint16_t)ep->xfer_count); + + /* SETUP bit kept frozen while CTR_RX = 1 */ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); /* Process SETUP Packet*/ @@ -1725,76 +1764,96 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) HAL_PCD_SetupStageCallback(hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - else if ((wEPVal & USB_EP_CTR_RX) != 0U) { PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); - /* Get Control Data OUT Packet*/ + + /* Get Control Data OUT Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0U) + if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U)) { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, (uint16_t)ep->xfer_count); + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, + ep->pmaadress, (uint16_t)ep->xfer_count); + ep->xfer_buff += ep->xfer_count; + + /* Process Control Data OUT Packet */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, 0U); +#else + HAL_PCD_DataOutStageCallback(hpcd, 0U); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - /* Process Control Data OUT Packet*/ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataOutStageCallback(hpcd, 0U); -#else - HAL_PCD_DataOutStageCallback(hpcd, 0U); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); - PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + if ((PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0) & USB_EP_SETUP) == 0U) + { + PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } } } } else { - /* Decode and service non control endpoints interrupt */ - + /* Decode and service non control endpoints interrupt */ /* process related endpoint register */ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex); + if ((wEPVal & USB_EP_CTR_RX) != 0U) { /* clear int flag */ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex); ep = &hpcd->OUT_ep[epindex]; - /* OUT double Buffering*/ + /* OUT Single Buffering */ if (ep->doublebuffer == 0U) { count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + if (count != 0U) { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); } } +#if (USE_USB_DOUBLE_BUFFER == 1U) else { - if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U) + /* manage double buffer bulk out */ + if (ep->type == EP_TYPE_BULK) { - /*read from endpoint BUF0Addr buffer*/ - count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (count != 0U) + count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal); + } + else /* manage double buffer iso out */ + { + /* free EP OUT Buffer */ + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); + + if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U) { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); + /* read from endpoint BUF0Addr buffer */ + count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + + if (count != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); + } + } + else + { + /* read from endpoint BUF1Addr buffer */ + count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + + if (count != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); + } } } - else - { - /*read from endpoint BUF1Addr buffer*/ - count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (count != 0U) - { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); - } - } - /* free EP OUT Buffer */ - PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U); } - /*multi-packet on the NON control OUT endpoint*/ +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + /* multi-packet on the NON control OUT endpoint */ ep->xfer_count += count; ep->xfer_buff += count; @@ -1809,10 +1868,9 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) } else { - (void)HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + (void) USB_EPStartXfer(hpcd->Instance, ep); } - - } /* if((wEPVal & EP_CTR_RX) */ + } if ((wEPVal & USB_EP_CTR_TX) != 0U) { @@ -1821,13 +1879,24 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* clear int flag */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); - /*multi-packet on the NON control IN endpoint*/ - ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - ep->xfer_buff += ep->xfer_count; - - /* Zero Length Packet? */ - if (ep->xfer_len == 0U) + if (ep->type != EP_TYPE_BULK) { + ep->xfer_len = 0U; + +#if (USE_USB_DOUBLE_BUFFER == 1U) + if (ep->doublebuffer != 0U) + { + if ((wEPVal & USB_EP_DTOG_TX) != 0U) + { + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + } + else + { + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + } + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -1837,15 +1906,307 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) } else { - (void)HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + /* Manage Bulk Single Buffer Transaction */ + if ((wEPVal & USB_EP_KIND) == 0U) + { + /* multi-packet on the NON control IN endpoint */ + TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_len > TxPctSize) + { + ep->xfer_len -= TxPctSize; + } + else + { + ep->xfer_len = 0U; + } + + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + { + /* TX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, ep->num); +#else + HAL_PCD_DataInStageCallback(hpcd, ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + /* Transfer is not yet Done */ + ep->xfer_buff += TxPctSize; + ep->xfer_count += TxPctSize; + (void)USB_EPStartXfer(hpcd->Instance, ep); + } + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + /* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */ + else + { + (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal); + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ } } } } + return HAL_OK; } +#if (USE_USB_DOUBLE_BUFFER == 1U) +/** + * @brief Manage double buffer bulk out transaction from ISR + * @param hpcd PCD handle + * @param ep current endpoint handle + * @param wEPVal Last snapshot of EPRx register value taken in ISR + * @retval HAL status + */ +static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, + PCD_EPTypeDef *ep, uint16_t wEPVal) +{ + uint16_t count; + + /* Manage Buffer0 OUT */ + if ((wEPVal & USB_EP_DTOG_RX) != 0U) + { + /* Get count of received Data on buffer0 */ + count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_len >= count) + { + ep->xfer_len -= count; + } + else + { + ep->xfer_len = 0U; + } + + if (ep->xfer_len == 0U) + { + /* set NAK to OUT endpoint since double buffer is enabled */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); + } + + /* Check if Buffer1 is in blocked state which requires to toggle */ + if ((wEPVal & USB_EP_DTOG_TX) != 0U) + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); + } + + if (count != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); + } + } + /* Manage Buffer 1 DTOG_RX=0 */ + else + { + /* Get count of received data */ + count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_len >= count) + { + ep->xfer_len -= count; + } + else + { + ep->xfer_len = 0U; + } + + if (ep->xfer_len == 0U) + { + /* set NAK on the current endpoint */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); + } + + /*Need to FreeUser Buffer*/ + if ((wEPVal & USB_EP_DTOG_TX) == 0U) + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); + } + + if (count != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); + } + } + + return count; +} + + +/** + * @brief Manage double buffer bulk IN transaction from ISR + * @param hpcd PCD handle + * @param ep current endpoint handle + * @param wEPVal Last snapshot of EPRx register value taken in ISR + * @retval HAL status + */ +static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, + PCD_EPTypeDef *ep, uint16_t wEPVal) +{ + uint32_t len; + uint16_t TxPctSize; + + /* Data Buffer0 ACK received */ + if ((wEPVal & USB_EP_DTOG_TX) != 0U) + { + /* multi-packet on the NON control IN endpoint */ + TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_len > TxPctSize) + { + ep->xfer_len -= TxPctSize; + } + else + { + ep->xfer_len = 0U; + } + + /* Transfer is completed */ + if (ep->xfer_len == 0U) + { + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + + /* TX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, ep->num); +#else + HAL_PCD_DataInStageCallback(hpcd, ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + if ((wEPVal & USB_EP_DTOG_RX) != 0U) + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); + } + } + else /* Transfer is not yet Done */ + { + /* need to Free USB Buff */ + if ((wEPVal & USB_EP_DTOG_RX) != 0U) + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); + } + + /* Still there is data to Fill in the next Buffer */ + if (ep->xfer_fill_db == 1U) + { + ep->xfer_buff += TxPctSize; + ep->xfer_count += TxPctSize; + + /* Calculate the len of the new buffer to fill */ + if (ep->xfer_len_db >= ep->maxpacket) + { + len = ep->maxpacket; + ep->xfer_len_db -= len; + } + else if (ep->xfer_len_db == 0U) + { + len = TxPctSize; + ep->xfer_fill_db = 0U; + } + else + { + ep->xfer_fill_db = 0U; + len = ep->xfer_len_db; + ep->xfer_len_db = 0U; + } + + /* Write remaining Data to Buffer */ + /* Set the Double buffer counter for pma buffer1 */ + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); + + /* Copy user buffer to USB PMA */ + USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, (uint16_t)len); + } + } + } + else /* Data Buffer1 ACK received */ + { + /* multi-packet on the NON control IN endpoint */ + TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_len >= TxPctSize) + { + ep->xfer_len -= TxPctSize; + } + else + { + ep->xfer_len = 0U; + } + + /* Transfer is completed */ + if (ep->xfer_len == 0U) + { + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + + /* TX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, ep->num); +#else + HAL_PCD_DataInStageCallback(hpcd, ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + /* need to Free USB Buff */ + if ((wEPVal & USB_EP_DTOG_RX) == 0U) + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); + } + } + else /* Transfer is not yet Done */ + { + /* need to Free USB Buff */ + if ((wEPVal & USB_EP_DTOG_RX) == 0U) + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); + } + + /* Still there is data to Fill in the next Buffer */ + if (ep->xfer_fill_db == 1U) + { + ep->xfer_buff += TxPctSize; + ep->xfer_count += TxPctSize; + + /* Calculate the len of the new buffer to fill */ + if (ep->xfer_len_db >= ep->maxpacket) + { + len = ep->maxpacket; + ep->xfer_len_db -= len; + } + else if (ep->xfer_len_db == 0U) + { + len = TxPctSize; + ep->xfer_fill_db = 0U; + } + else + { + len = ep->xfer_len_db; + ep->xfer_len_db = 0U; + ep->xfer_fill_db = 0; + } + + /* Set the Double buffer counter for pmabuffer1 */ + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); + + /* Copy the user buffer to USB PMA */ + USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, (uint16_t)len); + } + } + } + + /*enable endpoint IN*/ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); + + return HAL_OK; +} +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + + /** * @} */ @@ -1859,5 +2220,3 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c index d6e4fc3..60d761e 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c @@ -10,13 +10,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,7 @@ /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions * @brief PCDEx control functions - * + * @verbatim =============================================================================== ##### Extended features functions ##### @@ -78,10 +77,8 @@ * @retval HAL status */ -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, - uint16_t ep_addr, - uint16_t ep_kind, - uint32_t pmaadress) +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, + uint16_t ep_kind, uint32_t pmaadress) { PCD_EPTypeDef *ep; @@ -103,6 +100,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, /* Configure the PMA */ ep->pmaadress = (uint16_t)pmaadress; } +#if (USE_USB_DOUBLE_BUFFER == 1U) else /* USB_DBL_BUF */ { /* Double Buffer Endpoint */ @@ -111,6 +109,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU); ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16); } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ return HAL_OK; } @@ -125,6 +124,9 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) USB_TypeDef *USBx = hpcd->Instance; hpcd->battery_charging_active = 1U; + /* Enable BCD feature */ + USBx->BCDR |= USB_BCDR_BCDEN; + /* Enable DCD : Data Contact Detect */ USBx->BCDR &= ~(USB_BCDR_PDEN); USBx->BCDR &= ~(USB_BCDR_SDEN); @@ -143,6 +145,7 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) USB_TypeDef *USBx = hpcd->Instance; hpcd->battery_charging_active = 0U; + /* Disable BCD feature */ USBx->BCDR &= ~(USB_BCDR_BCDEN); return HAL_OK; @@ -158,7 +161,7 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) USB_TypeDef *USBx = hpcd->Instance; uint32_t tickstart = HAL_GetTick(); - /* Wait Detect flag or a timeout is happen*/ + /* Wait Detect flag or a timeout is happen */ while ((USBx->BCDR & USB_BCDR_DCDET) == 0U) { /* Check for the Timeout */ @@ -330,5 +333,3 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c index 65b63bf..7127cb4 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c @@ -11,13 +11,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -187,7 +186,7 @@ void HAL_PWR_DisableBkUpAccess(void) ========================================= [..] (+) Entry: - The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API + The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered. (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode). (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode). @@ -209,7 +208,7 @@ void HAL_PWR_DisableBkUpAccess(void) =============================== [..] (+) Entry: - The Stop 0, Stop 1 modes are entered thru the following API's: + The Stop 0, Stop 1 modes are entered through the following API's: (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode(). (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only): (++) PWR_MAINREGULATOR_ON @@ -241,7 +240,7 @@ void HAL_PWR_DisableBkUpAccess(void) and Standby circuitry. (++) Entry: - (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API. + (+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API. SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API @@ -262,7 +261,7 @@ void HAL_PWR_DisableBkUpAccess(void) SRAM and registers contents are lost except for backup domain registers. (+) Entry: - The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API. + The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API. (+) Exit: (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, @@ -651,4 +650,3 @@ __weak void HAL_PWR_PVDCallback(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c index 96a9b21..05577aa 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c @@ -11,13 +11,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -40,10 +39,10 @@ /* Private define ------------------------------------------------------------*/ -#if defined (STM32G474xx) || defined (STM32G473xx) || defined (STM32G471xx) || defined (STM32G484xx) +#if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G483xx) || defined (STM32G484xx) #define PWR_PORTF_AVAILABLE_PINS 0x0000FFFFU /* PF0..PF15 */ #define PWR_PORTG_AVAILABLE_PINS 0x000007FFU /* PG0..PG10 */ -#elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB) +#elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB) || defined (STM32G491xx) || defined (STM32G4A1xx) #define PWR_PORTF_AVAILABLE_PINS 0x00000607U /* PF0..PF2 and PF9 and PF10 */ #define PWR_PORTG_AVAILABLE_PINS 0x00000400U /* PG10 */ #endif @@ -229,7 +228,7 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) /** * @brief Enable battery charging. - * When VDD is present, charge the external battery on VBAT thru an internal resistor. + * When VDD is present, charge the external battery on VBAT through an internal resistor. * @param ResistorSelection: specifies the resistor impedance. * This parameter can be one of the following values: * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor @@ -682,7 +681,7 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) /* Configure EXTI 35 to 38 interrupts if so required: - scan thru PVMType to detect which PVMx is set and + scan through PVMType to detect which PVMx is set and configure the corresponding EXTI line accordingly. */ switch (sConfigPVM->PVMType) { @@ -822,62 +821,6 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) return status; } -#if defined(PWR_CR3_UCPD_DBDIS) -/** - * @brief Enable the USB Type-C dead battery pull-down behavior - * on UCPDx_CC1 and UCPDx_CC2 pins - * @note After exiting reset, the USB Type-C dead battery behavior will be enabled, - * which may have a pull-down effect on CC1 and CC2 pins. - * It is recommended to disable it in all cases, either to stop this pull-down - * or to hand over control to the UCPD (which should therefore be - * initialized before doing the disable). - * @retval None - */ -void HAL_PWREx_EnableUSBDeadBatteryPD(void) -{ - /* writing 0 to enable the USB Type-C dead battery pull-down behavior */ - CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); -} - -/** - * @brief Disable the USB Type-C dead battery pull-down behavior - * on UCPDx_CC1 and UCPDx_CC2 pins - * @note After exiting reset, the USB Type-C dead battery behavior will be enabled, - * which may have a pull-down effect on CC1 and CC2 pins. - * It is recommended to disable it in all cases, either to stop this pull-down - * or to hand over control to the UCPD (which should therefore be - * initialized before doing the disable). - * @retval None - */ -void HAL_PWREx_DisableUSBDeadBatteryPD(void) -{ - /* writing 1 to disable the USB Type-C dead battery pull-down behavior */ - SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); -} -#endif /* PWR_CR3_UCPD_DBDIS */ - -#if defined(PWR_CR3_UCPD_STDBY) -/** - * @brief Enable the USB Type-C and Power Delivery standby mode - * @retval None - */ -void HAL_PWREx_EnableUSBStandByModePD(void) -{ - /* Write 1 just before entering Standby when using UCPD */ - SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); -} - -/** - * @brief Disable the USB Type-C and Power Delivery standby mode - * @retval None - */ -void HAL_PWREx_DisableUSBStandByModePD (void) -{ - /* Write 0 immediately after Standby exit when using UCPD, - and before writing any UCPD registers */ - CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); -} -#endif /* PWR_CR3_UCPD_STDBY */ /** * @brief Enter Low-power Run mode @@ -1164,6 +1107,61 @@ __weak void HAL_PWREx_PVM4Callback(void) */ } +#if defined(PWR_CR3_UCPD_STDBY) +/** + * @brief Enable UCPD configuration memorization in Standby. + * @retval None + */ +void HAL_PWREx_EnableUCPDStandbyMode(void) +{ + /* Memorize UCPD configuration when entering standby mode */ + SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); +} + +/** + * @brief Disable UCPD configuration memorization in Standby. + * @note This function must be called on exiting the Standby mode and before any UCPD + * configuration update. + * @retval None + */ +void HAL_PWREx_DisableUCPDStandbyMode(void) +{ + /* Write 0 immediately after Standby exit when using UCPD, + and before writing any UCPD registers */ + CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); +} +#endif /* PWR_CR3_UCPD_STDBY */ + +#if defined(PWR_CR3_UCPD_DBDIS) +/** + * @brief Enable the USB Type-C dead battery pull-down behavior + * on UCPDx_CC1 and UCPDx_CC2 pins + * @retval None + */ +void HAL_PWREx_EnableUCPDDeadBattery(void) +{ + /* Write 0 to enable the USB Type-C dead battery pull-down behavior */ + CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); +} + +/** + * @brief Disable the USB Type-C dead battery pull-down behavior + * on UCPDx_CC1 and UCPDx_CC2 pins + * @note After exiting reset, the USB Type-C dead battery behavior will be enabled, + * which may have a pull-down effect on CC1 and CC2 pins. + * It is recommended to disable it in all cases, either to stop this pull-down + * or to hand over control to the UCPD (which should therefore be + * initialized before doing the disable). + * @retval None + */ +void HAL_PWREx_DisableUCPDDeadBattery(void) +{ + /* Write 1 to disable the USB Type-C dead battery pull-down behavior */ + SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); +} +#endif /* PWR_CR3_UCPD_DBDIS */ + + /** * @} @@ -1182,4 +1180,3 @@ __weak void HAL_PWREx_PVM4Callback(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c index e3b91e7..8c6fe27 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c @@ -18,8 +18,8 @@ and I-Cache are disabled, and all peripherals are off except internal SRAM, Flash and JTAG. - (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses: - all peripherals mapped on these busses are running at HSI speed. + (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) buses: + all peripherals mapped on these buses are running at HSI speed. (+) The clock for all peripherals is switched off, except the SRAM and FLASH. (+) All GPIOs are in analog mode, except the JTAG pins which are assigned to be used for debug purpose. @@ -29,7 +29,7 @@ (+) Configure the clock source to be used to drive the System clock (if the application needs higher frequency/performance) (+) Configure the System clock frequency and Flash settings - (+) Configure the AHB and APB busses prescalers + (+) Configure the AHB and APB buses prescalers (+) Enable the clock for the peripheral(s) to be used (+) Configure the clock source(s) for peripherals which clocks are not derived from the System clock (USB, RNG, USART, LPUART, FDCAN, some TIMERs, @@ -39,14 +39,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -83,9 +81,13 @@ /** @defgroup RCC_Private_Macros RCC Private Macros * @{ */ -#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() -#define MCO1_GPIO_PORT GPIOA -#define MCO1_PIN GPIO_PIN_8 +#define RCC_GET_MCO_GPIO_PIN(__RCC_MCOx__) ((__RCC_MCOx__) & GPIO_PIN_MASK) + +#define RCC_GET_MCO_GPIO_AF(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOAF_MASK) >> RCC_MCO_GPIOAF_POS) + +#define RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOPORT_MASK) >> RCC_MCO_GPIOPORT_POS) + +#define RCC_GET_MCO_GPIO_PORT(__RCC_MCOx__) (AHB2PERIPH_BASE + ((0x00000400UL) * RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__))) #define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \ (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__))) @@ -119,7 +121,7 @@ static uint32_t RCC_GetSysClockFreqFromPLLSource(void); =============================================================================== [..] This section provides functions allowing to configure the internal and external oscillators - (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 + (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 and APB2). [..] Internal/external clock and PLL configuration @@ -149,14 +151,14 @@ static uint32_t RCC_GetSysClockFreqFromPLLSource(void); (+) MCO (microcontroller clock output): used to output LSI, HSI, LSE, HSE, main PLL clock, system clock or RC48 clock (through a configurable prescaler) on PA8 pin. - [..] System, AHB and APB busses clocks configuration + [..] System, AHB and APB buses clocks configuration (+) Several clock sources can be used to drive the System clock (SYSCLK): HSI, HSE and main PLL. The AHB clock (HCLK) is derived from System clock through configurable prescaler and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these busses. You can use + the peripherals mapped on these buses. You can use "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: @@ -180,30 +182,22 @@ static uint32_t RCC_GetSysClockFreqFromPLLSource(void); @endverbatim Table 1. HCLK clock frequency for STM32G4xx devices - +--------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |--------------------------------------| - | | voltage range 1 | voltage range 2 | - | | 1.2 V | 1.0 V | - |-----------------|-------------------|------------------| - |0WS(1 CPU cycles)| 0 < HCLK <= 20 | 0 < HCLK <= 8 | - |-----------------|-------------------|------------------| - |1WS(2 CPU cycles)| 20 < HCLK <= 40 | 8 < HCLK <= 16 | - |-----------------|-------------------|------------------| - |2WS(3 CPU cycles)| 40 < HCLK <= 60 | 16 < HCLK <= 26 | - |-----------------|-------------------|------------------| - |3WS(4 CPU cycles)| 60 < HCLK <= 80 | 16 < HCLK <= 26 | - |-----------------|-------------------|------------------| - |4WS(5 CPU cycles)| 80 < HCLK <= 100 | 16 < HCLK <= 26 | - |-----------------|-------------------|------------------| - |5WS(6 CPU cycles)| 100 < HCLK <= 120 | 16 < HCLK <= 26 | - |-----------------|-------------------|------------------| - |6WS(7 CPU cycles)| 120 < HCLK <= 140 | 16 < HCLK <= 26 | - |-----------------|-------------------|------------------| - |7WS(8 CPU cycles)| 140 < HCLK <= 160 | 16 < HCLK <= 26 | - |-----------------|-------------------|------------------| - |8WS(9 CPU cycles)| 160 < HCLK <= 170 | 16 < HCLK <= 26 | - +--------------------------------------------------------+ + +----------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |----------------------------------------------------------| + | | voltage range 1 | voltage range 1 | voltage range 2 | + | | boost mode 1.28 V | normal mode 1.2 V | 1.0 V | + |-----------------|-------------------|-------------------|------------------| + |0WS(1 CPU cycles)| HCLK <= 34 | HCLK <= 30 | HCLK <= 13 | + |-----------------|-------------------|-------------------|------------------| + |1WS(2 CPU cycles)| HCLK <= 68 | HCLK <= 60 | HCLK <= 26 | + |-----------------|-------------------|-------------------|------------------| + |2WS(3 CPU cycles)| HCLK <= 102 | HCLK <= 90 | - | + |-----------------|-------------------|-------------------|------------------| + |3WS(4 CPU cycles)| HCLK <= 136 | HCLK <= 120 | - | + |-----------------|-------------------|-------------------|------------------| + |4WS(5 CPU cycles)| HCLK <= 170 | HCLK <= 150 | - | + +----------------------------------------------------------------------------+ * @{ */ @@ -263,7 +257,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) SystemCoreClock = HSI_VALUE; /* Adapt Systick interrupt period */ - if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + if (HAL_InitTick(uwTickPrio) != HAL_OK) { return HAL_ERROR; } @@ -407,7 +401,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); /* Adapt Systick interrupt period */ - if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + if (HAL_InitTick(uwTickPrio) != HAL_OK) { return HAL_ERROR; } @@ -723,7 +717,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /** - * @brief Initialize the CPU, AHB and APB busses clocks according to the specified + * @brief Initialize the CPU, AHB and APB buses clocks according to the specified * parameters in the RCC_ClkInitStruct. * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC peripheral. @@ -943,7 +937,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); /* Configure the source of time base considering new system clocks settings*/ - return HAL_InitTick(TICK_INT_PRIORITY); + return HAL_InitTick(uwTickPrio); } /** @@ -960,7 +954,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui [..] This subsection provides a set of functions allowing to: - (+) Ouput clock to MCO pin. + (+) Output clock to MCO pin. (+) Retrieve current clock frequencies. (+) Enable the Clock Security System. @@ -969,11 +963,16 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui */ /** - * @brief Select the clock source to output on MCO pin(PA8). - * @note PA8 should be configured in alternate function mode. + * @brief Select the clock source to output on MCO pin(PA8/PG10). + * @note PA8/PG10 should be configured in alternate function mode. + * @note The default configuration of the GPIOG pin 10 (PG10) is set to reset mode (NRST pin) + * and user shall set the NRST_MODE Bit in the FLASH OPTR register to be able to use it + * as an MCO pin. + * The @ref HAL_FLASHEx_OBProgram() API can be used to configure the NRST_MODE Bit value. * @param RCC_MCOx specifies the output direction for the clock source. * For STM32G4xx family this parameter can have only one value: - * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). + * @arg @ref RCC_MCO_PA8 Clock source to output on MCO1 pin(PA8). + * @arg @ref RCC_MCO_PG10 Clock source to output on MCO1 pin(PG10). * @param RCC_MCOSource specifies the clock source to output. * This parameter can be one of the following values: * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO @@ -995,29 +994,41 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui */ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) { - GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitTypeDef gpio_initstruct; + uint32_t mcoindex; + uint32_t mco_gpio_index; + GPIO_TypeDef * mco_gpio_port; /* Check the parameters */ assert_param(IS_RCC_MCO(RCC_MCOx)); - assert_param(IS_RCC_MCODIV(RCC_MCODiv)); - assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); - /* Prevent unused argument(s) compilation warning if no assert_param check */ - UNUSED(RCC_MCOx); + /* Common GPIO init parameters */ + gpio_initstruct.Mode = GPIO_MODE_AF_PP; + gpio_initstruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + gpio_initstruct.Pull = GPIO_NOPULL; - /* MCO Clock Enable */ - MCO1_CLK_ENABLE(); + /* Get MCOx selection */ + mcoindex = RCC_MCOx & RCC_MCO_INDEX_MASK; - /* Configue the MCO1 pin in alternate function mode */ - GPIO_InitStruct.Pin = MCO1_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Alternate = GPIO_AF0_MCO; - HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); + /* Get MCOx GPIO Port */ + mco_gpio_port = (GPIO_TypeDef *) RCC_GET_MCO_GPIO_PORT(RCC_MCOx); - /* Mask MCOSEL[] and MCOPRE[] bits then set MCO1 clock source and prescaler */ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv)); + /* MCOx Clock Enable */ + mco_gpio_index = RCC_GET_MCO_GPIO_INDEX(RCC_MCOx); + SET_BIT(RCC->AHB2ENR, (1UL << mco_gpio_index )); + + /* Configure the MCOx pin in alternate function mode */ + gpio_initstruct.Pin = RCC_GET_MCO_GPIO_PIN(RCC_MCOx); + gpio_initstruct.Alternate = RCC_GET_MCO_GPIO_AF(RCC_MCOx); + HAL_GPIO_Init(mco_gpio_port, &gpio_initstruct); + + if (mcoindex == RCC_MCO1_INDEX) + { + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv)); + } } /** @@ -1388,4 +1399,3 @@ static uint32_t RCC_GetSysClockFreqFromPLLSource(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c index bddb486..acd2664 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c @@ -12,14 +12,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -498,8 +496,17 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC345 | \ RCC_PERIPHCLK_QSPI | \ RCC_PERIPHCLK_RTC; +#elif defined(STM32G491xx) || defined(STM32G4A1xx) -#elif defined(STM32G473xx) + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ + RCC_PERIPHCLK_UART5 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_FDCAN | \ + RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC345 | \ + RCC_PERIPHCLK_QSPI | \ + RCC_PERIPHCLK_RTC; + +#elif defined(STM32G473xx) || defined(STM32G483xx) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ RCC_PERIPHCLK_UART5 | \ @@ -1360,7 +1367,7 @@ void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) /* LSCO Pin Clock Enable */ __LSCO_CLK_ENABLE(); - /* Configue the LSCO pin in analog mode */ + /* Configure the LSCO pin in analog mode */ GPIO_InitStruct.Pin = LSCO_PIN; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; @@ -1442,7 +1449,7 @@ void HAL_RCCEx_DisableLSCO(void) ##### Extended Clock Recovery System Control functions ##### =============================================================================== [..] - For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows: + For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows: (#) In System clock config, HSI48 needs to be enabled @@ -1815,5 +1822,4 @@ __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c index 363c0cc..d505b72 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c @@ -9,7 +9,17 @@ * + IO operation functions * + Peripheral Control functions * + Peripheral State functions + ****************************************************************************** + * @attention * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -65,16 +75,16 @@ Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback. Function HAL_SPI_RegisterCallback() allows to register following callbacks: - (+) TxCpltCallback : SPI Tx Completed callback - (+) RxCpltCallback : SPI Rx Completed callback - (+) TxRxCpltCallback : SPI TxRx Completed callback - (+) TxHalfCpltCallback : SPI Tx Half Completed callback - (+) RxHalfCpltCallback : SPI Rx Half Completed callback - (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback - (+) ErrorCallback : SPI Error callback - (+) AbortCpltCallback : SPI Abort callback - (+) MspInitCallback : SPI Msp Init callback - (+) MspDeInitCallback : SPI Msp DeInit callback + (++) TxCpltCallback : SPI Tx Completed callback + (++) RxCpltCallback : SPI Rx Completed callback + (++) TxRxCpltCallback : SPI TxRx Completed callback + (++) TxHalfCpltCallback : SPI Tx Half Completed callback + (++) RxHalfCpltCallback : SPI Rx Half Completed callback + (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (++) ErrorCallback : SPI Error callback + (++) AbortCpltCallback : SPI Abort callback + (++) MspInitCallback : SPI Msp Init callback + (++) MspDeInitCallback : SPI Msp DeInit callback This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. @@ -84,17 +94,18 @@ HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: - (+) TxCpltCallback : SPI Tx Completed callback - (+) RxCpltCallback : SPI Rx Completed callback - (+) TxRxCpltCallback : SPI TxRx Completed callback - (+) TxHalfCpltCallback : SPI Tx Half Completed callback - (+) RxHalfCpltCallback : SPI Rx Half Completed callback - (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback - (+) ErrorCallback : SPI Error callback - (+) AbortCpltCallback : SPI Abort callback - (+) MspInitCallback : SPI Msp Init callback - (+) MspDeInitCallback : SPI Msp DeInit callback + (++) TxCpltCallback : SPI Tx Completed callback + (++) RxCpltCallback : SPI Rx Completed callback + (++) TxRxCpltCallback : SPI TxRx Completed callback + (++) TxHalfCpltCallback : SPI Tx Half Completed callback + (++) RxHalfCpltCallback : SPI Rx Half Completed callback + (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (++) ErrorCallback : SPI Error callback + (++) AbortCpltCallback : SPI Abort callback + (++) MspInitCallback : SPI Msp Init callback + (++) MspDeInitCallback : SPI Msp DeInit callback + [..] By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET all callbacks are set to the corresponding weak functions: examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback(). @@ -104,6 +115,7 @@ If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state, @@ -112,7 +124,8 @@ using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() or HAL_SPI_Init() function. - When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or + [..] + When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available and weak (surcharged) callbacks are used. @@ -128,7 +141,7 @@ DataSize = SPI_DATASIZE_8BIT: +----------------------------------------------------------------------------------------------+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | - | Process | Tranfert mode |---------------------|----------------------|----------------------| + | Process | Transfer mode |---------------------|----------------------|----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==============================================================================================| | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | @@ -153,7 +166,7 @@ DataSize = SPI_DATASIZE_16BIT: +----------------------------------------------------------------------------------------------+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | - | Process | Tranfert mode |---------------------|----------------------|----------------------| + | Process | Transfer mode |---------------------|----------------------|----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==============================================================================================| | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | @@ -181,18 +194,6 @@ (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -334,6 +335,24 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + } + else + { + /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ + hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + } + } + else + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + + /* Force polarity and phase to TI protocaol requirements */ + hspi->Init.CLKPolarity = SPI_POLARITY_LOW; + hspi->Init.CLKPhase = SPI_PHASE_1EDGE; } #if (USE_SPI_CRC != 0U) assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); @@ -397,44 +416,56 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; } - /* Align the CRC Length on the data size */ - if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) - { - /* CRC Length aligned on the data size : value set by default */ - if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; - } - else - { - hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT; - } - } - /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, Communication speed, First bit and CRC calculation state */ - WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | - hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | - hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation)); + WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | + (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) | + (hspi->Init.CLKPolarity & SPI_CR1_CPOL) | + (hspi->Init.CLKPhase & SPI_CR1_CPHA) | + (hspi->Init.NSS & SPI_CR1_SSM) | + (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) | + (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | + (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); #if (USE_SPI_CRC != 0U) - /* Configure : CRC Length */ - if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + /*---------------------------- SPIx CRCL Configuration -------------------*/ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - hspi->Instance->CR1 |= SPI_CR1_CRCL; + /* Align the CRC Length on the data size */ + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) + { + /* CRC Length aligned on the data size : value set by default */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; + } + else + { + hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT; + } + } + + /* Configure : CRC Length */ + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL); + } } #endif /* USE_SPI_CRC */ /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ - WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode | - hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth); + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | + (hspi->Init.TIMode & SPI_CR2_FRF) | + (hspi->Init.NSSPMode & SPI_CR2_NSSP) | + (hspi->Init.DataSize & SPI_CR2_DS_Msk) | + (frxth & SPI_CR2_FRXTH))); #if (USE_SPI_CRC != 0U) /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ /* Configure : CRC Polynomial */ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); + WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk)); } #endif /* USE_SPI_CRC */ @@ -832,6 +863,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_TX(hspi); } @@ -972,6 +1005,11 @@ error: */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; +#endif /* USE_SPI_CRC */ uint32_t tickstart; HAL_StatusTypeDef errorcode = HAL_OK; @@ -1039,6 +1077,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Configure communication direction: 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_RX(hspi); } @@ -1136,12 +1176,18 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) { /* Read 16bit CRC */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; /* Read 8bit CRC */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) { @@ -1153,7 +1199,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 goto error; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); } } } @@ -1204,8 +1252,11 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD HAL_SPI_StateTypeDef tmp_state; uint32_t tickstart; #if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; uint32_t spi_cr1; uint32_t spi_cr2; + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ /* Variable used to alternate Rx and Tx during transfer */ @@ -1439,12 +1490,18 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) { /* Read 16bit CRC */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; /* Read 8bit CRC */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { @@ -1456,7 +1513,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD goto error; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); } } } @@ -1541,6 +1600,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_TX(hspi); } @@ -1632,6 +1693,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_RX(hspi); } @@ -1832,6 +1895,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_TX(hspi); } @@ -1962,6 +2027,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_RX(hspi); } @@ -3003,6 +3070,11 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; +#endif /* USE_SPI_CRC */ /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -3027,12 +3099,18 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { /* Read 16bit CRC */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; /* Read 8bit CRC */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { @@ -3042,14 +3120,25 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); } } } #endif /* USE_SPI_CRC */ - /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + /* Check if we are in Master RX 2 line mode */ + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + } + else + { + /* Normal case */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + } /* Check the end of the transaction */ if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) @@ -3098,6 +3187,11 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; +#endif /* USE_SPI_CRC */ /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -3120,8 +3214,12 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } - /* Read CRC to Flush DR and RXNE flag */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); } else { @@ -3131,7 +3229,9 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } /* Read CRC to Flush DR and RXNE flag */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } } #endif /* USE_SPI_CRC */ @@ -3466,8 +3566,15 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - /* Read 8bit CRC to flush Data Regsiter */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; + + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC to flush Data Register */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); hspi->CRCSize--; @@ -3574,8 +3681,12 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { - /* Read 16bit CRC to flush Data Regsiter */ - READ_REG(hspi->Instance->DR); + __IO uint32_t tmpreg = 0U; + + /* Read 16bit CRC to flush Data Register */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); /* Disable RXNE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); @@ -3630,8 +3741,15 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; + + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; /* Read 8bit CRC to flush Data Register */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); hspi->CRCSize--; @@ -3684,8 +3802,12 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint32_t tmpreg = 0U; + /* Read 16bit CRC to flush Data Register */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); /* Disable RXNE and ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); @@ -3791,69 +3913,22 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart) { + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + tmp_tickstart = HAL_GetTick(); + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) { if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U)) - { - /* Disable the SPI and reset the CRC: the CRC value should be cleared - on both master and slave sides in order to resynchronize the master - and slave for their respective CRC calculation */ - - /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); - - if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) - || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) - { - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - } - - /* Reset CRC Calculation */ - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } - - hspi->State = HAL_SPI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_TIMEOUT; - } - } - } - - return HAL_OK; -} - -/** - * @brief Handle SPI FIFO Communication Timeout. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param Fifo Fifo to check - * @param State Fifo state to check - * @param Timeout Timeout duration - * @param Tickstart tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, - uint32_t Timeout, uint32_t Tickstart) -{ - while ((hspi->Instance->SR & Fifo) != State) - { - if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) - { - /* Read 8bit CRC to flush Data Register */ - READ_REG(*((__IO uint8_t *)&hspi->Instance->DR)); - } - - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) { /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master @@ -3882,6 +3957,94 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, return HAL_TIMEOUT; } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if (count == 0U) + { + tmp_timeout = 0U; + } + count--; + } + } + + return HAL_OK; +} + +/** + * @brief Handle SPI FIFO Communication Timeout. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Fifo Fifo to check + * @param State Fifo state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, + uint32_t Timeout, uint32_t Tickstart) +{ + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + tmp_tickstart = HAL_GetTick(); + + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U); + + while ((hspi->Instance->SR & Fifo) != State) + { + if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) + { + /* Flush Data Register by a blank read */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + } + + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if (count == 0U) + { + tmp_timeout = 0U; + } + count--; } } @@ -3968,7 +4131,7 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) { uint32_t tickstart; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Disable ERR interrupt */ @@ -4271,4 +4434,3 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.c index ec72eb4..ddec1b0 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.c @@ -10,13 +10,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -111,5 +110,3 @@ HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c index d75c805..02cbdb4 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c @@ -29,6 +29,17 @@ * + Commutation Event configuration with Interruption and DMA * + TIM OCRef clear configuration * + TIM External Clock configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### TIMER Generic features ##### @@ -103,14 +114,14 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_TIM_RegisterCallback() to register a callback. - @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + Use Function HAL_TIM_RegisterCallback() to register a callback. + HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default + Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. [..] @@ -151,7 +162,7 @@ [..] By default, after the Init and when the state is HAL_TIM_STATE_RESET all interrupt callbacks are set to the corresponding weak functions: - examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). + examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback(). [..] Exception done for MspInit and MspDeInit functions that are reset to the legacy weak @@ -165,7 +176,7 @@ all interrupt callbacks are set to the corresponding weak functions: in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. + using HAL_TIM_RegisterCallback() before calling DeInit or Init function. [..] When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or @@ -174,17 +185,6 @@ all interrupt callbacks are set to the corresponding weak functions: @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -203,9 +203,15 @@ all interrupt callbacks are set to the corresponding weak functions: /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +/** @addtogroup TIM_Private_Constants + * @{ + */ #define TIMx_AF2_OCRSEL TIM1_AF2_OCRSEL -/* Private macro -------------------------------------------------------------*/ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup TIM_Private_Functions @@ -227,6 +233,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, @@ -312,6 +319,13 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -345,6 +359,13 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_Base_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -397,19 +418,29 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } - /* Change the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - /* Return function status */ return HAL_OK; } @@ -424,13 +455,10 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the TIM state*/ + /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ @@ -449,12 +477,28 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -472,12 +516,16 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Disable the TIM Update interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + /* Return function status */ return HAL_OK; } @@ -496,11 +544,12 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + /* Set the TIM state */ + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { @@ -513,7 +562,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat } else { - /* nothing to do */ + return HAL_ERROR; } /* Set the DMA Period elapsed callbacks */ @@ -524,8 +573,10 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -533,8 +584,15 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -561,7 +619,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ + /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ @@ -644,6 +702,13 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -677,6 +742,13 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_OC_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -736,6 +808,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); @@ -746,8 +827,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -786,6 +874,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -803,11 +894,21 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -839,27 +940,38 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } } /* Return function status */ - return HAL_OK; + return status; } /** @@ -875,6 +987,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -909,23 +1023,30 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - /* Return function status */ - return HAL_OK; + return status; } /** @@ -943,16 +1064,18 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { @@ -960,12 +1083,12 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } switch (Channel) @@ -980,8 +1103,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1000,8 +1125,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1020,8 +1147,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ @@ -1039,8 +1168,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -1049,27 +1180,38 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } default: + status = HAL_ERROR; break; } - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1085,6 +1227,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel */ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1123,26 +1267,30 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - /* Return function status */ - return HAL_OK; + return status; } /** @@ -1221,6 +1369,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -1254,6 +1409,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_PWM_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -1313,6 +1475,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); @@ -1323,8 +1494,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1363,8 +1541,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1383,10 +1561,21 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -1418,27 +1607,38 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel } default: + status = HAL_ERROR; break; } - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1454,6 +1654,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1488,23 +1690,30 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - /* Return function status */ - return HAL_OK; + return status; } /** @@ -1522,16 +1731,18 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { @@ -1539,12 +1750,12 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } switch (Channel) @@ -1559,8 +1770,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1579,8 +1792,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ @@ -1598,8 +1813,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Capture/Compare 3 request */ @@ -1617,8 +1834,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -1627,27 +1846,38 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } default: + status = HAL_ERROR; break; } - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1663,6 +1893,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1701,26 +1933,30 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } default: + status = HAL_ERROR; break; } - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - /* Return function status */ - return HAL_OK; + return status; } /** @@ -1799,6 +2035,13 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) /* Init the base time for the input capture */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -1832,6 +2075,13 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_IC_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -1885,16 +2135,36 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1925,6 +2195,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1942,11 +2216,26 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -1978,20 +2267,32 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (status == HAL_OK) { - __HAL_TIM_ENABLE(htim); + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } } /* Return function status */ - return HAL_OK; + return status; } /** @@ -2007,6 +2308,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -2041,17 +2344,25 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + if (status == HAL_OK) + { + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -2069,17 +2380,24 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + /* Set the TIM channel state */ + if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData == NULL) && (Length > 0U)) { @@ -2087,14 +2405,18 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + switch (Channel) { case TIM_CHANNEL_1: @@ -2107,8 +2429,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ @@ -2126,8 +2450,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ @@ -2145,8 +2471,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ @@ -2164,8 +2492,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -2174,21 +2504,26 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } default: + status = HAL_ERROR; break; } - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } /* Return function status */ - return HAL_OK; + return status; } /** @@ -2204,10 +2539,15 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel */ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + switch (Channel) { case TIM_CHANNEL_1: @@ -2243,20 +2583,22 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + if (status == HAL_OK) + { + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** * @} @@ -2290,6 +2632,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @note When the timer instance is initialized in One Pulse mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. * @param htim TIM One Pulse handle * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: @@ -2345,6 +2690,15 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul /* Configure the OPM Mode */ htim->Instance->CR1 |= OnePulseMode; + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -2378,6 +2732,15 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_OnePulse_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -2419,23 +2782,44 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ @@ -2455,11 +2839,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu /** * @brief Stops the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be disable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2471,7 +2856,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); @@ -2485,29 +2870,56 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ @@ -2533,11 +2945,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2555,7 +2968,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); @@ -2568,6 +2981,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -2606,6 +3025,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @note When the timer instance is initialized in Encoder mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status @@ -2623,15 +3045,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini } /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); @@ -2703,6 +3125,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -2737,6 +3168,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_Encoder_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -2788,8 +3228,58 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } /* Enable the encoder interface channels */ switch (Channel) @@ -2833,7 +3323,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ @@ -2862,6 +3352,20 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + /* Return function status */ return HAL_OK; } @@ -2878,8 +3382,58 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } /* Enable the encoder interface channels */ /* Enable the capture compare Interrupts 1 and/or 2 */ @@ -2929,7 +3483,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ @@ -2960,8 +3514,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ return HAL_OK; @@ -2983,27 +3548,95 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) { - /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - if ((htim->State == HAL_TIM_STATE_BUSY)) + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) { - return HAL_BUSY; - } - else if ((htim->State == HAL_TIM_STATE_READY)) - { - if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) { - return HAL_ERROR; + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData1 == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } } else { - htim->State = HAL_TIM_STATE_BUSY; + return HAL_ERROR; + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData2 == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; } } else { - /* nothing to do */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } } switch (Channel) @@ -3018,18 +3651,21 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); break; } @@ -3042,22 +3678,25 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); break; } - case TIM_CHANNEL_ALL: + default: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; @@ -3067,8 +3706,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -3080,27 +3721,29 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + break; } - - default: - break; } + /* Return function status */ return HAL_OK; } @@ -3118,7 +3761,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ @@ -3153,8 +3796,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ return HAL_OK; @@ -3467,6 +4121,8 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_CHANNEL_MODE(sConfig->OCMode, Channel)); @@ -3475,8 +4131,6 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, /* Process Locked */ __HAL_LOCK(htim); - htim->State = HAL_TIM_STATE_BUSY; - switch (Channel) { case TIM_CHANNEL_1: @@ -3540,14 +4194,13 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, } default: + status = HAL_ERROR; break; } - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -3565,6 +4218,8 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, */ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); @@ -3575,8 +4230,6 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /* Process Locked */ __HAL_LOCK(htim); - htim->State = HAL_TIM_STATE_BUSY; - if (Channel == TIM_CHANNEL_1) { /* TI1 Configuration */ @@ -3623,7 +4276,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /* Set the IC3PSC value */ htim->Instance->CCMR2 |= sConfig->ICPrescaler; } - else + else if (Channel == TIM_CHANNEL_4) { /* TI4 Configuration */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); @@ -3639,12 +4292,14 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /* Set the IC4PSC value */ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); } - - htim->State = HAL_TIM_STATE_READY; + else + { + status = HAL_ERROR; + } __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -3666,6 +4321,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); @@ -3675,8 +4332,6 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, /* Process Locked */ __HAL_LOCK(htim); - htim->State = HAL_TIM_STATE_BUSY; - switch (Channel) { case TIM_CHANNEL_1: @@ -3782,14 +4437,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, } default: + status = HAL_ERROR; break; } - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -3805,11 +4459,16 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @note To output a waveform with a minimum delay user can enable the fast + * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx + * output is forced in response to the edge detection on TIx input, + * without taking in account the comparison. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel) { + HAL_StatusTypeDef status = HAL_OK; TIM_OC_InitTypeDef temp1; /* Check the parameters */ @@ -3840,6 +4499,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O TIM_OC1_SetConfig(htim->Instance, &temp1); break; } + case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); @@ -3847,60 +4507,67 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O TIM_OC2_SetConfig(htim->Instance, &temp1); break; } + default: + status = HAL_ERROR; break; } - switch (InputChannel) + if (status == HAL_OK) { - case TIM_CHANNEL_1: + switch (InputChannel) { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1FP1; + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - break; + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + status = HAL_ERROR; + break; } - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); - - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI2FP2; - - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - break; - } - - default: - break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); - return HAL_OK; + return status; } else { @@ -3958,8 +4625,14 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { - return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - ((BurstLength) >> 8U) + 1U); + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + + return status; } /** @@ -4014,6 +4687,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); @@ -4021,11 +4696,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint assert_param(IS_TIM_DMA_LENGTH(BurstLength)); assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { @@ -4033,13 +4708,14 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint } else { - htim->State = HAL_TIM_STATE_BUSY; + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; } } else { /* nothing to do */ } + switch (BurstRequestSrc) { case TIM_DMA_UPDATE: @@ -4055,6 +4731,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4072,6 +4749,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4089,6 +4767,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4106,6 +4785,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4123,6 +4803,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4140,6 +4821,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4157,23 +4839,26 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; } default: + status = HAL_ERROR; break; } - /* Configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength); - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - - htim->State = HAL_TIM_STATE_READY; + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -4185,6 +4870,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -4193,47 +4879,51 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B { case TIM_DMA_UPDATE: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); break; } case TIM_DMA_CC1: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_DMA_CC2: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_DMA_CC3: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_DMA_CC4: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } case TIM_DMA_COM: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); break; } case TIM_DMA_TRIGGER: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); break; } default: + status = HAL_ERROR; break; } - if (HAL_OK == status) + if (status == HAL_OK) { /* Disable the TIM Update DMA request */ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; } /* Return function status */ @@ -4290,8 +4980,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { - return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - ((BurstLength) >> 8U) + 1U); + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + return status; } /** @@ -4346,6 +5041,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); @@ -4353,11 +5050,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 assert_param(IS_TIM_DMA_LENGTH(BurstLength)); assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { @@ -4365,7 +5062,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 } else { - htim->State = HAL_TIM_STATE_BUSY; + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; } } else @@ -4387,6 +5084,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4404,6 +5102,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4421,6 +5120,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4438,6 +5138,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4455,6 +5156,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4472,6 +5174,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4489,24 +5192,27 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; } default: + status = HAL_ERROR; break; } - /* Configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength); + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - - htim->State = HAL_TIM_STATE_READY; + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -4518,6 +5224,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -4526,47 +5233,51 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu { case TIM_DMA_UPDATE: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); break; } case TIM_DMA_CC1: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_DMA_CC2: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_DMA_CC3: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_DMA_CC4: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } case TIM_DMA_COM: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); break; } case TIM_DMA_TRIGGER: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); break; } default: + status = HAL_ERROR; break; } - if (HAL_OK == status) + if (status == HAL_OK) { /* Disable the TIM Update DMA request */ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; } /* Return function status */ @@ -4637,6 +5348,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); @@ -4660,7 +5373,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, } else { - CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); } break; } @@ -4722,104 +5435,108 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, } default: + status = HAL_ERROR; break; } - switch (Channel) + if (status == HAL_OK) { - case TIM_CHANNEL_1: + switch (Channel) { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + case TIM_CHANNEL_1: { - /* Enable the OCREF clear feature for Channel 1 */ - SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; } - else + case TIM_CHANNEL_2: { - /* Disable the OCREF clear feature for Channel 1 */ - CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; } - break; + case TIM_CHANNEL_3: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; + } + case TIM_CHANNEL_4: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; + } + case TIM_CHANNEL_5: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 5 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + else + { + /* Disable the OCREF clear feature for Channel 5 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + break; + } + case TIM_CHANNEL_6: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 6 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + else + { + /* Disable the OCREF clear feature for Channel 6 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + break; + } + default: + break; } - case TIM_CHANNEL_2: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 2 */ - SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); - } - else - { - /* Disable the OCREF clear feature for Channel 2 */ - CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); - } - break; - } - case TIM_CHANNEL_3: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 3 */ - SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); - } - else - { - /* Disable the OCREF clear feature for Channel 3 */ - CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); - } - break; - } - case TIM_CHANNEL_4: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 4 */ - SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); - } - else - { - /* Disable the OCREF clear feature for Channel 4 */ - CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); - } - break; - } - case TIM_CHANNEL_5: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 5 */ - SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); - } - else - { - /* Disable the OCREF clear feature for Channel 5 */ - CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); - } - break; - } - case TIM_CHANNEL_6: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 6 */ - SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); - } - else - { - /* Disable the OCREF clear feature for Channel 6 */ - CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); - } - break; - } - default: - break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -4831,6 +5548,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Process Locked */ @@ -4961,7 +5679,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo #if defined (TIM20) case TIM_CLOCKSOURCE_ITR9: #endif /* TIM20 */ +#if defined (HRTIM1) case TIM_CLOCKSOURCE_ITR10: +#endif /* HRTIM1 */ case TIM_CLOCKSOURCE_ITR11: { /* Check whether or not the timer instance supports internal trigger input */ @@ -4972,13 +5692,14 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo } default: + status = HAL_ERROR; break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -5528,7 +6249,7 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call default : /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; break; } } @@ -5594,14 +6315,14 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call default : /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; break; } } else { /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; } /* Release Lock */ @@ -5647,7 +6368,7 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID - * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transistion Error Callback ID + * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID * @retval status */ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) @@ -5662,136 +6383,168 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; break; case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; break; case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; break; case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; break; case HAL_TIM_PERIOD_ELAPSED_CB_ID : - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ + /* Legacy weak Period Elapsed Callback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; break; case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */ + /* Legacy weak Period Elapsed half complete Callback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; break; case HAL_TIM_TRIGGER_CB_ID : - htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ + /* Legacy weak Trigger Callback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; break; case HAL_TIM_TRIGGER_HALF_CB_ID : - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */ + /* Legacy weak Trigger half complete Callback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; break; case HAL_TIM_IC_CAPTURE_CB_ID : - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ + /* Legacy weak IC Capture Callback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; break; case HAL_TIM_IC_CAPTURE_HALF_CB_ID : - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */ + /* Legacy weak IC Capture half complete Callback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; break; case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ + /* Legacy weak OC Delay Elapsed Callback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ + /* Legacy weak PWM Pulse Finished Callback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */ + /* Legacy weak PWM Pulse Finished half complete Callback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; break; case HAL_TIM_ERROR_CB_ID : - htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ + /* Legacy weak Error Callback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; break; case HAL_TIM_COMMUTATION_CB_ID : - htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */ + /* Legacy weak Commutation Callback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; break; case HAL_TIM_COMMUTATION_HALF_CB_ID : - htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */ + /* Legacy weak Commutation half complete Callback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; break; case HAL_TIM_BREAK_CB_ID : - htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */ + /* Legacy weak Break Callback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; break; case HAL_TIM_BREAK2_CB_ID : - htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */ + /* Legacy weak Break2 Callback */ + htim->Break2Callback = HAL_TIMEx_Break2Callback; break; case HAL_TIM_ENCODER_INDEX_CB_ID : - htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback; /* Legacy weak Encoder Index Callback */ + /* Legacy weak Encoder Index Callback */ + htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback; break; case HAL_TIM_DIRECTION_CHANGE_CB_ID : - htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback; /* Legacy weak Direction Change Callback */ + /* Legacy weak Direction Change Callback */ + htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback; break; case HAL_TIM_INDEX_ERROR_CB_ID : - htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback; /* Legacy weak Index Error Callback */ + /* Legacy weak Index Error Callback */ + htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback; break; case HAL_TIM_TRANSITION_ERROR_CB_ID : - htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback; /* Legacy weak Transition Error Callback */ + /* Legacy weak Transition Error Callback */ + htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback; break; default : /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; break; } } @@ -5800,71 +6553,85 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; break; case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; break; case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; break; case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; break; default : /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; break; } } else { /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; } /* Release Lock */ @@ -5953,6 +6720,54 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) return htim->State; } +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM handle + * @retval Active channel + */ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) +{ + return htim->Channel; +} + +/** + * @brief Return actual state of the TIM channel. + * @param htim TIM handle + * @param Channel TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval TIM Channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + + return channel_state; +} + +/** + * @brief Return actual state of a DMA burst operation. + * @param htim TIM handle + * @retval DMA burst state + */ +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + + return htim->DMABurstState; +} + /** * @} */ @@ -5974,13 +6789,38 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + htim->State = HAL_TIM_STATE_READY; + } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->ErrorCallback(htim); #else HAL_TIM_ErrorCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** @@ -5988,27 +6828,45 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) * @param hdma pointer to DMA handle. * @retval None */ -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } } else { @@ -6033,8 +6891,6 @@ void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; @@ -6074,23 +6930,45 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } } else { @@ -6115,8 +6993,6 @@ void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; @@ -6156,7 +7032,10 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; + if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); @@ -6174,8 +7053,6 @@ static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedHalfCpltCallback(htim); #else @@ -6192,7 +7069,10 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; + if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); @@ -6210,8 +7090,6 @@ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerHalfCpltCallback(htim); #else @@ -6270,7 +7148,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) /** * @brief Timer Output Compare 1 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -6345,7 +7223,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 2 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -6421,7 +7299,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 3 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -6495,7 +7373,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 4 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -6572,7 +7450,7 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 5 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, @@ -6625,7 +7503,7 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, /** * @brief Timer Output Compare 6 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, @@ -6685,6 +7563,7 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; @@ -6729,7 +7608,8 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - if ((sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) || (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET)) + if ((sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) || \ + (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET)) { return HAL_ERROR; } @@ -6791,7 +7671,9 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, #if defined (TIM20) case TIM_TS_ITR9: #endif /* TIM20 */ +#if defined (HRTIM1) case TIM_TS_ITR10: +#endif /* HRTIM1 */ case TIM_TS_ITR11: { /* Check the parameter */ @@ -6800,9 +7682,11 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, } default: + status = HAL_ERROR; break; } - return HAL_OK; + + return status; } /** @@ -7189,24 +8073,24 @@ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelStat void TIM_ResetCallback(TIM_HandleTypeDef *htim) { /* Reset the TIM callback to the legacy weak callbacks */ - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */ - htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */ - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */ - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */ - htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ - htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */ - htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */ - htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */ - htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2Callback */ - htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback; /* Legacy weak Encoder Index Callback */ - htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback; /* Legacy weak Direction Change Callback */ - htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback; /* Legacy weak Index Error Callback */ - htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback; /* Legacy weak Transition Error Callback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + htim->TriggerCallback = HAL_TIM_TriggerCallback; + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + htim->ErrorCallback = HAL_TIM_ErrorCallback; + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + htim->BreakCallback = HAL_TIMEx_BreakCallback; + htim->Break2Callback = HAL_TIMEx_Break2Callback; + htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback; + htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback; + htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback; + htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback; } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ @@ -7222,4 +8106,3 @@ void TIM_ResetCallback(TIM_HandleTypeDef *htim) /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c index 5ddf9e5..0ffa8d1 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c @@ -13,6 +13,17 @@ * + Time OCRef clear configuration * + Timer remapping capabilities configuration * + Timer encoder index configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### TIMER Extended features ##### @@ -62,24 +73,16 @@ (#) Activate the TIM peripheral using one of the start functions: - (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT() - (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), + HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), + HAL_TIMEx_PWMN_Start_IT() (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() - (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), + HAL_TIMEx_HallSensor_Start_IT(). @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -109,9 +112,11 @@ */ /* End of private constants --------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); /* Exported functions --------------------------------------------------------*/ @@ -142,6 +147,9 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha */ /** * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @note When the timer instance is initialized in Hall Sensor Interface mode, + * timer channels 1 and channel 2 are reserved and cannot be used for + * other purpose. * @param htim TIM Hall Sensor Interface handle * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status @@ -227,6 +235,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen htim->Instance->CR2 &= ~TIM_CR2_MMS; htim->Instance->CR2 |= TIM_TRGO_OC2REF; + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -260,6 +277,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) HAL_TIMEx_HallSensor_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -307,17 +333,44 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -337,12 +390,19 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1, 2 and 3 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -355,20 +415,47 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the capture compare Interrupts 1 event */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -388,7 +475,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts event */ @@ -397,6 +485,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -411,31 +505,39 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + /* Set the TIM channel state */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { - if (((uint32_t)pData == 0U) && (Length > 0U)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } + /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Set the DMA Input Capture 1 Callbacks */ @@ -447,14 +549,22 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /* Enable the DMA channel for Capture 1*/ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the capture compare 1 Interrupt */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -474,7 +584,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); @@ -482,9 +593,14 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -532,6 +648,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); @@ -539,8 +664,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -575,6 +707,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -593,11 +728,21 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -630,27 +775,38 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann } default: + status = HAL_ERROR; break; } - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (status == HAL_OK) { - __HAL_TIM_ENABLE(htim); + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } } /* Return function status */ - return HAL_OK; + return status; } /** @@ -667,7 +823,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpccer; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -702,27 +860,34 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe } default: + status = HAL_ERROR; break; } - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET) + if (status == HAL_OK) { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - /* Return function status */ - return HAL_OK; + return status; } /** @@ -741,29 +906,31 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if (((uint32_t)pData == 0U) && (Length > 0U)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } switch (Channel) @@ -771,15 +938,17 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ @@ -790,15 +959,17 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ @@ -809,15 +980,17 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ @@ -828,15 +1001,17 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan case TIM_CHANNEL_4: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ @@ -845,24 +1020,35 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan } default: + status = HAL_ERROR; break; } - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (status == HAL_OK) { - __HAL_TIM_ENABLE(htim); + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } } /* Return function status */ - return HAL_OK; + return status; } /** @@ -879,6 +1065,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -917,23 +1105,27 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann } default: + status = HAL_ERROR; break; } - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -988,6 +1180,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); @@ -995,8 +1196,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1030,6 +1238,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1048,11 +1259,21 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -1084,27 +1305,38 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan } default: + status = HAL_ERROR; break; } - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (status == HAL_OK) { - __HAL_TIM_ENABLE(htim); + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1121,6 +1353,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpccer; /* Check the parameters */ @@ -1157,27 +1390,34 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann } default: + status = HAL_ERROR; break; } - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET) + if (status == HAL_OK) { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - /* Return function status */ - return HAL_OK; + return status; } /** @@ -1196,44 +1436,49 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if (((uint32_t)pData == 0U) && (Length > 0U)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } + switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ @@ -1244,15 +1489,17 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ @@ -1263,15 +1510,17 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ @@ -1282,15 +1531,17 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha case TIM_CHANNEL_4: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -1299,24 +1550,35 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha } default: + status = HAL_ERROR; break; } - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (status == HAL_OK) { - __HAL_TIM_ENABLE(htim); + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1333,6 +1595,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -1371,23 +1635,27 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan } default: + status = HAL_ERROR; break; } - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1415,8 +1683,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM One Pulse signal generation on the complementary * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be enabled + * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1424,11 +1694,33 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - /* Enable the complementary One Pulse output */ + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); @@ -1440,8 +1732,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be disabled + * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1449,12 +1743,14 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - /* Disable the complementary One Pulse output */ + /* Disable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); @@ -1462,6 +1758,12 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1469,8 +1771,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be enabled + * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1478,17 +1782,39 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - /* Enable the complementary One Pulse output */ + /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); @@ -1500,8 +1826,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be disabled + * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1509,6 +1837,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); @@ -1518,8 +1848,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - /* Disable the complementary One Pulse output */ + /* Disable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); @@ -1527,6 +1858,12 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1613,14 +1950,19 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || - (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR10) || - (InputTrigger == TIM_TS_ITR11)) + (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) +#elif defined(TIM20) + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || + (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || + (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || + (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11)) #else if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || - (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11)) + (InputTrigger == TIM_TS_ITR11)) #endif /* TIM5 && TIM20 */ { /* Select the Input trigger */ @@ -1699,14 +2041,19 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || - (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR10) || - (InputTrigger == TIM_TS_ITR11)) + (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) +#elif defined(TIM20) + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || + (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || + (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || + (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11)) #else if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || - (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11)) + (InputTrigger == TIM_TS_ITR11)) #endif /* TIM5 && TIM20 */ { /* Select the Input trigger */ @@ -1786,14 +2133,19 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint3 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || - (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR10) || - (InputTrigger == TIM_TS_ITR11)) + (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) +#elif defined(TIM20) + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || + (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || + (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || + (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11)) #else if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || - (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11)) + (InputTrigger == TIM_TS_ITR11)) #endif /* TIM5 && TIM20 */ { /* Select the Input trigger */ @@ -1840,7 +2192,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, uint32_t tmpsmcr; /* Check the parameters */ - assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); @@ -1873,16 +2225,19 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; - /* Reset the MSM Bit */ - tmpsmcr &= ~TIM_SMCR_MSM; - /* Set master mode */ - tmpsmcr |= sMasterConfig->MasterSlaveMode; - /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; - /* Update TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; @@ -1898,6 +2253,9 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, * @param htim TIM handle * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that * contains the BDTR Register configuration information for the TIM peripheral. + * @note Interrupts can be generated when an active level is detected on the + * break input, the break 2 input or the system break input. Break + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, @@ -1987,11 +2345,12 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmporx; - uint32_t bkin_enable_mask = 0U; - uint32_t bkin_polarity_mask = 0U; - uint32_t bkin_enable_bitpos = 0U; - uint32_t bkin_polarity_bitpos = 0U; + uint32_t bkin_enable_mask; + uint32_t bkin_polarity_mask; + uint32_t bkin_enable_bitpos; + uint32_t bkin_polarity_bitpos; /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); @@ -2051,6 +2410,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, bkin_enable_mask = TIM1_AF1_BKCMP5E; bkin_enable_bitpos = TIM1_AF1_BKCMP5E_Pos; /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */ + bkin_polarity_mask = 0U; + bkin_polarity_bitpos = 0U; break; } #endif /* COMP5 */ @@ -2060,6 +2421,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, bkin_enable_mask = TIM1_AF1_BKCMP6E; bkin_enable_bitpos = TIM1_AF1_BKCMP6E_Pos; /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */ + bkin_polarity_mask = 0U; + bkin_polarity_bitpos = 0U; break; } #endif /* COMP7 */ @@ -2069,12 +2432,20 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, bkin_enable_mask = TIM1_AF1_BKCMP7E; bkin_enable_bitpos = TIM1_AF1_BKCMP7E_Pos; /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */ + bkin_polarity_mask = 0U; + bkin_polarity_bitpos = 0U; break; } #endif /* COMP7 */ default: + { + bkin_enable_mask = 0U; + bkin_polarity_mask = 0U; + bkin_enable_bitpos = 0U; + bkin_polarity_bitpos = 0U; break; + } } switch (BreakInput) @@ -2114,12 +2485,13 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, break; } default: + status = HAL_ERROR; break; } __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -2501,6 +2873,7 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Chan */ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpbdtr; /* Check the parameters */ @@ -2535,10 +2908,11 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B break; } default: + status = HAL_ERROR; break; } - return HAL_OK; + return status; } /** @@ -2554,6 +2928,7 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B */ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tickstart; /* Check the parameters */ @@ -2570,15 +2945,17 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t Br /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); - do + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) { - if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != TIM_BDTR_BKDSRM) + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) { - return HAL_OK; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) + { + return HAL_TIMEOUT; + } } - } while ((HAL_GetTick() - tickstart) <= TIM_BREAKINPUT_REARM_TIMEOUT); - - return HAL_TIMEOUT; + } } break; } @@ -2591,23 +2968,26 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t Br /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); - do + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) { - if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != TIM_BDTR_BK2DSRM) + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) { - return HAL_OK; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) + { + return HAL_TIMEOUT; + } } - } while ((HAL_GetTick() - tickstart) <= TIM_BREAKINPUT_REARM_TIMEOUT); - - return HAL_TIMEOUT; + } } break; } default: + status = HAL_ERROR; break; } - return HAL_OK; + return status; } /** @@ -2624,8 +3004,9 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t Br * @note Macros @ref __HAL_TIM_CALC_PERIOD_DITHER() __HAL_TIM_CALC_DELAY_DITHER() __HAL_TIM_CALC_PULSE_DITHER() * can be used to calculate period (ARR) and delay (CCRx) value. * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part. - * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD() __HAL_TIM_GET_COMPARE() - * and if necessary update Init structure field htim->Init.Period . + * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part. + * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD() + * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period . * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim) @@ -2648,8 +3029,8 @@ HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim) * - ARR and CCRx values are limited to 0xFFEF in dithering mode * (corresponds to 4094 for the integer part and 15 for the dithered part). * @note Disabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part. - * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD() __HAL_TIM_GET_COMPARE() - * and if necessary update Init structure field htim->Init.Period . + * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD() + * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period . * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim) @@ -3110,6 +3491,28 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) return htim->State; } +/** + * @brief Return actual state of the TIM complementary channel. + * @param htim TIM handle + * @param ChannelN TIM Complementary channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @retval TIM Complementary channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); + + channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); + + return channel_state; +} /** * @} */ @@ -3119,7 +3522,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Functions TIMEx Private Functions +/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions * @{ */ @@ -3162,6 +3565,103 @@ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) } +/** + * @brief TIM DMA Delay Pulse complete callback (complementary channel). + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA error callback (complementary channel) + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx to select the TIM peripheral @@ -3199,5 +3699,3 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c index 8a3a042..3a2509f 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -39,7 +50,8 @@ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. @@ -75,8 +87,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_UART_RegisterCallback() to register a user callback. - Function @ref HAL_UART_RegisterCallback() allows to register following callbacks: + Use Function HAL_UART_RegisterCallback() to register a user callback. + Function HAL_UART_RegisterCallback() allows to register following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. (+) TxCpltCallback : Tx Complete Callback. (+) RxHalfCpltCallback : Rx Half Complete Callback. @@ -94,9 +106,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default + Use function HAL_UART_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. @@ -114,13 +126,17 @@ (+) MspDeInitCallback : UART MspDeInit. [..] - By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + For specific callback RxEventCallback, use dedicated registration/reset functions: + respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback(). + + [..] + By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback(). + examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init() - and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_UART_Init() + and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -129,8 +145,8 @@ in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit() - or @ref HAL_UART_Init() function. + using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit() + or HAL_UART_Init() function. [..] When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or @@ -140,17 +156,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -172,25 +177,22 @@ /** @defgroup UART_Private_Constants UART Private Constants * @{ */ -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \ - USART_CR1_FIFOEN )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \ + USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \ - USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \ + USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ #define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */ #define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */ #define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ #define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ - /** * @} */ /* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup UART_Private_Functions * @{ @@ -220,6 +222,16 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); * @} */ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup UART_Private_variables + * @{ + */ +const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; +/** + * @} + */ + +/* Exported Constants --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup UART_Exported_Functions UART Exported Functions @@ -643,6 +655,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_RESET; huart->RxState = HAL_UART_STATE_RESET; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; __HAL_UNLOCK(huart); @@ -842,55 +855,57 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR switch (CallbackID) { case HAL_UART_TX_HALFCOMPLETE_CB_ID : - huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ break; case HAL_UART_TX_COMPLETE_CB_ID : - huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ break; case HAL_UART_RX_HALFCOMPLETE_CB_ID : - huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ break; case HAL_UART_RX_COMPLETE_CB_ID : - huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ break; case HAL_UART_ERROR_CB_ID : - huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_UART_ABORT_COMPLETE_CB_ID : - huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : - huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ break; case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : - huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ break; case HAL_UART_WAKEUP_CB_ID : - huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ break; case HAL_UART_RX_FIFO_FULL_CB_ID : - huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ break; case HAL_UART_TX_FIFO_EMPTY_CB_ID : - huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ break; case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ + huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ break; case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ + huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ break; default : @@ -930,6 +945,74 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR return status; } + +/** + * @brief Register a User UART Rx Event Callback + * To be used instead of the weak predefined callback + * @param huart Uart handle + * @param pCallback Pointer to the Rx Event Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = pCallback; + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief UnRegister the UART Rx Event Callback + * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback + * @param huart Uart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + return status; +} + #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** @@ -995,16 +1078,23 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR (+) HAL_UART_AbortTransmitCpltCallback() (+) HAL_UART_AbortReceiveCpltCallback() + (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced + reception services: + (+) HAL_UARTEx_RxEventCallback() + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side. + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. If user wants to abort it, Abort services should be called by user. (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. -@- In the Half duplex communication, it is forbidden to run the transmit and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. @@ -1015,20 +1105,23 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR /** * @brief Send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. * @note When FIFO mode is enabled, writing a data in the TDR register adds one * data to the TXFIFO. Write operations to the TDR register are performed * when TXFNF flag is set. From hardware perspective, TXFNF flag and * TXE are mapped on the same bit-field. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint8_t *pdata8bits; - uint16_t *pdata16bits; + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; uint32_t tickstart; /* Check that a Tx process is not already ongoing */ @@ -1044,7 +1137,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); huart->TxXferSize = Size; @@ -1054,7 +1147,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { pdata8bits = NULL; - pdata16bits = (uint16_t *) pData; + pdata16bits = (const uint16_t *) pData; } else { @@ -1062,6 +1155,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u pdata16bits = NULL; } + __HAL_UNLOCK(huart); + while (huart->TxXferCount > 0U) { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) @@ -1089,8 +1184,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - __HAL_UNLOCK(huart); - return HAL_OK; } else @@ -1101,13 +1194,16 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO * is not empty. Read operations from the RDR register are performed when * RXFNE flag is set. From hardware perspective, RXFNE flag and * RXNE are mapped on the same bit-field. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @param Timeout Timeout duration. * @retval HAL status */ @@ -1130,8 +1226,9 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); huart->RxXferSize = Size; @@ -1153,6 +1250,8 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui pdata16bits = NULL; } + __HAL_UNLOCK(huart); + /* as long as data have to be received */ while (huart->RxXferCount > 0U) { @@ -1176,8 +1275,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - __HAL_UNLOCK(huart); - return HAL_OK; } else @@ -1188,12 +1285,15 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui /** * @brief Send an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) @@ -1229,7 +1329,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData __HAL_UNLOCK(huart); /* Enable the TX FIFO threshold interrupt */ - SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); } else { @@ -1246,7 +1346,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData __HAL_UNLOCK(huart); /* Enable the Transmit Data Register Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); } return HAL_OK; @@ -1259,9 +1359,12 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData /** * @brief Receive an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -1276,58 +1379,20 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, __HAL_LOCK(huart); - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; - huart->RxXferCount = Size; - huart->RxISR = NULL; + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - /* Computation of UART mask to apply to RDR register */ - UART_MASK_COMPUTATION(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Configure Rx interrupt processing*/ - if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) + if (!(IS_LPUART_INSTANCE(huart->Instance))) { - /* Set the Rx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) { - huart->RxISR = UART_RxISR_16BIT_FIFOEN; + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); } - else - { - huart->RxISR = UART_RxISR_8BIT_FIFOEN; - } - - __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); - } - else - { - /* Set the Rx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - huart->RxISR = UART_RxISR_16BIT; - } - else - { - huart->RxISR = UART_RxISR_8BIT; - } - - __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); } - return HAL_OK; + return (UART_Start_Receive_IT(huart, pData, Size)); } else { @@ -1337,12 +1402,15 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, /** * @brief Send an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) @@ -1396,7 +1464,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); return HAL_OK; } @@ -1410,9 +1478,12 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat * @brief Receive an amount of data in DMA mode. * @note When the UART parity is enabled (PCE = 1), the received data contain * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -1427,53 +1498,20 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData __HAL_LOCK(huart); - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - if (huart->hdmarx != NULL) + if (!(IS_LPUART_INSTANCE(huart->Instance))) { - /* Set the UART DMA transfer complete callback */ - huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmarx->XferErrorCallback = UART_DMAError; - - /* Set the DMA abort callback */ - huart->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - __HAL_UNLOCK(huart); - - /* Restore huart->gState to ready */ - huart->gState = HAL_UART_STATE_READY; - - return HAL_ERROR; + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); } } - __HAL_UNLOCK(huart); - /* Enable the UART Parity Error Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - return HAL_OK; + return (UART_Start_Receive_DMA(huart, pData, Size)); } else { @@ -1497,17 +1535,17 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) (gstate == HAL_UART_STATE_BUSY_TX)) { /* Disable the UART DMA Tx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); } if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && (rxstate == HAL_UART_STATE_BUSY_RX)) { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the UART DMA Rx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } __HAL_UNLOCK(huart); @@ -1527,19 +1565,22 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) if (huart->gState == HAL_UART_STATE_BUSY_TX) { /* Enable the UART DMA Tx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); } if (huart->RxState == HAL_UART_STATE_BUSY_RX) { /* Clear the Overrun flag before resuming the Rx transfer */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Enable the UART DMA Rx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } __HAL_UNLOCK(huart); @@ -1568,7 +1609,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && (gstate == HAL_UART_STATE_BUSY_TX)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel */ if (huart->hdmatx != NULL) @@ -1592,7 +1633,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && (rxstate == HAL_UART_STATE_BUSY_RX)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) @@ -1630,13 +1671,21 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) { /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | + USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); - /* Disable the UART DMA Tx request if enabled */ + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) @@ -1658,10 +1707,11 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) } } - /* Disable the UART DMA Rx request if enabled */ + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) @@ -1702,6 +1752,7 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -1723,13 +1774,14 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) { /* Disable TCIE, TXEIE and TXFTIE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - /* Disable the UART DMA Tx request if enabled */ + /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) @@ -1781,13 +1833,20 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) { /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); - /* Disable the UART DMA Rx request if enabled */ + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) @@ -1820,6 +1879,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; return HAL_OK; } @@ -1843,8 +1903,15 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) uint32_t abortcplt = 1U; /* Disable interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | USART_CR1_TXEIE_TXFNFIE)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | + USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ @@ -1877,11 +1944,11 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) } } - /* Disable the UART DMA Tx request if enabled */ + /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { /* Disable DMA Tx at UART level */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmatx != NULL) @@ -1901,10 +1968,11 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) } } - /* Disable the UART DMA Rx request if enabled */ + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmarx != NULL) @@ -1954,6 +2022,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* As no DMA to be aborted, call directly user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -1985,13 +2054,14 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) { /* Disable interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - /* Disable the UART DMA Tx request if enabled */ + /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmatx != NULL) @@ -2075,13 +2145,20 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - /* Disable the UART DMA Rx request if enabled */ + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmarx != NULL) @@ -2113,6 +2190,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* As no DMA to be aborted, call directly user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -2137,6 +2215,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* As no DMA to be aborted, call directly user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -2166,7 +2245,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) uint32_t errorcode; /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); if (errorflags == 0U) { /* UART in mode Receiver ---------------------------------------------------*/ @@ -2185,7 +2264,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* If some errors occur */ if ((errorflags != 0U) && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) - || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) @@ -2221,10 +2300,18 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) huart->ErrorCode |= HAL_UART_ERROR_ORE; } - /* Call UART Error Call back function if need be --------------------------*/ + /* UART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + huart->ErrorCode |= HAL_UART_ERROR_RTO; + } + + /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) { - /* UART in mode Receiver ---------------------------------------------------*/ + /* UART in mode Receiver --------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || ((cr3its & USART_CR3_RXFTIE) != 0U))) @@ -2235,21 +2322,25 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } } - /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ errorcode = huart->ErrorCode; if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || - ((errorcode & HAL_UART_ERROR_ORE) != 0U)) + ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); - /* Disable the UART DMA Rx request if enabled */ + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) @@ -2308,6 +2399,93 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } /* End if some error occurs */ + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + && ((isrflags & USART_ISR_IDLE) != 0U) + && ((cr1its & USART_ISR_IDLE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + + /* Check if DMA mode is enabled in UART */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* DMA mode enabled */ + /* Check received length : If all expected data are received, do nothing, + (DMA cplt callback will be called). + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); + if ((nb_remaining_rx_data > 0U) + && (nb_remaining_rx_data < huart->RxXferSize)) + { + /* Reception is not complete */ + huart->RxXferCount = nb_remaining_rx_data; + + /* In Normal mode, end DMA xfer and HAL UART Rx process*/ + if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Last bytes received, so no need as the abort is immediate */ + (void)HAL_DMA_Abort(huart->hdmarx); + } +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; + } + else + { + /* DMA mode not enabled */ + /* Check received length : If all expected data are received, do nothing. + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; + if ((huart->RxXferCount > 0U) + && (nb_rx_data > 0U)) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxEventCallback(huart, nb_rx_data); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, nb_rx_data); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; + } + } + /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) { @@ -2492,6 +2670,24 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) */ } +/** + * @brief Reception Event Callback (Rx event notification called after use of advanced reception service). + * @param huart UART handle + * @param Size Number of data available in application reception buffer (indicates a position in + * reception buffer until which, data are available) + * @retval None + */ +__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + UNUSED(Size); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxEventCallback can be implemented in the user file. + */ +} + /** * @} */ @@ -2505,6 +2701,9 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) =============================================================================== [..] This subsection provides a set of functions allowing to control the UART. + (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly + (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature + (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode @@ -2518,6 +2717,99 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) * @{ */ +/** + * @brief Update on the fly the receiver timeout value in RTOR register. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout + * value must be less or equal to 0x0FFFFFFFF. + * @retval None + */ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue)); + MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); + } +} + +/** + * @brief Enable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Set the USART RTOEN bit */ + SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Disable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear the USART RTOEN bit */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + } + else + { + return HAL_ERROR; + } +} + /** * @brief Enable UART in mute mode (does not mean UART enters mute mode; * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). @@ -2531,7 +2823,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Enable USART mute mode by setting the MME bit in the CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_MME); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME); huart->gState = HAL_UART_STATE_READY; @@ -2551,7 +2843,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Disable USART mute mode by clearing the MME bit in the CR1 register */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); huart->gState = HAL_UART_STATE_READY; @@ -2580,10 +2872,10 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Clear TE and RE bits */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_TE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE); huart->gState = HAL_UART_STATE_READY; @@ -2603,10 +2895,10 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Clear TE and RE bits */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_RE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE); huart->gState = HAL_UART_STATE_READY; @@ -2718,6 +3010,7 @@ void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */ } #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ @@ -2732,9 +3025,10 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; - uint32_t usartdiv = 0x00000000U; + uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; - uint32_t lpuart_ker_ck_pres = 0x00000000U; + uint32_t lpuart_ker_ck_pres; + uint32_t pclk; /* Check the parameters */ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); @@ -2763,7 +3057,6 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; - tmpreg |= (uint32_t)huart->FifoMode; MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); /*-------------------------- USART CR2 Configuration -----------------------*/ @@ -2800,27 +3093,30 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: - lpuart_ker_ck_pres = (HAL_RCC_GetPCLK1Freq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK1Freq(); break; case UART_CLOCKSOURCE_HSI: - lpuart_ker_ck_pres = ((uint32_t)HSI_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); + pclk = (uint32_t) HSI_VALUE; break; case UART_CLOCKSOURCE_SYSCLK: - lpuart_ker_ck_pres = (HAL_RCC_GetSysClockFreq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetSysClockFreq(); break; case UART_CLOCKSOURCE_LSE: - lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); + pclk = (uint32_t) LSE_VALUE; break; - case UART_CLOCKSOURCE_UNDEFINED: default: + pclk = 0U; ret = HAL_ERROR; break; } - /* if proper clock source reported */ - if (lpuart_ker_ck_pres != 0U) + /* If proper clock source reported */ + if (pclk != 0U) { - /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ + /* Compute clock after Prescaler */ + lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); + + /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) { @@ -2828,27 +3124,9 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) } else { - switch (clocksource) - { - case UART_CLOCKSOURCE_PCLK1: - usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); - break; - case UART_CLOCKSOURCE_HSI: - usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - break; - case UART_CLOCKSOURCE_SYSCLK: - usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); - break; - case UART_CLOCKSOURCE_LSE: - usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - break; - case UART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; - } - - /* It is forbidden to write values lower than 0x300 in the LPUART_BRR register */ + /* Check computed UsartDiv value is in allocated range + (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ + usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) { huart->Instance->BRR = usartdiv; @@ -2857,8 +3135,9 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { ret = HAL_ERROR; } - } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ - } /* if (lpuart_ker_ck_pres != 0) */ + } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || + (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ + } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) @@ -2866,36 +3145,40 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK1Freq(); break; case UART_CLOCKSOURCE_PCLK2: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK2Freq(); break; case UART_CLOCKSOURCE_HSI: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = (uint32_t) HSI_VALUE; break; case UART_CLOCKSOURCE_SYSCLK: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetSysClockFreq(); break; case UART_CLOCKSOURCE_LSE: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = (uint32_t) LSE_VALUE; break; - case UART_CLOCKSOURCE_UNDEFINED: default: + pclk = 0U; ret = HAL_ERROR; break; } /* USARTDIV must be greater than or equal to 0d16 */ - if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + if (pclk != 0U) { - brrtemp = (uint16_t)(usartdiv & 0xFFF0U); - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - huart->Instance->BRR = brrtemp; - } - else - { - ret = HAL_ERROR; + usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + huart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } } } else @@ -2903,34 +3186,38 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK1Freq(); break; case UART_CLOCKSOURCE_PCLK2: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK2Freq(); break; case UART_CLOCKSOURCE_HSI: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = (uint32_t) HSI_VALUE; break; case UART_CLOCKSOURCE_SYSCLK: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetSysClockFreq(); break; case UART_CLOCKSOURCE_LSE: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = (uint32_t) LSE_VALUE; break; - case UART_CLOCKSOURCE_UNDEFINED: default: + pclk = 0U; ret = HAL_ERROR; break; } - /* USARTDIV must be greater than or equal to 0d16 */ - if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + if (pclk != 0U) { - huart->Instance->BRR = usartdiv; - } - else - { - ret = HAL_ERROR; + /* USARTDIV must be greater than or equal to 0d16 */ + usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + huart->Instance->BRR = (uint16_t)usartdiv; + } + else + { + ret = HAL_ERROR; + } } } @@ -3031,7 +3318,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Check if the Transmitter is enabled */ @@ -3059,6 +3346,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; __HAL_UNLOCK(huart); @@ -3066,10 +3354,11 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) } /** - * @brief Handle UART Communication Timeout. + * @brief This function handles UART Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param huart UART handle. * @param Flag Specifies the UART flag to check - * @param Status Flag status (SET or RESET) + * @param Status The actual Flag status (SET or RESET) * @param Tickstart Tick start value * @param Timeout Timeout duration * @retval HAL status @@ -3085,9 +3374,11 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | + USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; @@ -3096,11 +3387,176 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ return HAL_TIMEOUT; } + + if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | + USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ErrorCode = HAL_UART_ERROR_RTO; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } } } return HAL_OK; } +/** + * @brief Start Receive operation in interrupt mode. + * @note This function could be called by all HAL UART API providing reception in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + huart->RxXferCount = Size; + huart->RxISR = NULL; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Configure Rx interrupt processing */ + if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT_FIFOEN; + } + else + { + huart->RxISR = UART_RxISR_8BIT_FIFOEN; + } + + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + } + else + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT; + } + else + { + huart->RxISR = UART_RxISR_8BIT; + } + + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + return HAL_OK; +} + +/** + * @brief Start Receive operation in DMA mode. + * @note This function could be called by all HAL UART API providing reception in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + if (huart->hdmarx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + __HAL_UNLOCK(huart); + + /* Restore huart->RxState to ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error Interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; +} + /** * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). @@ -3110,8 +3566,8 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { /* Disable TXEIE, TCIE, TXFT interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; @@ -3126,11 +3582,18 @@ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* Reset RxIsr function pointer */ huart->RxISR = NULL; @@ -3153,10 +3616,10 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } /* DMA Circular mode */ else @@ -3204,24 +3667,46 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) huart->RxXferCount = 0U; /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + + /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } } + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); #else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } } /** @@ -3233,13 +3718,29 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Half complete callback*/ - huart->RxHalfCpltCallback(huart); + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize / 2U); #else - /*Call legacy weak Rx Half complete callback*/ - HAL_UART_RxHalfCpltCallback(huart); + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Half Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + huart->RxHalfCpltCallback(huart); +#else + /*Call legacy weak Rx Half complete callback*/ + HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } } /** @@ -3344,6 +3845,7 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* Call user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -3395,6 +3897,7 @@ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* Call user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -3462,6 +3965,7 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* Call user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -3474,7 +3978,7 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) } /** - * @brief TX interrrupt handler for 7 or 8 bits data word length . + * @brief TX interrupt handler for 7 or 8 bits data word length . * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. @@ -3488,10 +3992,10 @@ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) if (huart->TxXferCount == 0U) { /* Disable the UART Transmit Data Register Empty Interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } else { @@ -3503,7 +4007,7 @@ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) } /** - * @brief TX interrrupt handler for 9 bits data word length. + * @brief TX interrupt handler for 9 bits data word length. * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. @@ -3511,7 +4015,7 @@ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) */ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) { - uint16_t *tmp; + const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) @@ -3519,14 +4023,14 @@ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) if (huart->TxXferCount == 0U) { /* Disable the UART Transmit Data Register Empty Interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } else { - tmp = (uint16_t *) huart->pTxBuffPtr; + tmp = (const uint16_t *) huart->pTxBuffPtr; huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; @@ -3535,7 +4039,7 @@ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) } /** - * @brief TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. @@ -3553,10 +4057,10 @@ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) if (huart->TxXferCount == 0U) { /* Disable the TX FIFO threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); break; /* force exit loop */ } @@ -3575,7 +4079,7 @@ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) } /** - * @brief TX interrrupt handler for 9 bits data word length and FIFO mode is enabled. + * @brief TX interrupt handler for 9 bits data word length and FIFO mode is enabled. * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. @@ -3583,7 +4087,7 @@ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) */ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { - uint16_t *tmp; + const uint16_t *tmp; uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ @@ -3594,16 +4098,16 @@ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) if (huart->TxXferCount == 0U) { /* Disable the TX FIFO threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); break; /* force exit loop */ } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) { - tmp = (uint16_t *) huart->pTxBuffPtr; + tmp = (const uint16_t *) huart->pTxBuffPtr; huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; @@ -3625,7 +4129,7 @@ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { /* Disable the UART Transmit Complete Interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; @@ -3643,7 +4147,7 @@ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) } /** - * @brief RX interrrupt handler for 7 or 8 bits data word length . + * @brief RX interrupt handler for 7 or 8 bits data word length . * @param huart UART handle. * @retval None */ @@ -3663,10 +4167,10 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -3674,13 +4178,40 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); #else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } } } else @@ -3691,7 +4222,7 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) } /** - * @brief RX interrrupt handler for 9 bits data word length . + * @brief RX interrupt handler for 9 bits data word length . * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. @@ -3715,10 +4246,10 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -3726,13 +4257,40 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); #else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } } } else @@ -3743,7 +4301,7 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) } /** - * @brief RX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @brief RX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. @@ -3753,26 +4311,75 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { uint16_t uhMask = huart->Mask; uint16_t uhdata; - uint16_t nb_rx_data; + uint16_t nb_rx_data; uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) { - for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) + nb_rx_data = huart->NbRxDataToProcess; + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); huart->pRxBuffPtr++; huart->RxXferCount--; + isrflags = READ_REG(huart->Instance->ISR); + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -3780,13 +4387,40 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); #else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } } } @@ -3798,13 +4432,13 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) { /* Disable the UART RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_8BIT; /* Enable the UART Data Register Not Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); } } else @@ -3815,7 +4449,7 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) } /** - * @brief RX interrrupt handler for 9 bits data word length and FIFO mode is enabled. + * @brief RX interrupt handler for 9 bits data word length and FIFO mode is enabled. * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. @@ -3826,27 +4460,76 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) uint16_t *tmp; uint16_t uhMask = huart->Mask; uint16_t uhdata; - uint16_t nb_rx_data; + uint16_t nb_rx_data; uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) { - for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) + nb_rx_data = huart->NbRxDataToProcess; + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); tmp = (uint16_t *) huart->pRxBuffPtr ; *tmp = (uint16_t)(uhdata & uhMask); huart->pRxBuffPtr += 2U; huart->RxXferCount--; + isrflags = READ_REG(huart->Instance->ISR); + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -3854,13 +4537,40 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); #else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } } } @@ -3872,13 +4582,13 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) { /* Disable the UART RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_16BIT; /* Enable the UART Data Register Not Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); } } else @@ -3901,4 +4611,3 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c index b5a765c..c980cee 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c @@ -9,6 +9,17 @@ * + Peripheral Control functions * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### UART peripheral extended features ##### @@ -27,17 +38,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -332,13 +332,45 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold + [..] This subsection also provides a set of additional functions providing enhanced reception + services to user. (For example, these functions allow application to handle use cases + where number of data to be received is unknown). + + (#) Compared to standard reception services which only consider number of received + data elements as reception completion criteria, these functions also consider additional events + as triggers for updating reception status to caller : + (+) Detection of inactivity period (RX line has not been active for a given period). + (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + for 1 frame time, after last received byte. + (++) RX inactivity detected by RTO, i.e. line has been in idle state + for a programmable time, after last received byte. + (+) Detection that a specific character has been received. + + (#) There are two mode of transfer: + (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + or till IDLE event occurs. Reception is handled only during function execution. + When function exits, no data reception could occur. HAL status and number of actually received data elements, + are returned by function after finishing transfer. + (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. + These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. + The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. + + (#) Blocking mode API: + (+) HAL_UARTEx_ReceiveToIdle() + + (#) Non-Blocking mode API with Interrupt: + (+) HAL_UARTEx_ReceiveToIdle_IT() + + (#) Non-Blocking mode API with DMA: + (+) HAL_UARTEx_ReceiveToIdle_DMA() + @endverbatim * @{ */ - - - /** * @brief By default in multiprocessor mode, when the wake up method is set * to address mark, the UART handles only 4-bit long addresses detection; @@ -419,7 +451,7 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Wait until REACK flag is set */ @@ -451,7 +483,7 @@ HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) __HAL_LOCK(huart); /* Set UESM bit */ - SET_BIT(huart->Instance->CR1, USART_CR1_UESM); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM); /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -470,7 +502,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) __HAL_LOCK(huart); /* Clear UESM bit */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -655,6 +687,259 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 return HAL_OK; } +/** + * @brief Receive an amount of data in blocking mode till either the expected number of data + * is received or an IDLE event occurs. + * @note HAL_OK is returned if reception is completed (expected number of data has been received) + * or if reception is stopped after IDLE event (less than the expected number of data has been received) + * In this case, RxLen output parameter indicates number of data available in reception buffer. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @param RxLen Number of data elements finally received + * (could be lower than Size, in case reception ends on IDLE event) + * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + __HAL_LOCK(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + __HAL_UNLOCK(huart); + + /* Initialize output number of received elements */ + *RxLen = 0U; + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + /* Check if IDLE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + { + /* Clear IDLE flag in ISR */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + + /* If Set, but no data ever received, clear flag without exiting loop */ + /* If Set, and data has already been received, this means Idle Event is valid : End reception */ + if (*RxLen > 0U) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + } + + /* Check if RXNE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) + { + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + /* Increment number of received elements */ + *RxLen += 1U; + huart->RxXferCount--; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + + /* Set number of received elements in output parameter : RxLen */ + *RxLen = huart->RxXferSize - huart->RxXferCount; + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode till either the expected number of data + * is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + __HAL_LOCK(huart); + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + + status = UART_Start_Receive_IT(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode till either the expected number + * of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + __HAL_LOCK(huart); + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + + status = UART_Start_Receive_DMA(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + } + + return status; + } + else + { + return HAL_BUSY; + } +} + /** * @} */ @@ -697,8 +982,8 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) uint8_t tx_fifo_depth; uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; - uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; - uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) { @@ -711,8 +996,10 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) tx_fifo_depth = TX_FIFO_DEPTH; rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); - huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; - huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; + huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + (uint16_t)denominator[tx_fifo_threshold]; + huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + (uint16_t)denominator[rx_fifo_threshold]; } } /** @@ -729,4 +1016,3 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c index 3b85cf9..b40c47c 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -83,7 +82,7 @@ /* Check of parameters for configuration of ADC hierarchical scope: */ /* common to several ADC instances. */ #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ - ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \ + (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \ @@ -103,19 +102,19 @@ /* Check of parameters for configuration of ADC hierarchical scope: */ /* ADC instance. */ #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ - ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ + (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ ) #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ - ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ + (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ ) #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \ - ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \ + (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \ || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \ ) @@ -123,7 +122,7 @@ /* ADC group regular */ #if defined(STM32G474xx) || defined(STM32G484xx) #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ - ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ @@ -172,13 +171,14 @@ ) \ ) \ ) -#elif defined(STM32G473xx) +#elif defined(STM32G473xx) || defined(STM32G483xx) #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ - ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ @@ -213,9 +213,46 @@ ) \ ) \ ) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) +#elif defined(STM32G471xx) #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ - ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \ + || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ + && ( \ + ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ + ) \ + ) \ + || (((__ADC_INSTANCE__) == ADC3) \ + && ( \ + ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) \ + ) \ + ) \ + ) +#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) +#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ + (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ @@ -235,26 +272,67 @@ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ ) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) +#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ + (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \ + || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ + && ( \ + ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ + ) \ + ) \ + || (((__ADC_INSTANCE__) == ADC3) \ + && ( \ + ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) \ + ) \ + ) \ + ) #endif #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ - ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ + (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ ) #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ - ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ + (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ ) #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \ - ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \ + (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \ || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \ ) #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ - ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ + (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ @@ -273,7 +351,7 @@ ) #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ - ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ + (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ @@ -288,7 +366,7 @@ /* ADC group injected */ #if defined(STM32G474xx) || defined(STM32G484xx) #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ - ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ + (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ @@ -336,9 +414,9 @@ ) \ ) \ ) -#elif defined(STM32G473xx) +#elif defined(STM32G473xx) || defined(STM32G483xx) #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ - ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ + (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ @@ -376,9 +454,45 @@ ) \ ) \ ) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) +#elif defined(STM32G471xx) #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ - ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ + (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \ + || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ + && ( \ + ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ + ) \ + ) \ + || ((((__ADC_INSTANCE__) == ADC3)) \ + && ( \ + ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) \ + ) \ + ) \ + ) +#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) +#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ + (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ @@ -399,28 +513,68 @@ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ ) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) +#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ + (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \ + || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ + && ( \ + ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ + ) \ + ) \ + || ((((__ADC_INSTANCE__) == ADC3)) \ + && ( \ + ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) \ + ) \ + ) \ + ) #endif #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ - ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ + (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ ) #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ - ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ + (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ ) #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ - ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ + (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ ) #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ - ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ + (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ ) @@ -428,7 +582,7 @@ /* Check of parameters for configuration of ADC hierarchical scope: */ /* multimode. */ #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ - ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ + (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ @@ -439,7 +593,7 @@ ) #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \ - ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \ + (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \ @@ -447,7 +601,7 @@ ) #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \ - ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \ + (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \ @@ -462,7 +616,7 @@ ) #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \ - ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ + (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ ) @@ -489,7 +643,7 @@ * the same ADC common instance to their default reset values. * @note This function is performing a hard reset, using high level * clock source RCC ADC reset. - * Caution: On this STM32 serie, if several ADC instances are available + * Caution: On this STM32 series, if several ADC instances are available * on the selected device, RCC ADC reset will reset * all ADC instances belonging to the common ADC instance. * To de-initialize only 1 ADC instance, use @@ -561,7 +715,7 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /* Note: Hardware constraint (refer to description of functions */ /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ - /* On this STM32 serie, setting of these features is conditioned to */ + /* On this STM32 series, setting of these features is conditioned to */ /* ADC state: */ /* All ADC instances of the ADC common group must be disabled. */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) @@ -648,7 +802,7 @@ void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) * is in an unknown state. * In this case, perform a hard reset using high level * clock source RCC ADC reset. - * Caution: On this STM32 serie, if several ADC instances are available + * Caution: On this STM32 series, if several ADC instances are available * on the selected device, RCC ADC reset will reset * all ADC instances belonging to the common ADC instance. * Refer to function @ref LL_ADC_CommonDeInit(). @@ -868,7 +1022,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 | ADC_OFR3_SATEN | ADC_OFR3_OFFSETPOS); /* Reset register OFR4 */ CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 | ADC_OFR4_SATEN | ADC_OFR4_OFFSETPOS); - + /* Reset registers JDR1, JDR2, JDR3, JDR4 */ /* Note: bits in access mode read only, no direct reset applicable */ @@ -892,10 +1046,10 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* ADC instance is in an unknown state */ /* Need to performing a hard reset of ADC instance, using high level */ /* clock source RCC ADC reset. */ - /* Caution: On this STM32 serie, if several ADC instances are available */ + /* Caution: On this STM32 series, if several ADC instances are available */ /* on the selected device, RCC ADC reset will reset */ /* all ADC instances belonging to the common ADC instance. */ - /* Caution: On this STM32 serie, if several ADC instances are available */ + /* Caution: On this STM32 series, if several ADC instances are available */ /* on the selected device, RCC ADC reset will reset */ /* all ADC instances belonging to the common ADC instance. */ status = ERROR; @@ -973,6 +1127,7 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) /* Initialization error: ADC instance is not disabled. */ status = ERROR; } + return status; } @@ -1035,6 +1190,11 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); + + /* ADC group regular continuous mode and discontinuous mode */ + /* can not be enabled simultenaeously */ + assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) + || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); } assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); @@ -1053,7 +1213,7 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I /* - Set ADC group regular conversion data transfer: no transfer or */ /* transfer by DMA, and DMA requests mode */ /* - Set ADC group regular overrun behavior */ - /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ + /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { @@ -1115,7 +1275,7 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) { /* Set ADC_REG_InitStruct fields to default values */ /* Set fields of ADC group regular */ - /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ + /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; @@ -1151,6 +1311,12 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). * - Set ADC channel sampling time * Refer to function LL_ADC_SetChannelSamplingTime(); + * @note Caution if feature ADC group injected contexts queue is enabled + * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ): + * using successively several times this function will appear as + * having no effect. + * To set several features of ADC group injected, use + * function @ref LL_ADC_INJ_ConfigQueueContext(). * @param ADCx ADC instance * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure * @retval An ErrorStatus enumeration value: @@ -1182,7 +1348,7 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I /* - Set ADC group injected sequencer discontinuous mode */ /* - Set ADC group injected conversion trigger: independent or */ /* from ADC group regular */ - /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ + /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { @@ -1257,5 +1423,3 @@ void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_dma.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_dma.c index cd77a89..778b628 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_dma.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_dma.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -375,4 +374,3 @@ void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_exti.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_exti.c index fd35de3..e6e1ebe 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_exti.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_exti.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -117,7 +116,7 @@ uint32_t LL_EXTI_DeInit(void) * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. * @retval An ErrorStatus enumeration value: * - 0x00: EXTI registers are initialized - * - any other calue : wrong configuration + * - any other value : wrong configuration */ uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) { @@ -295,4 +294,3 @@ void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_gpio.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_gpio.c index bbbf0f1..86ea40b 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_gpio.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_gpio.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -189,9 +188,6 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru if (currentpin != 0x00u) { - /* Pin Mode configuration */ - LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) { /* Check Speed mode parameters */ @@ -199,6 +195,12 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru /* Speed mode configuration */ LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); + + /* Check Output mode parameters */ + assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + + /* Output mode configuration*/ + LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); } /* Pull-up Pull down resistor configuration*/ @@ -219,19 +221,12 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); } } + + /* Pin Mode configuration */ + LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); } pinpos++; } - - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) - { - /* Check Output mode parameters */ - assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); - - /* Output mode configuration*/ - LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); - - } return (SUCCESS); } @@ -273,4 +268,3 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_tim.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_tim.c deleted file mode 100644 index 59ebcfa..0000000 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_tim.c +++ /dev/null @@ -1,1377 +0,0 @@ -/** - ****************************************************************************** - * @file stm32g4xx_ll_tim.c - * @author MCD Application Team - * @brief TIM LL module driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32g4xx_ll_tim.h" -#include "stm32g4xx_ll_bus.h" - -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -/** @addtogroup STM32G4xx_LL_Driver - * @{ - */ - -#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM20) - -/** @addtogroup TIM_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup TIM_LL_Private_Macros - * @{ - */ -#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) - -#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \ - || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ - || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) - -#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \ - || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ - || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \ - || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ - || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2) \ - || ((__VALUE__) == LL_TIM_OCMODE_PULSE_ON_COMPARE) \ - || ((__VALUE__) == LL_TIM_OCMODE_DIRECTION_OUTPUT)) - -#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ - || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) - -#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \ - || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) - -#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \ - || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH)) - -#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \ - || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ - || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) - -#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \ - || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ - || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ - || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) - -#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) - -#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ - || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \ - || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE)) - -#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \ - || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ - || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12) \ - || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) \ - || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) \ - || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) \ - || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) \ - || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI1) \ - || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI2)) - -#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ - || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) - -#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \ - || ((__VALUE__) == LL_TIM_OSSR_ENABLE)) - -#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \ - || ((__VALUE__) == LL_TIM_OSSI_ENABLE)) - -#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \ - || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \ - || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \ - || ((__VALUE__) == LL_TIM_LOCKLEVEL_3)) - -#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \ - || ((__VALUE__) == LL_TIM_BREAK_ENABLE)) - -#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \ - || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH)) - -#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8)) - -#define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \ - || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL)) - -#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \ - || ((__VALUE__) == LL_TIM_BREAK2_ENABLE)) - -#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \ - || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH)) - -#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) - -#define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \ - || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL)) - -#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ - || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) -/** - * @} - */ - - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup TIM_LL_Private_Functions TIM Private Functions - * @{ - */ -static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIM_LL_Exported_Functions - * @{ - */ - -/** @addtogroup TIM_LL_EF_Init - * @{ - */ - -/** - * @brief Set TIMx registers to their reset values. - * @param TIMx Timer instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: invalid TIMx instance - */ -ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) -{ - ErrorStatus result = SUCCESS; - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(TIMx)); - - if (TIMx == TIM1) - { - LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1); - LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1); - } - else if (TIMx == TIM2) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); - } - else if (TIMx == TIM3) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); - } - else if (TIMx == TIM4) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4); - } -#if defined(TIM5) - else if (TIMx == TIM5) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5); - } -#endif /* TIM5 */ - else if (TIMx == TIM6) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); - } - else if (TIMx == TIM7) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); - } - else if (TIMx == TIM8) - { - LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8); - LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8); - } - else if (TIMx == TIM15) - { - LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15); - LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15); - } - else if (TIMx == TIM16) - { - LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16); - LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16); - } - else if (TIMx == TIM17) - { - LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17); - LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17); - } -#if defined(TIM20) - else if (TIMx == TIM20) - { - LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM20); - LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM20); - } -#endif /* TIM20 */ - else - { - result = ERROR; - } - - return result; -} - -/** - * @brief Set the fields of the time base unit configuration data structure - * to their default values. - * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure) - * @retval None - */ -void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) -{ - /* Set the default configuration */ - TIM_InitStruct->Prescaler = (uint16_t)0x0000; - TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; - TIM_InitStruct->Autoreload = 0xFFFFFFFFU; - TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; - TIM_InitStruct->RepetitionCounter = (uint8_t)0x00; -} - -/** - * @brief Configure the TIMx time base unit. - * @param TIMx Timer Instance - * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure) - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) -{ - uint32_t tmpcr1; - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); - assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); - - tmpcr1 = LL_TIM_ReadReg(TIMx, CR1); - - if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) - { - /* Select the Counter Mode */ - MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); - } - - if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) - { - /* Set the clock division */ - MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); - } - - /* Write to TIMx CR1 */ - LL_TIM_WriteReg(TIMx, CR1, tmpcr1); - - /* Set the Autoreload value */ - LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload); - - /* Set the Prescaler value */ - LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler); - - if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) - { - /* Set the Repetition Counter value */ - LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter); - } - - /* Generate an update event to reload the Prescaler - and the repetition counter value (if applicable) immediately */ - LL_TIM_GenerateEvent_UPDATE(TIMx); - - return SUCCESS; -} - -/** - * @brief Set the fields of the TIMx output channel configuration data - * structure to their default values. - * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure) - * @retval None - */ -void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) -{ - /* Set the default configuration */ - TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN; - TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; - TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; - TIM_OC_InitStruct->CompareValue = 0x00000000U; - TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH; - TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH; - TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; - TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; -} - -/** - * @brief Configure the TIMx output channel. - * @param TIMx Timer Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure) - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx output channel is initialized - * - ERROR: TIMx output channel is not initialized - */ -ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) -{ - ErrorStatus result = ERROR; - - switch (Channel) - { - case LL_TIM_CHANNEL_CH1: - result = OC1Config(TIMx, TIM_OC_InitStruct); - break; - case LL_TIM_CHANNEL_CH2: - result = OC2Config(TIMx, TIM_OC_InitStruct); - break; - case LL_TIM_CHANNEL_CH3: - result = OC3Config(TIMx, TIM_OC_InitStruct); - break; - case LL_TIM_CHANNEL_CH4: - result = OC4Config(TIMx, TIM_OC_InitStruct); - break; - case LL_TIM_CHANNEL_CH5: - result = OC5Config(TIMx, TIM_OC_InitStruct); - break; - case LL_TIM_CHANNEL_CH6: - result = OC6Config(TIMx, TIM_OC_InitStruct); - break; - default: - break; - } - - return result; -} - -/** - * @brief Set the fields of the TIMx input channel configuration data - * structure to their default values. - * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure) - * @retval None - */ -void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) -{ - /* Set the default configuration */ - TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING; - TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; - TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1; - TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1; -} - -/** - * @brief Configure the TIMx input channel. - * @param TIMx Timer Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure) - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx output channel is initialized - * - ERROR: TIMx output channel is not initialized - */ -ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) -{ - ErrorStatus result = ERROR; - - switch (Channel) - { - case LL_TIM_CHANNEL_CH1: - result = IC1Config(TIMx, TIM_IC_InitStruct); - break; - case LL_TIM_CHANNEL_CH2: - result = IC2Config(TIMx, TIM_IC_InitStruct); - break; - case LL_TIM_CHANNEL_CH3: - result = IC3Config(TIMx, TIM_IC_InitStruct); - break; - case LL_TIM_CHANNEL_CH4: - result = IC4Config(TIMx, TIM_IC_InitStruct); - break; - default: - break; - } - - return result; -} - -/** - * @brief Fills each TIM_EncoderInitStruct field with its default value - * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure) - * @retval None - */ -void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) -{ - /* Set the default configuration */ - TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1; - TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; - TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; - TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; - TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; - TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING; - TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; - TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1; - TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1; -} - -/** - * @brief Configure the encoder interface of the timer instance. - * @param TIMx Timer Instance - * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure) - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); - assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); - assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); - assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); - assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter)); - assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity)); - assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput)); - assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler)); - assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter)); - - /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ - TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); - - /* Get the TIMx CCER register value */ - tmpccer = LL_TIM_ReadReg(TIMx, CCER); - - /* Configure TI1 */ - tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); - tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); - tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); - tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); - - /* Configure TI2 */ - tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC); - tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); - tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); - tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); - - /* Set TI1 and TI2 polarity and enable TI1 and TI2 */ - tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); - tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); - tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); - - /* Set encoder mode */ - LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode); - - /* Write to TIMx CCMR1 */ - LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); - - /* Write to TIMx CCER */ - LL_TIM_WriteReg(TIMx, CCER, tmpccer); - - return SUCCESS; -} - -/** - * @brief Set the fields of the TIMx Hall sensor interface configuration data - * structure to their default values. - * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure) - * @retval None - */ -void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) -{ - /* Set the default configuration */ - TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; - TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; - TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; - TIM_HallSensorInitStruct->CommutationDelay = 0U; -} - -/** - * @brief Configure the Hall sensor interface of the timer instance. - * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR - * to the TI1 input channel - * @note TIMx slave mode controller is configured in reset mode. - Selected internal trigger is TI1F_ED. - * @note Channel 1 is configured as input, IC1 is mapped on TRC. - * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed - * between 2 changes on the inputs. It gives information about motor speed. - * @note Channel 2 is configured in output PWM 2 mode. - * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay. - * @note OC2REF is selected as trigger output on TRGO. - * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used - * when TIMx operates in Hall sensor interface mode. - * @param TIMx Timer Instance - * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure) - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) -{ - uint32_t tmpcr2; - uint32_t tmpccmr1; - uint32_t tmpccer; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity)); - assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler)); - assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter)); - - /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ - TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); - - /* Get the TIMx CR2 register value */ - tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); - - /* Get the TIMx CCER register value */ - tmpccer = LL_TIM_ReadReg(TIMx, CCER); - - /* Get the TIMx SMCR register value */ - tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR); - - /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */ - tmpcr2 |= TIM_CR2_TI1S; - - /* OC2REF signal is used as trigger output (TRGO) */ - tmpcr2 |= LL_TIM_TRGO_OC2REF; - - /* Configure the slave mode controller */ - tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS); - tmpsmcr |= LL_TIM_TS_TI1F_ED; - tmpsmcr |= LL_TIM_SLAVEMODE_RESET; - - /* Configure input channel 1 */ - tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); - tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U); - tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U); - tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U); - - /* Configure input channel 2 */ - tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE); - tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U); - - /* Set Channel 1 polarity and enable Channel 1 and Channel2 */ - tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity); - tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); - - /* Write to TIMx CR2 */ - LL_TIM_WriteReg(TIMx, CR2, tmpcr2); - - /* Write to TIMx SMCR */ - LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr); - - /* Write to TIMx CCMR1 */ - LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); - - /* Write to TIMx CCER */ - LL_TIM_WriteReg(TIMx, CCER, tmpccer); - - /* Write to TIMx CCR2 */ - LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay); - - return SUCCESS; -} - -/** - * @brief Set the fields of the Break and Dead Time configuration data structure - * to their default values. - * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) - * @retval None - */ -void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) -{ - /* Set the default configuration */ - TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE; - TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE; - TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF; - TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00; - TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; - TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; - TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1; - TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT; - TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE; - TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW; - TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1; - TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT; - TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE; -} - -/** - * @brief Configure the Break and Dead Time feature of the timer instance. - * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR - * and DTG[7:0] can be write-locked depending on the LOCK configuration, it - * can be necessary to configure all of them during the first write access to - * the TIMx_BDTR register. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a second break input. - * @param TIMx Timer Instance - * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Break and Dead Time is initialized - * - ERROR: not applicable - */ -ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) -{ - uint32_t tmpbdtr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState)); - assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState)); - assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel)); - assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); - assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); - assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); - - /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - - /* Set the BDTR bits */ - MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); - MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); - MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); - MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); - MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); - MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); - if (IS_TIM_ADVANCED_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); - assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); - } - - if (IS_TIM_BKIN2_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State)); - assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity)); - assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter)); - assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode)); - - /* Set the BREAK2 input related BDTR bit-fields */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter)); - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State); - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity); - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode); - } - - /* Set TIMx_BDTR */ - LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr); - - return SUCCESS; -} -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup TIM_LL_Private_Functions TIM Private Functions - * @brief Private functions - * @{ - */ -/** - * @brief Configure the TIMx output channel 1. - * @param TIMx Timer Instance - * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - - /* Disable the Channel 1: Reset the CC1E Bit */ - CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); - - /* Get the TIMx CCER register value */ - tmpccer = LL_TIM_ReadReg(TIMx, CCER); - - /* Get the TIMx CR2 register value */ - tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); - - /* Reset Capture/Compare selection Bits */ - CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S); - - /* Set the Output Compare Mode */ - MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); - - /* Set the Output Compare Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity); - - /* Set the Output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); - - /* Set the complementary output Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); - - /* Set the complementary output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); - - /* Set the Output Idle state */ - MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); - - /* Set the complementary output Idle state */ - MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); - } - - /* Write to TIMx CR2 */ - LL_TIM_WriteReg(TIMx, CR2, tmpcr2); - - /* Write to TIMx CCMR1 */ - LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); - - /* Set the Capture Compare Register value */ - LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue); - - /* Write to TIMx CCER */ - LL_TIM_WriteReg(TIMx, CCER, tmpccer); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx output channel 2. - * @param TIMx Timer Instance - * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - - /* Disable the Channel 2: Reset the CC2E Bit */ - CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); - - /* Get the TIMx CCER register value */ - tmpccer = LL_TIM_ReadReg(TIMx, CCER); - - /* Get the TIMx CR2 register value */ - tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); - - /* Reset Capture/Compare selection Bits */ - CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S); - - /* Select the Output Compare Mode */ - MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U); - - /* Set the Output Compare Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U); - - /* Set the Output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); - - /* Set the complementary output Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); - - /* Set the complementary output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); - - /* Set the Output Idle state */ - MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); - - /* Set the complementary output Idle state */ - MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); - } - - /* Write to TIMx CR2 */ - LL_TIM_WriteReg(TIMx, CR2, tmpcr2); - - /* Write to TIMx CCMR1 */ - LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); - - /* Set the Capture Compare Register value */ - LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue); - - /* Write to TIMx CCER */ - LL_TIM_WriteReg(TIMx, CCER, tmpccer); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx output channel 3. - * @param TIMx Timer Instance - * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) -{ - uint32_t tmpccmr2; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - - /* Disable the Channel 3: Reset the CC3E Bit */ - CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); - - /* Get the TIMx CCER register value */ - tmpccer = LL_TIM_ReadReg(TIMx, CCER); - - /* Get the TIMx CR2 register value */ - tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); - - /* Reset Capture/Compare selection Bits */ - CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); - - /* Select the Output Compare Mode */ - MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); - - /* Set the Output Compare Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); - - /* Set the Output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); - - /* Set the complementary output Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); - - /* Set the complementary output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); - - /* Set the Output Idle state */ - MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); - - /* Set the complementary output Idle state */ - MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); - } - - /* Write to TIMx CR2 */ - LL_TIM_WriteReg(TIMx, CR2, tmpcr2); - - /* Write to TIMx CCMR2 */ - LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); - - /* Set the Capture Compare Register value */ - LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue); - - /* Write to TIMx CCER */ - LL_TIM_WriteReg(TIMx, CCER, tmpccer); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx output channel 4. - * @param TIMx Timer Instance - * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) -{ - uint32_t tmpccmr2; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - - /* Disable the Channel 4: Reset the CC4E Bit */ - CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); - - /* Get the TIMx CCER register value */ - tmpccer = LL_TIM_ReadReg(TIMx, CCER); - - /* Get the TIMx CR2 register value */ - tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); - - /* Reset Capture/Compare selection Bits */ - CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); - - /* Select the Output Compare Mode */ - MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); - - /* Set the Output Compare Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U); - - /* Set the Output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); - - /* Set the complementary output Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U); - - /* Set the complementary output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U); - - /* Set the Output Idle state */ - MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); - - /* Set the complementary output Idle state */ - MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U); - } - - /* Write to TIMx CR2 */ - LL_TIM_WriteReg(TIMx, CR2, tmpcr2); - - /* Write to TIMx CCMR2 */ - LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); - - /* Set the Capture Compare Register value */ - LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue); - - /* Write to TIMx CCER */ - LL_TIM_WriteReg(TIMx, CCER, tmpccer); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx output channel 5. - * @param TIMx Timer Instance - * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) -{ - uint32_t tmpccmr3; - uint32_t tmpccer; - - /* Check the parameters */ - assert_param(IS_TIM_CC5_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - - /* Disable the Channel 5: Reset the CC5E Bit */ - CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E); - - /* Get the TIMx CCER register value */ - tmpccer = LL_TIM_ReadReg(TIMx, CCER); - - /* Get the TIMx CCMR3 register value */ - tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); - - /* Select the Output Compare Mode */ - MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode); - - /* Set the Output Compare Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U); - - /* Set the Output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U); - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); - - /* Set the Output Idle state */ - MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U); - - } - - /* Write to TIMx CCMR3 */ - LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); - - /* Set the Capture Compare Register value */ - LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue); - - /* Write to TIMx CCER */ - LL_TIM_WriteReg(TIMx, CCER, tmpccer); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx output channel 6. - * @param TIMx Timer Instance - * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) -{ - uint32_t tmpccmr3; - uint32_t tmpccer; - - /* Check the parameters */ - assert_param(IS_TIM_CC6_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - - /* Disable the Channel 5: Reset the CC6E Bit */ - CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E); - - /* Get the TIMx CCER register value */ - tmpccer = LL_TIM_ReadReg(TIMx, CCER); - - /* Get the TIMx CCMR3 register value */ - tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); - - /* Select the Output Compare Mode */ - MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U); - - /* Set the Output Compare Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U); - - /* Set the Output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U); - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); - - /* Set the Output Idle state */ - MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U); - } - - /* Write to TIMx CCMR3 */ - LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); - - /* Set the Capture Compare Register value */ - LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue); - - /* Write to TIMx CCER */ - LL_TIM_WriteReg(TIMx, CCER, tmpccer); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx input channel 1. - * @param TIMx Timer Instance - * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); - assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); - assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); - assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; - - /* Select the Input and set the filter and the prescaler value */ - MODIFY_REG(TIMx->CCMR1, - (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC), - (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); - - /* Select the Polarity and set the CC1E Bit */ - MODIFY_REG(TIMx->CCER, - (TIM_CCER_CC1P | TIM_CCER_CC1NP), - (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E)); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx input channel 2. - * @param TIMx Timer Instance - * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); - assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); - assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); - assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; - - /* Select the Input and set the filter and the prescaler value */ - MODIFY_REG(TIMx->CCMR1, - (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC), - (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); - - /* Select the Polarity and set the CC2E Bit */ - MODIFY_REG(TIMx->CCER, - (TIM_CCER_CC2P | TIM_CCER_CC2NP), - ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E)); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx input channel 3. - * @param TIMx Timer Instance - * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); - assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); - assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); - assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); - - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; - - /* Select the Input and set the filter and the prescaler value */ - MODIFY_REG(TIMx->CCMR2, - (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC), - (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); - - /* Select the Polarity and set the CC3E Bit */ - MODIFY_REG(TIMx->CCER, - (TIM_CCER_CC3P | TIM_CCER_CC3NP), - ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E)); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx input channel 4. - * @param TIMx Timer Instance - * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); - assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); - assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); - assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; - - /* Select the Input and set the filter and the prescaler value */ - MODIFY_REG(TIMx->CCMR2, - (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), - (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); - - /* Select the Polarity and set the CC2E Bit */ - MODIFY_REG(TIMx->CCER, - (TIM_CCER_CC4P | TIM_CCER_CC4NP), - ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); - - return SUCCESS; -} - - -/** - * @} - */ - -/** - * @} - */ - -#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM15 || TIM16 || TIM17 || TIM20 */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_ucpd.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_ucpd.c index 127a36e..15f66a3 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_ucpd.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_ucpd.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -27,7 +26,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32G4xx_LL_Driver * @{ @@ -83,7 +82,7 @@ ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx) /* Check the parameters */ assert_param(IS_UCPD_ALL_INSTANCE(UCPDx)); - + LL_UCPD_Disable(UCPDx); if (UCPD1 == UCPDx) @@ -94,7 +93,7 @@ ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx) /* Release reset of ucpd clock */ LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_UCPD1); - /* Disbale ucpd clock */ + /* Disable ucpd clock */ LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_UCPD1); status = SUCCESS; @@ -105,8 +104,9 @@ ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx) /** * @brief Initialize the ucpd registers according to the specified parameters in UCPD_InitStruct. - * @note As some bits in ucpd configuration registers can only be written when the ucpd is disabled (ucpd_CR1_SPE bit =0), - * UCPD peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in ucpd configuration registers can only be written when the ucpd is disabled + * (ucpd_CR1_SPE bit =0), UCPD peripheral should be in disabled state prior calling this function. + * Otherwise, ERROR result will be returned. * @param UCPDx UCPD Instance * @param UCPD_InitStruct pointer to a @ref LL_UCPD_InitTypeDef structure that contains * the configuration information for the UCPD peripheral. @@ -117,7 +117,7 @@ ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStru /* Check the ucpd Instance UCPDx*/ assert_param(IS_UCPD_ALL_INSTANCE(UCPDx)); - if(UCPD1 == UCPDx) + if (UCPD1 == UCPDx) { LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_UCPD1); } @@ -143,10 +143,10 @@ ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStru void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct) { /* Set UCPD_InitStruct fields to default values */ - UCPD_InitStruct->psc_ucpdclk = LL_UCPD_PSC_DIV1; + UCPD_InitStruct->psc_ucpdclk = LL_UCPD_PSC_DIV2; UCPD_InitStruct->transwin = 0x7; /* Divide by 8 */ UCPD_InitStruct->IfrGap = 0x10; /* Divide by 17 */ - UCPD_InitStruct->HbitClockDiv = 0x1A; /* Divide by 27 to produce HBITCLK */ + UCPD_InitStruct->HbitClockDiv = 0x0D; /* Divide by 14 to produce HBITCLK */ } /** @@ -167,4 +167,3 @@ void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c index 7d5cb3d..c8f9fda 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c @@ -11,6 +11,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -23,17 +34,7 @@ (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * + ****************************************************************************** */ @@ -53,11 +54,10 @@ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ - /** * @brief Initializes the USB Core - * @param USBx: USB Instance - * @param cfg : pointer to a USB_CfgTypeDef structure that contains + * @param USBx USB Instance + * @param cfg pointer to a USB_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ @@ -78,12 +78,15 @@ HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) /** * @brief USB_EnableGlobalInt * Enables the controller's Global Int in the AHB Config reg - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) { - uint16_t winterruptmask; + uint32_t winterruptmask; + + /* Clear pending interrupts */ + USBx->ISTR = 0U; /* Set winterruptmask variable */ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | @@ -92,7 +95,7 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) USB_CNTR_RESETM | USB_CNTR_L1REQM; /* Set interrupt mask */ - USBx->CNTR |= winterruptmask; + USBx->CNTR = (uint16_t)winterruptmask; return HAL_OK; } @@ -100,12 +103,12 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) /** * @brief USB_DisableGlobalInt * Disable the controller's Global Int in the AHB Config reg - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status -*/ + */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) { - uint16_t winterruptmask; + uint32_t winterruptmask; /* Set winterruptmask variable */ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | @@ -114,17 +117,17 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) USB_CNTR_RESETM | USB_CNTR_L1REQM; /* Clear interrupt mask */ - USBx->CNTR &= ~winterruptmask; + USBx->CNTR &= (uint16_t)(~winterruptmask); return HAL_OK; } /** - * @brief USB_SetCurrentMode : Set functional mode - * @param USBx : Selected device - * @param mode : current core mode + * @brief USB_SetCurrentMode Set functional mode + * @param USBx Selected device + * @param mode current core mode * This parameter can be one of the these values: - * @arg USB_DEVICE_MODE: Peripheral mode mode + * @arg USB_DEVICE_MODE Peripheral mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode) @@ -141,10 +144,10 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode) } /** - * @brief USB_DevInit : Initializes the USB controller registers + * @brief USB_DevInit Initializes the USB controller registers * for device mode - * @param USBx : Selected device - * @param cfg : pointer to a USB_CfgTypeDef structure that contains + * @param USBx Selected device + * @param cfg pointer to a USB_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ @@ -154,89 +157,26 @@ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) UNUSED(cfg); /* Init Device */ - /*CNTR_FRES = 1*/ - USBx->CNTR = USB_CNTR_FRES; + /* CNTR_FRES = 1 */ + USBx->CNTR = (uint16_t)USB_CNTR_FRES; - /*CNTR_FRES = 0*/ - USBx->CNTR = 0; + /* CNTR_FRES = 0 */ + USBx->CNTR = 0U; - /*Clear pending interrupts*/ - USBx->ISTR = 0; + /* Clear pending interrupts */ + USBx->ISTR = 0U; /*Set Btable Address*/ USBx->BTABLE = BTABLE_ADDRESS; - /* Enable USB Device Interrupt mask */ - (void)USB_EnableGlobalInt(USBx); - - return HAL_OK; -} - -/** - * @brief USB_SetDevSpeed :Initializes the device speed - * depending on the PHY type and the enumeration speed of the device. - * @param USBx Selected device - * @param speed device speed - * @retval Hal status - */ -HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(speed); - - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - return HAL_OK; -} - -/** - * @brief USB_FlushTxFifo : Flush a Tx FIFO - * @param USBx : Selected device - * @param num : FIFO number - * This parameter can be a value from 1 to 15 - 15 means Flush all Tx FIFOs - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(num); - - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - return HAL_OK; -} - -/** - * @brief USB_FlushRxFifo : Flush Rx FIFO - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - return HAL_OK; } +#if defined (HAL_PCD_MODULE_ENABLED) /** * @brief Activate and configure an endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) @@ -270,7 +210,7 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) break; } - PCD_SET_ENDPOINT(USBx, ep->num, wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX); + PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num); @@ -295,20 +235,32 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) } else { - /*Set the endpoint Receive buffer address */ + /* Set the endpoint Receive buffer address */ PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress); - /*Set the endpoint Receive buffer counter*/ + + /* Set the endpoint Receive buffer counter */ PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket); PCD_CLEAR_RX_DTOG(USBx, ep->num); - /* Configure VALID status for the Endpoint*/ + + /* Configure VALID status for the Endpoint */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); } } - /*Double Buffer*/ +#if (USE_USB_DOUBLE_BUFFER == 1U) + /* Double Buffer */ else { - /* Set the endpoint as double buffered */ - PCD_SET_EP_DBUF(USBx, ep->num); + if (ep->type == EP_TYPE_BULK) + { + /* Set bulk endpoint as double buffered */ + PCD_SET_BULK_EP_DBUF(USBx, ep->num); + } + else + { + /* Set the ISOC endpoint in double buffer mode */ + PCD_CLEAR_EP_KIND(USBx, ep->num); + } + /* Set buffer address for double buffered mode */ PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1); @@ -318,9 +270,6 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); - /* Reset value of the data toggle bits for the endpoint out */ - PCD_TX_DTOG(USBx, ep->num); - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } @@ -329,7 +278,6 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) /* Clear the data toggle bits for the endpoint IN/OUT */ PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); - PCD_RX_DTOG(USBx, ep->num); if (ep->type != EP_TYPE_ISOC) { @@ -345,14 +293,15 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); } } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ return ret; } /** * @brief De-activate and de-initialize an endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) @@ -362,17 +311,21 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) if (ep->is_in != 0U) { PCD_CLEAR_TX_DTOG(USBx, ep->num); - /* Configure DISABLE status for the Endpoint*/ + + /* Configure DISABLE status for the Endpoint */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } + else { PCD_CLEAR_RX_DTOG(USBx, ep->num); - /* Configure DISABLE status for the Endpoint*/ + + /* Configure DISABLE status for the Endpoint */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); } } - /*Double Buffer*/ +#if (USE_USB_DOUBLE_BUFFER == 1U) + /* Double Buffer */ else { if (ep->is_in == 0U) @@ -393,25 +346,30 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); PCD_RX_DTOG(USBx, ep->num); + /* Configure DISABLE status for the Endpoint*/ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); } } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ return HAL_OK; } /** - * @brief USB_EPStartXfer : setup and starts a transfer over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @brief USB_EPStartXfer setup and starts a transfer over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - uint16_t pmabuffer; uint32_t len; +#if (USE_USB_DOUBLE_BUFFER == 1U) + uint16_t pmabuffer; + uint16_t wEPVal; +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ /* IN endpoint */ if (ep->is_in == 1U) @@ -420,12 +378,10 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) if (ep->xfer_len > ep->maxpacket) { len = ep->maxpacket; - ep->xfer_len -= len; } else { len = ep->xfer_len; - ep->xfer_len = 0U; } /* configure and validate Tx endpoint */ @@ -434,52 +390,185 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len); PCD_SET_EP_TX_CNT(USBx, ep->num, len); } +#if (USE_USB_DOUBLE_BUFFER == 1U) else { - /* Write the data to the USB endpoint */ - if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) + /* double buffer bulk management */ + if (ep->type == EP_TYPE_BULK) { - /* Set the Double buffer counter for pmabuffer1 */ - PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); - pmabuffer = ep->pmaaddr1; + if (ep->xfer_len_db > ep->maxpacket) + { + /* enable double buffer */ + PCD_SET_BULK_EP_DBUF(USBx, ep->num); + + /* each Time to write in PMA xfer_len_db will */ + ep->xfer_len_db -= len; + + /* Fill the two first buffer in the Buffer0 & Buffer1 */ + if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) + { + /* Set the Double buffer counter for pmabuffer1 */ + PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr1; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + ep->xfer_buff += len; + + if (ep->xfer_len_db > ep->maxpacket) + { + ep->xfer_len_db -= len; + } + else + { + len = ep->xfer_len_db; + ep->xfer_len_db = 0U; + } + + /* Set the Double buffer counter for pmabuffer0 */ + PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr0; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } + else + { + /* Set the Double buffer counter for pmabuffer0 */ + PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr0; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + ep->xfer_buff += len; + + if (ep->xfer_len_db > ep->maxpacket) + { + ep->xfer_len_db -= len; + } + else + { + len = ep->xfer_len_db; + ep->xfer_len_db = 0U; + } + + /* Set the Double buffer counter for pmabuffer1 */ + PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr1; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } + } + /* auto Switch to single buffer mode when transfer xfer_len_db; + + /* disable double buffer mode for Bulk endpoint */ + PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num); + + /* Set Tx count with nbre of byte to be transmitted */ + PCD_SET_EP_TX_CNT(USBx, ep->num, len); + pmabuffer = ep->pmaaddr0; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } } - else + else /* manage isochronous double buffer IN mode */ { - /* Set the Double buffer counter for pmabuffer0 */ - PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); - pmabuffer = ep->pmaaddr0; + /* each Time to write in PMA xfer_len_db will */ + ep->xfer_len_db -= len; + + /* Fill the data buffer */ + if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) + { + /* Set the Double buffer counter for pmabuffer1 */ + PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr1; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } + else + { + /* Set the Double buffer counter for pmabuffer0 */ + PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr0; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } } - USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - PCD_FreeUserBuffer(USBx, ep->num, ep->is_in); } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); } else /* OUT endpoint */ { - /* Multi packet transfer*/ - if (ep->xfer_len > ep->maxpacket) - { - len = ep->maxpacket; - ep->xfer_len -= len; - } - else - { - len = ep->xfer_len; - ep->xfer_len = 0U; - } - - /* configure and validate Rx endpoint */ if (ep->doublebuffer == 0U) { - /*Set RX buffer count*/ + /* Multi packet transfer */ + if (ep->xfer_len > ep->maxpacket) + { + len = ep->maxpacket; + ep->xfer_len -= len; + } + else + { + len = ep->xfer_len; + ep->xfer_len = 0U; + } + /* configure and validate Rx endpoint */ PCD_SET_EP_RX_CNT(USBx, ep->num, len); } +#if (USE_USB_DOUBLE_BUFFER == 1U) else { - /*Set the Double buffer counter*/ - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); + /* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */ + /* Set the Double buffer counter */ + if (ep->type == EP_TYPE_BULK) + { + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); + + /* Coming from ISR */ + if (ep->xfer_count != 0U) + { + /* update last value to check if there is blocking state */ + wEPVal = PCD_GET_ENDPOINT(USBx, ep->num); + + /*Blocking State */ + if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || + (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) + { + PCD_FREE_USER_BUFFER(USBx, ep->num, 0U); + } + } + } + /* iso out double */ + else if (ep->type == EP_TYPE_ISOC) + { + /* Multi packet transfer */ + if (ep->xfer_len > ep->maxpacket) + { + len = ep->maxpacket; + ep->xfer_len -= len; + } + else + { + len = ep->xfer_len; + ep->xfer_len = 0U; + } + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); + } + else + { + return HAL_ERROR; + } } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); } @@ -487,54 +576,11 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) return HAL_OK; } -/** - * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated - * with the EP/channel - * @param USBx : Selected device - * @param src : pointer to source buffer - * @param ch_ep_num : endpoint or host channel number - * @param len : Number of bytes to write - * @retval HAL status - */ -HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(src); - UNUSED(ch_ep_num); - UNUSED(len); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - return HAL_OK; -} /** - * @brief USB_ReadPacket : read a packet from the Tx FIFO associated - * with the EP/channel - * @param USBx : Selected device - * @param dest : destination pointer - * @param len : Number of bytes to read - * @retval pointer to destination buffer - */ -void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(dest); - UNUSED(len); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - return ((void *)NULL); -} - -/** - * @brief USB_EPSetStall : set a stall condition over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @brief USB_EPSetStall set a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) @@ -552,9 +598,9 @@ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) } /** - * @brief USB_EPClearStall : Clear a stall condition over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @brief USB_EPClearStall Clear a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) @@ -575,37 +621,38 @@ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) { PCD_CLEAR_RX_DTOG(USBx, ep->num); - /* Configure VALID status for the Endpoint*/ + /* Configure VALID status for the Endpoint */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); } } return HAL_OK; } +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ /** - * @brief USB_StopDevice : Stop the usb device mode - * @param USBx : Selected device + * @brief USB_StopDevice Stop the usb device mode + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) { /* disable all interrupts and force USB reset */ - USBx->CNTR = USB_CNTR_FRES; + USBx->CNTR = (uint16_t)USB_CNTR_FRES; /* clear interrupt status register */ - USBx->ISTR = 0; + USBx->ISTR = 0U; /* switch-off device */ - USBx->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN); + USBx->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN); return HAL_OK; } /** - * @brief USB_SetDevAddress : Stop the usb device mode - * @param USBx : Selected device - * @param address : new device address to be assigned + * @brief USB_SetDevAddress Stop the usb device mode + * @param USBx Selected device + * @param address new device address to be assigned * This parameter can be a value from 0 to 255 * @retval HAL status */ @@ -614,28 +661,28 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address) if (address == 0U) { /* set device address and enable function */ - USBx->DADDR = USB_DADDR_EF; + USBx->DADDR = (uint16_t)USB_DADDR_EF; } return HAL_OK; } /** - * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down - * @param USBx : Selected device + * @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx) { /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */ - USBx->BCDR |= USB_BCDR_DPPU; + USBx->BCDR |= (uint16_t)USB_BCDR_DPPU; return HAL_OK; } /** - * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down - * @param USBx : Selected device + * @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx) @@ -647,8 +694,8 @@ HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx) } /** - * @brief USB_ReadInterrupts: return the global USB interrupt status - * @param USBx : Selected device + * @brief USB_ReadInterrupts return the global USB interrupt status + * @param USBx Selected device * @retval HAL status */ uint32_t USB_ReadInterrupts(USB_TypeDef *USBx) @@ -659,131 +706,27 @@ uint32_t USB_ReadInterrupts(USB_TypeDef *USBx) return tmpreg; } -/** - * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status - * @param USBx : Selected device - * @retval HAL status - */ -uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - return (0); -} - -/** - * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status - * @param USBx : Selected device - * @retval HAL status - */ -uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - return (0); -} - -/** - * @brief Returns Device OUT EP Interrupt register - * @param USBx : Selected device - * @param epnum : endpoint number - * This parameter can be a value from 0 to 15 - * @retval Device OUT EP Interrupt register - */ -uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(epnum); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - return (0); -} - -/** - * @brief Returns Device IN EP Interrupt register - * @param USBx : Selected device - * @param epnum : endpoint number - * This parameter can be a value from 0 to 15 - * @retval Device IN EP Interrupt register - */ -uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(epnum); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - return (0); -} - -/** - * @brief USB_ClearInterrupts: clear a USB interrupt - * @param USBx Selected device - * @param interrupt interrupt flag - * @retval None - */ -void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(interrupt); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ -} - -/** - * @brief Prepare the EP0 to start the first control setup - * @param USBx Selected device - * @param psetup pointer to setup packet - * @retval HAL status - */ -HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(psetup); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - return HAL_OK; -} - /** * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling - * @param USBx Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx) { - USBx->CNTR |= USB_CNTR_RESUME; + USBx->CNTR |= (uint16_t)USB_CNTR_RESUME; return HAL_OK; } /** - * @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling - * @param USBx Selected device + * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx) { - USBx->CNTR &= ~(USB_CNTR_RESUME); + USBx->CNTR &= (uint16_t)(~USB_CNTR_RESUME); + return HAL_OK; } @@ -792,56 +735,59 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx) * @param USBx USB peripheral instance register address. * @param pbUsrBuf pointer to user memory area. * @param wPMABufAddr address into PMA. - * @param wNBytes: no. of bytes to be copied. + * @param wNBytes no. of bytes to be copied. * @retval None */ void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { uint32_t n = ((uint32_t)wNBytes + 1U) >> 1; uint32_t BaseAddr = (uint32_t)USBx; - uint32_t i, temp1, temp2; - uint16_t *pdwVal; + uint32_t i; + uint32_t temp1; + uint32_t temp2; + __IO uint16_t *pdwVal; uint8_t *pBuf = pbUsrBuf; - pdwVal = (uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); + pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); for (i = n; i != 0U; i--) { - temp1 = (uint16_t) * pBuf; + temp1 = *pBuf; pBuf++; - temp2 = temp1 | ((uint16_t)((uint16_t) * pBuf << 8)); + temp2 = temp1 | ((uint16_t)((uint16_t) *pBuf << 8)); *pdwVal = (uint16_t)temp2; pdwVal++; #if PMA_ACCESS > 1U pdwVal++; -#endif +#endif /* PMA_ACCESS */ pBuf++; } } /** - * @brief Copy a buffer from user memory area to packet memory area (PMA) - * @param USBx: USB peripheral instance register address. + * @brief Copy data from packet memory area (PMA) to user memory buffer + * @param USBx USB peripheral instance register address. * @param pbUsrBuf pointer to user memory area. * @param wPMABufAddr address into PMA. - * @param wNBytes: no. of bytes to be copied. + * @param wNBytes no. of bytes to be copied. * @retval None */ void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { uint32_t n = (uint32_t)wNBytes >> 1; uint32_t BaseAddr = (uint32_t)USBx; - uint32_t i, temp; - uint16_t *pdwVal; + uint32_t i; + uint32_t temp; + __IO uint16_t *pdwVal; uint8_t *pBuf = pbUsrBuf; - pdwVal = (uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); + pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); for (i = n; i != 0U; i--) { - temp = *pdwVal; + temp = *(__IO uint16_t *)pdwVal; pdwVal++; *pBuf = (uint8_t)((temp >> 0) & 0xFFU); pBuf++; @@ -850,7 +796,7 @@ void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uin #if PMA_ACCESS > 1U pdwVal++; -#endif +#endif /* PMA_ACCESS */ } if ((wNBytes % 2U) != 0U) @@ -874,5 +820,3 @@ void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uin /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.c b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.c index 9e1fb7b..4e589a8 100644 --- a/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.c +++ b/Software/VNA_embedded/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -142,7 +141,6 @@ */ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); -static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency); static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); static ErrorStatus UTILS_PLL_IsBusy(void); /** @@ -268,6 +266,118 @@ void LL_SetSystemCoreClock(uint32_t HCLKFrequency) SystemCoreClock = HCLKFrequency; } +/** + * @brief Update number of Flash wait states in line with new frequency and current + voltage range. + * @param HCLKFrequency HCLK frequency + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Latency has been modified + * - ERROR: Latency cannot be modified + */ +ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency) +{ + uint32_t timeout; + uint32_t getlatency; + ErrorStatus status = SUCCESS; + + uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ + + /* Frequency cannot be equal to 0 or greater than max clock */ + if((HCLKFrequency == 0U) || (HCLKFrequency > UTILS_SCALE1_LATENCY9_FREQ)) + { + status = ERROR; + } + else + { + if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) + { + if(HCLKFrequency > UTILS_SCALE1_LATENCY8_FREQ) + { + /* 160 < HCLK <= 170 => 8WS (9 CPU cycles) */ + latency = LL_FLASH_LATENCY_8; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY7_FREQ) + { + /* 140 < HCLK <= 160 => 7WS (8 CPU cycles) */ + latency = LL_FLASH_LATENCY_7; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY6_FREQ) + { + /* 120 < HCLK <= 140 => 6WS (7 CPU cycles) */ + latency = LL_FLASH_LATENCY_6; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY5_FREQ) + { + /* 100 < HCLK <= 120 => 5WS (6 CPU cycles) */ + latency = LL_FLASH_LATENCY_5; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY4_FREQ) + { + /* 80 < HCLK <= 100 => 4WS (5 CPU cycles) */ + latency = LL_FLASH_LATENCY_4; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY3_FREQ) + { + /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ) + { + /* 40 < HCLK <= 60 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if(HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ) + { + /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLKFrequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */ + } + } + else /* SCALE2 */ + { + if(HCLKFrequency > UTILS_SCALE2_LATENCY2_FREQ) + { + /* 16 < HCLK <= 26 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if(HCLKFrequency > UTILS_SCALE2_LATENCY1_FREQ) + { + /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLKFrequency <= 8MHz default LL_FLASH_LATENCY_0 0WS */ + } + } + + if (status != ERROR) + { + LL_FLASH_SetLatency(latency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + timeout = 2U; + do + { + /* Wait for Flash latency to be updated */ + getlatency = LL_FLASH_GetLatency(); + timeout--; + } while ((getlatency != latency) && (timeout > 0U)); + + if(getlatency != latency) + { + status = ERROR; + } + } + } + + return status; +} + /** * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL * @note The application need to ensure that PLL is disabled. @@ -289,7 +399,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS { ErrorStatus status; uint32_t pllfreq; - uint32_t hpre = 0U; + uint32_t hpre = LL_RCC_SYSCLK_DIV_1; /* Check if one of the PLL is enabled */ if(UTILS_PLL_IsBusy() == SUCCESS) @@ -314,10 +424,10 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */ if(pllfreq > 80000000U) { - hpre = UTILS_ClkInitStruct->AHBCLKDivider; - if(hpre == LL_RCC_SYSCLK_DIV_1) + if (UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1) { UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2; + hpre = LL_RCC_SYSCLK_DIV_2; } } @@ -325,10 +435,16 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); /* Apply definitive AHB prescaler value if necessary */ - if((status == SUCCESS) && (hpre != 0U)) + if ((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1)) { - UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; - LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + /* Set FLASH latency to highest latency */ + status = LL_SetFlashLatency(pllfreq); + if (status == SUCCESS) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + LL_SetSystemCoreClock(pllfreq); + } } } else @@ -365,7 +481,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa { ErrorStatus status; uint32_t pllfreq; - uint32_t hpre = 0U; + uint32_t hpre = LL_RCC_SYSCLK_DIV_1; /* Check the parameters */ assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); @@ -405,10 +521,10 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */ if(pllfreq > 80000000U) { - hpre = UTILS_ClkInitStruct->AHBCLKDivider; - if(hpre == LL_RCC_SYSCLK_DIV_1) + if (UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1) { UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2; + hpre = LL_RCC_SYSCLK_DIV_2; } } @@ -416,10 +532,16 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); /* Apply definitive AHB prescaler value if necessary */ - if((status == SUCCESS) && (hpre != 0U)) + if ((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1)) { - UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; - LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + /* Set FLASH latency to highest latency */ + status = LL_SetFlashLatency(pllfreq); + if (status == SUCCESS) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + LL_SetSystemCoreClock(pllfreq); + } } } else @@ -442,103 +564,6 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa /** @addtogroup UTILS_LL_Private_Functions * @{ */ -/** - * @brief Update number of Flash wait states in line with new frequency and current - voltage range. - * @param HCLK_Frequency HCLK frequency - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Latency has been modified - * - ERROR: Latency cannot be modified - */ -static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency) -{ - ErrorStatus status = SUCCESS; - - uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ - - /* Frequency cannot be equal to 0 */ - if(HCLK_Frequency == 0U) - { - status = ERROR; - } - else - { - if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) - { - if(HCLK_Frequency > UTILS_SCALE1_LATENCY8_FREQ) - { - /* 160 < HCLK <= 170 => 8WS (9 CPU cycles) */ - latency = LL_FLASH_LATENCY_8; - } - else if(HCLK_Frequency > UTILS_SCALE1_LATENCY7_FREQ) - { - /* 140 < HCLK <= 160 => 7WS (8 CPU cycles) */ - latency = LL_FLASH_LATENCY_7; - } - else if(HCLK_Frequency > UTILS_SCALE1_LATENCY6_FREQ) - { - /* 120 < HCLK <= 140 => 6WS (7 CPU cycles) */ - latency = LL_FLASH_LATENCY_6; - } - else if(HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ) - { - /* 100 < HCLK <= 120 => 5WS (6 CPU cycles) */ - latency = LL_FLASH_LATENCY_5; - } - else if(HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) - { - /* 80 < HCLK <= 100 => 4WS (5 CPU cycles) */ - latency = LL_FLASH_LATENCY_4; - } - else if(HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) - { - /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */ - latency = LL_FLASH_LATENCY_3; - } - else if(HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) - { - /* 40 < HCLK <= 60 => 2WS (3 CPU cycles) */ - latency = LL_FLASH_LATENCY_2; - } - else - { - if(HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) - { - /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - /* else HCLK_Frequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */ - } - } - else /* SCALE2 */ - { - if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) - { - /* 16 < HCLK <= 26 => 2WS (3 CPU cycles) */ - latency = LL_FLASH_LATENCY_2; - } - else - { - if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) - { - /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - /* else HCLK_Frequency <= 8MHz default LL_FLASH_LATENCY_0 0WS */ - } - } - - LL_FLASH_SetLatency(latency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if(LL_FLASH_GetLatency() != latency) - { - status = ERROR; - } - } - return status; -} /** * @brief Function to check that PLL can be modified @@ -617,7 +642,7 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_ if(SystemCoreClock < hclk_frequency) { /* Set FLASH latency to highest latency */ - status = UTILS_SetFlashLatency(hclk_frequency); + status = LL_SetFlashLatency(hclk_frequency); } /* Update system clock configuration */ @@ -648,7 +673,7 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_ if(SystemCoreClock > hclk_frequency) { /* Set FLASH latency to lowest latency */ - status = UTILS_SetFlashLatency(hclk_frequency); + status = LL_SetFlashLatency(hclk_frequency); } /* Update SystemCoreClock variable */ @@ -672,4 +697,3 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_ * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Inc/FreeRTOSConfig.h b/Software/VNA_embedded/Inc/FreeRTOSConfig.h index d0c6f50..196dc02 100644 --- a/Software/VNA_embedded/Inc/FreeRTOSConfig.h +++ b/Software/VNA_embedded/Inc/FreeRTOSConfig.h @@ -1,7 +1,8 @@ /* USER CODE BEGIN Header */ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Portion Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Portion Copyright (C) 2019 StMicroelectronics, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -25,7 +26,7 @@ * * 1 tab == 4 spaces! */ - /* USER CODE END Header */ +/* USER CODE END Header */ #ifndef FREERTOS_CONFIG_H #define FREERTOS_CONFIG_H @@ -46,11 +47,13 @@ /* Section where include file can be added */ /* USER CODE END Includes */ -/* Ensure stdint is only used by the compiler, and not the assembler. */ +/* Ensure definitions are only used by the compiler, and not by the assembler. */ #if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__) - #include - extern uint32_t SystemCoreClock; + #include + extern uint32_t SystemCoreClock; #endif +#define configENABLE_FPU 0 +#define configENABLE_MPU 0 #define configUSE_PREEMPTION 1 #define configSUPPORT_STATIC_ALLOCATION 1 @@ -66,6 +69,11 @@ #define configUSE_MUTEXES 1 #define configQUEUE_REGISTRY_SIZE 8 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +/* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */ +/* Defaults to size_t for backward compatibility, but can be changed + if lengths will always be less than the number of bytes in a size_t. */ +#define configMESSAGE_BUFFER_LENGTH_TYPE size_t +/* USER CODE END MESSAGE_BUFFER_LENGTH_TYPE */ /* Co-routine definitions. */ #define configUSE_CO_ROUTINES 0 @@ -73,15 +81,15 @@ /* Set the following definitions to 1 to include the API function, or zero to exclude the API function. */ -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 0 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_xTaskGetSchedulerState 1 -#define INCLUDE_xTaskResumeFromISR 0 +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskResumeFromISR 0 /* Cortex-M specific definitions. */ #ifdef __NVIC_PRIO_BITS @@ -111,7 +119,7 @@ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ /* Normal assert() semantics without relying on the provision of an assert.h header file. */ /* USER CODE BEGIN 1 */ -#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );} +#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );} /* USER CODE END 1 */ /* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS @@ -121,6 +129,7 @@ standard names. */ /* IMPORTANT: This define is commented when used with STM32Cube firmware, when the timebase source is SysTick, to prevent overwriting SysTick_Handler defined within STM32Cube HAL */ + #define xPortSysTickHandler SysTick_Handler /* USER CODE BEGIN Defines */ diff --git a/Software/VNA_embedded/Inc/main.h b/Software/VNA_embedded/Inc/main.h index fb67cea..beb2f79 100644 --- a/Software/VNA_embedded/Inc/main.h +++ b/Software/VNA_embedded/Inc/main.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -29,6 +28,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" + #include "stm32g4xx_ll_ucpd.h" #include "stm32g4xx_ll_bus.h" #include "stm32g4xx_ll_cortex.h" @@ -102,5 +102,3 @@ void Error_Handler(void); #endif #endif /* __MAIN_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Inc/stm32_assert.h b/Software/VNA_embedded/Inc/stm32_assert.h index f59a230..3e124e4 100644 --- a/Software/VNA_embedded/Inc/stm32_assert.h +++ b/Software/VNA_embedded/Inc/stm32_assert.h @@ -1,20 +1,21 @@ +/* USER CODE BEGIN Header */ /** ****************************************************************************** * @file stm32_assert.h * @brief STM32 assert file. ****************************************************************************** - * @attention + * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ +/* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32_ASSERT_H @@ -50,4 +51,3 @@ #endif /* __STM32_ASSERT_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Inc/stm32g4xx_hal_conf.h b/Software/VNA_embedded/Inc/stm32g4xx_hal_conf.h index de213f4..0d7835e 100644 --- a/Software/VNA_embedded/Inc/stm32g4xx_hal_conf.h +++ b/Software/VNA_embedded/Inc/stm32g4xx_hal_conf.h @@ -1,21 +1,22 @@ +/* USER CODE BEGIN Header */ /** ****************************************************************************** * @file stm32g4xx_hal_conf.h * @author MCD Application Team * @brief HAL configuration file ****************************************************************************** - * @attention + * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ +/* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_CONF_H @@ -377,5 +378,3 @@ void assert_failed(uint8_t *file, uint32_t line); #endif #endif /* STM32G4xx_HAL_CONF_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Inc/stm32g4xx_it.h b/Software/VNA_embedded/Inc/stm32g4xx_it.h index def7573..700988d 100644 --- a/Software/VNA_embedded/Inc/stm32g4xx_it.h +++ b/Software/VNA_embedded/Inc/stm32g4xx_it.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -68,5 +67,3 @@ void UCPD1_IRQHandler(void); #endif #endif /* __STM32G4xx_IT_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Inc/usbpd.h b/Software/VNA_embedded/Inc/usbpd.h deleted file mode 100644 index 1a138bc..0000000 --- a/Software/VNA_embedded/Inc/usbpd.h +++ /dev/null @@ -1,61 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file usbpd.h - * @author MCD Application Team - * @brief This file contains the device define. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __usbpd_H -#define __usbpd_H -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbpd_core.h" -#include "usbpd_dpm_core.h" -#include "usbpd_dpm_user.h" -#include "usbpd_hw_if.h" - -/* USER CODE BEGIN 0 */ -/* USER CODE END 0 */ - -/* Global variables ---------------------------------------------------------*/ - -/* USER CODE BEGIN 1 */ -/* USER CODE END 1 */ - -/* USBPD init function */ -void MX_USBPD_Init(void); - -/* USER CODE BEGIN 2 */ -/* USER CODE END 2 */ - -#ifdef __cplusplus -} -#endif -#endif /*__usbpd_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Inc/usbpd_devices_conf.h b/Software/VNA_embedded/Inc/usbpd_devices_conf.h deleted file mode 100644 index 5acfb69..0000000 --- a/Software/VNA_embedded/Inc/usbpd_devices_conf.h +++ /dev/null @@ -1,127 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file usbpd_devices_conf.h - * @author MCD Application Team - * @brief This file contains the device define. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* CubeMX Generated */ -#define CUBEMX_GENERATED - -#ifndef USBPD_DEVICE_CONF_H -#define USBPD_DEVICE_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32g4xx_ll_bus.h" -#include "stm32g4xx_ll_dma.h" -#include "stm32g4xx_ll_gpio.h" -#include "stm32g4xx_ll_rcc.h" -#include "stm32g4xx_ll_ucpd.h" -#include "stm32g4xx_ll_pwr.h" -#include "stm32g4xx_ll_tim.h" - -/* USER CODE BEGIN Includes */ -#include "usbpd_pwr_user.h" - -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ----------------------------------------------------------------------------- - usbpd_hw.c --------------------------------------------------------------------------------*/ - -/* defined used to configure function : BSP_USBPD_GetUSPDInstance */ -#define UCPD_INSTANCE0 UCPD1 - -/* defined used to configure function : BSP_USBPD_Init_DMARxInstance,BSP_USBPD_DeInit_DMARxInstance */ -#define UCPDDMA_INSTANCE0_CLOCKENABLE_RX LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1) - -#define UCPDDMA_INSTANCE0_DMA_RX DMA1 - -#define UCPDDMA_INSTANCE0_REQUEST_RX DMA_REQUEST_UCPD1_RX - -#define UCPDDMA_INSTANCE0_LL_CHANNEL_RX LL_DMA_CHANNEL_1 - -#define UCPDDMA_INSTANCE0_CHANNEL_RX DMA1_Channel1 - -/* defined used to configure function : BSP_USBPD_Init_DMATxInstance, BSP_USBPD_DeInit_DMATxInstance */ -#define UCPDDMA_INSTANCE0_CLOCKENABLE_TX LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1) - -#define UCPDDMA_INSTANCE0_DMA_TX DMA1 - -#define UCPDDMA_INSTANCE0_REQUEST_TX DMA_REQUEST_UCPD1_TX - -#define UCPDDMA_INSTANCE0_LL_CHANNEL_TX LL_DMA_CHANNEL_2 - -#define UCPDDMA_INSTANCE0_CHANNEL_TX DMA1_Channel2 - -/* defined used to configure BSP_USBPD_SetFRSSignalling */ -#define UCPDFRS_INSTANCE0_FRSCC1 -#define UCPDFRS_INSTANCE0_FRSCC2 - -#define UCPD_INSTANCE0_ENABLEIRQ do{ \ - NVIC_SetPriority(UCPD1_IRQn,4); \ - NVIC_EnableIRQ(UCPD1_IRQn); \ - } while(0) - -/* ----------------------------------------------------------------------------- - Definitions for timer service feature --------------------------------------------------------------------------------*/ - -#define TIMX TIM3 -#define TIMX_CLK_ENABLE LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM3) -#define TIMX_CLK_DISABLE LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM3) -#define TIMX_IRQ TIM3_IRQn -#define TIMX_CHANNEL_CH1 LL_TIM_CHANNEL_CH1 -#define TIMX_CHANNEL_CH2 LL_TIM_CHANNEL_CH2 -#define TIMX_CHANNEL_CH3 LL_TIM_CHANNEL_CH3 -#define TIMX_CHANNEL_CH4 LL_TIM_CHANNEL_CH4 -#define TIMX_CHANNEL1_SETEVENT do{ \ - LL_TIM_OC_SetCompareCH1(TIMX, (TimeUs + TIMX->CNT) % TIM_MAX_TIME);\ - LL_TIM_ClearFlag_CC1(TIMX); \ - }while(0) -#define TIMX_CHANNEL2_SETEVENT do{ \ - LL_TIM_OC_SetCompareCH2(TIMX, (TimeUs + TIMX->CNT) % TIM_MAX_TIME);\ - LL_TIM_ClearFlag_CC2(TIMX); \ - }while(0) -#define TIMX_CHANNEL3_SETEVENT do{ \ - LL_TIM_OC_SetCompareCH3(TIMX, (TimeUs + TIMX->CNT) % TIM_MAX_TIME);\ - LL_TIM_ClearFlag_CC3(TIMX); \ - }while(0) -#define TIMX_CHANNEL4_SETEVENT do{ \ - LL_TIM_OC_SetCompareCH4(TIMX, (TimeUs + TIMX->CNT) % TIM_MAX_TIME);\ - LL_TIM_ClearFlag_CC4(TIMX); \ - }while(0) -#define TIMX_CHANNEL1_GETFLAG LL_TIM_IsActiveFlag_CC1 -#define TIMX_CHANNEL2_GETFLAG LL_TIM_IsActiveFlag_CC2 -#define TIMX_CHANNEL3_GETFLAG LL_TIM_IsActiveFlag_CC3 -#define TIMX_CHANNEL4_GETFLAG LL_TIM_IsActiveFlag_CC4 - -#ifdef __cplusplus - } -#endif - -#endif /* USBPD_DEVICE_CONF_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Inc/usbpd_dpm_conf.h b/Software/VNA_embedded/Inc/usbpd_dpm_conf.h deleted file mode 100644 index 2c61280..0000000 --- a/Software/VNA_embedded/Inc/usbpd_dpm_conf.h +++ /dev/null @@ -1,121 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file usbpd_dpm_conf.h - * @author MCD Application Team - * @brief Header file for stack/application settings file - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -#ifndef __USBPD_DPM_CONF_H_ -#define __USBPD_DPM_CONF_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbpd_pdo_defs.h" -#include "usbpd_vdm_user.h" -#include "usbpd_dpm_user.h" - -/* USER CODE BEGIN Includes */ -/* Section where include file can be added */ - -/* USER CODE END Includes */ - -/* Define ------------------------------------------------------------------*/ -/* Define VID, PID,... manufacturer parameters */ -#define USBPD_VID (0x0483u) /*!< Vendor ID (assigned by the USB-IF) */ -#define USBPD_PID (0x0002u) /*!< Product ID (assigned by the manufacturer) */ -#define USBPD_XID (0xF0000003u) /*!< Value provided by the USB-IF assigned to the product */ - -/* USER CODE BEGIN Define */ -/* Section where Define can be added */ - -/* USER CODE END Define */ - -/* Exported typedef ----------------------------------------------------------*/ -/* USER CODE BEGIN Typedef */ -/* Section where Typedef can be added */ - -/* USER CODE END Typedef */ - -/* Private variables ---------------------------------------------------------*/ -#ifndef __USBPD_DPM_CORE_C -extern USBPD_SettingsTypeDef DPM_Settings[USBPD_PORT_COUNT]; -#else /* __USBPD_DPM_CORE_C */ -USBPD_SettingsTypeDef DPM_Settings[USBPD_PORT_COUNT] = -{ - { - .PE_SupportedSOP = USBPD_SUPPORTED_SOP_SOP , /* Supported SOP : SOP, SOP' SOP" SOP'Debug SOP"Debug */ - .PE_SpecRevision = USBPD_SPECIFICATION_REV2,/* spec revision value */ - .PE_DefaultRole = USBPD_PORTPOWERROLE_SNK, /* Default port role */ - .PE_RoleSwap = USBPD_FALSE, /* support port role swap */ - .PE_VDMSupport = USBPD_FALSE, - .PE_RespondsToDiscovSOP = USBPD_FALSE, /*!< Can respond successfully to a Discover Identity */ - .PE_AttemptsDiscovSOP = USBPD_FALSE, /*!< Can send a Discover Identity */ - .PE_PingSupport = USBPD_FALSE, /* support Ping (only for PD3.0) */ - .PE_CapscounterSupport = USBPD_FALSE, /* support caps counter */ - .CAD_RoleToggle = USBPD_FALSE, /* CAD role toggle */ - .CAD_TryFeature = 0, /* CAD try feature */ - .CAD_AccesorySupport = USBPD_FALSE, /* CAD accessory support */ - .PE_PD3_Support.d = /*!< PD3 SUPPORT FEATURE */ - { - .PE_UnchunkSupport = USBPD_FALSE, /* support Unchunked mode (valid only spec revision 3.0) */ - .PE_FastRoleSwapSupport = USBPD_FALSE, /* support fast role swap only spec revsion 3.0 */ - .Is_GetPPSStatus_Supported = USBPD_FALSE, /*!< PPS message NOT supported by PE stack */ - .Is_SrcCapaExt_Supported = USBPD_FALSE, /*!< Source_Capabilities_Extended message supported or not by DPM */ - .Is_Alert_Supported = USBPD_FALSE, /*!< Alert message supported or not by DPM */ - .Is_GetStatus_Supported = USBPD_FALSE, /*!< Status message supported or not by DPM (Is_Alert_Supported should be enabled) */ - .Is_GetManufacturerInfo_Supported = USBPD_FALSE, /*!< Manufacturer_Info message supported or not by DPM */ - .Is_GetCountryCodes_Supported = USBPD_FALSE, /*!< Country_Codes message supported or not by DPM */ - .Is_GetCountryInfo_Supported = USBPD_FALSE, /*!< Country_Info message supported or not by DPM */ - .Is_SecurityRequest_Supported = USBPD_FALSE, /*!< Security_Response message supported or not by DPM */ - .Is_FirmUpdateRequest_Supported = USBPD_FALSE, /*!< Firmware update response message supported by PE */ - .Is_SnkCapaExt_Supported = USBPD_FALSE, /*!< Sink_Capabilities_Extended message supported by PE */ - }, - - .CAD_SRCToggleTime = 0, /* uint8_t CAD_SRCToggleTime; */ - .CAD_SNKToggleTime = 0, /* uint8_t CAD_SNKToggleTime; */ - } -}; - -#endif - -/* USER CODE BEGIN Variable */ -/* Section where Variable can be added */ - -/* USER CODE END Variable */ - -/* Exported constants --------------------------------------------------------*/ -/* USER CODE BEGIN Constant */ -/* Section where Constant can be added */ - -/* USER CODE END Constant */ - -/* Exported macro ------------------------------------------------------------*/ -/* USER CODE BEGIN Macro */ -/* Section where Macro can be added */ - -/* USER CODE END Macro */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBPD_DPM_CONF_H_ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Inc/usbpd_dpm_core.h b/Software/VNA_embedded/Inc/usbpd_dpm_core.h deleted file mode 100644 index 3c3aec5..0000000 --- a/Software/VNA_embedded/Inc/usbpd_dpm_core.h +++ /dev/null @@ -1,75 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file usbpd_dpm_core.h - * @author MCD Application Team - * @brief Header file for usbpd_dpm_core.c file - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -#ifndef __USBPD_DPM_CORE_H_ -#define __USBPD_DPM_CORE_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Exported typedef ----------------------------------------------------------*/ -/* USER CODE BEGIN typedef */ - -/* USER CODE END typedef */ - -/* Exported define -----------------------------------------------------------*/ -/* USER CODE BEGIN define */ - -/* USER CODE END define */ - -/* Exported constants --------------------------------------------------------*/ -/* USER CODE BEGIN constants */ - -/* USER CODE END constants */ - -/* Exported macro ------------------------------------------------------------*/ -/* USER CODE BEGIN macro */ - -/* USER CODE END macro */ - -/* Exported variables --------------------------------------------------------*/ -extern USBPD_ParamsTypeDef DPM_Params[USBPD_PORT_COUNT]; -/* USER CODE BEGIN variables */ - -/* USER CODE END variables */ - -/* Exported functions --------------------------------------------------------*/ -USBPD_StatusTypeDef USBPD_DPM_InitCore(void); -USBPD_StatusTypeDef USBPD_DPM_InitOS(void); -void USBPD_DPM_Run(void); -void USBPD_DPM_TimerCounter(void); -/* USER CODE BEGIN functions */ - -/* USER CODE END functions */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBPD_DPM_H_ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Inc/usbpd_dpm_user.h b/Software/VNA_embedded/Inc/usbpd_dpm_user.h deleted file mode 100644 index 77f98a3..0000000 --- a/Software/VNA_embedded/Inc/usbpd_dpm_user.h +++ /dev/null @@ -1,136 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file usbpd_dpm_user.h - * @author MCD Application Team - * @brief Header file for usbpd_dpm_user.c file - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -#ifndef __USBPD_DPM_USER_H_ -#define __USBPD_DPM_USER_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -/* USER CODE BEGIN Include */ - -/* USER CODE END Include */ - -/** @addtogroup STM32_USBPD_APPLICATION - * @{ - */ - -/** @addtogroup STM32_USBPD_APPLICATION_DPM_USER - * @{ - */ - -/* Exported typedef ----------------------------------------------------------*/ -/* USER CODE BEGIN Typedef */ - -/* USER CODE END Typedef */ - -/* Exported define -----------------------------------------------------------*/ -/* USER CODE BEGIN Define */ - -/* USER CODE END Define */ - -/* Exported constants --------------------------------------------------------*/ -/* USER CODE BEGIN Constant */ - -/* USER CODE END Constant */ - -/* Exported macro ------------------------------------------------------------*/ -/* USER CODE BEGIN Macro */ - -/* USER CODE END Macro */ - -/* Exported variables --------------------------------------------------------*/ -/* USER CODE BEGIN Private_Variables */ - -/* USER CODE END Private_Variables */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup USBPD_USER_EXPORTED_FUNCTIONS - * @{ - */ -/** @addtogroup USBPD_USER_EXPORTED_FUNCTIONS_GROUP1 - * @{ - */ -USBPD_StatusTypeDef USBPD_DPM_UserInit(void); -void USBPD_DPM_UserExecute(void const *argument); -void USBPD_DPM_UserCableDetection(uint8_t PortNum, USBPD_CAD_EVENT State); -void USBPD_DPM_WaitForTime(uint32_t Time); -void USBPD_DPM_UserTimerCounter(uint8_t PortNum); - -/** - * @} - */ - -/** @addtogroup USBPD_USER_EXPORTED_FUNCTIONS_GROUP2 - * @{ - */ -USBPD_StatusTypeDef USBPD_DPM_SetupNewPower(uint8_t PortNum); -void USBPD_DPM_HardReset(uint8_t PortNum, USBPD_PortPowerRole_TypeDef CurrentRole, USBPD_HR_Status_TypeDef Status); -USBPD_StatusTypeDef USBPD_DPM_EvaluatePowerRoleSwap(uint8_t PortNum); -void USBPD_DPM_Notification(uint8_t PortNum, USBPD_NotifyEventValue_TypeDef EventVal); -USBPD_StatusTypeDef USBPD_DPM_IsContractStillValid(uint8_t PortNum); -void USBPD_DPM_ExtendedMessageReceived(uint8_t PortNum, USBPD_ExtendedMsg_TypeDef MsgType, uint8_t *ptrData, uint16_t DataSize); -void USBPD_DPM_GetDataInfo(uint8_t PortNum, USBPD_CORE_DataInfoType_TypeDef DataId , uint8_t *Ptr, uint32_t *Size); -void USBPD_DPM_SetDataInfo(uint8_t PortNum, USBPD_CORE_DataInfoType_TypeDef DataId , uint8_t *Ptr, uint32_t Size); -USBPD_StatusTypeDef USBPD_DPM_EvaluateRequest(uint8_t PortNum, USBPD_CORE_PDO_Type_TypeDef *PtrPowerObject); -void USBPD_DPM_SNK_EvaluateCapabilities(uint8_t PortNum, uint32_t *PtrRequestData, USBPD_CORE_PDO_Type_TypeDef *PtrPowerObjectType); -uint32_t USBPD_DPM_SNK_EvaluateMatchWithSRCPDO(uint8_t PortNum, uint32_t SrcPDO, uint32_t* PtrRequestedVoltage, uint32_t* PtrRequestedPower); -void USBPD_DPM_PowerRoleSwap(uint8_t PortNum, USBPD_PortPowerRole_TypeDef CurrentRole, USBPD_PRS_Status_TypeDef Status); -USBPD_StatusTypeDef USBPD_DPM_EvaluateVconnSwap(uint8_t PortNum); -USBPD_StatusTypeDef USBPD_DPM_PE_VconnPwr(uint8_t PortNum, USBPD_FunctionalState State); -USBPD_StatusTypeDef USBPD_DPM_EvaluateDataRoleSwap(uint8_t PortNum); -USBPD_FunctionalState USBPD_DPM_IsPowerReady(uint8_t PortNum, USBPD_VSAFE_StatusTypeDef Vsafe); - -/** - * @} - */ - -/** @addtogroup USBPD_USER_EXPORTED_FUNCTIONS_GROUP3 - * @{ - */ -/* USER CODE BEGIN Function */ - -/* USER CODE END Function */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBPD_DPM_USER_H_ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Inc/usbpd_pdo_defs.h b/Software/VNA_embedded/Inc/usbpd_pdo_defs.h deleted file mode 100644 index bbf381b..0000000 --- a/Software/VNA_embedded/Inc/usbpd_pdo_defs.h +++ /dev/null @@ -1,137 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file usbpd_pdo_defs.h - * @author MCD Application Team - * @brief Header file for definition of PDO/APDO values for 2 ports(DRP/SNK) configuration - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -#ifndef __USBPD_PDO_DEF_H_ -#define __USBPD_PDO_DEF_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ - -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Define ------------------------------------------------------------------*/ - -/* USER CODE BEGIN Define */ - -/* USER CODE END Define */ - -/* Exported typedef ----------------------------------------------------------*/ - -/* USER CODE BEGIN typedef */ - -/** - * @brief USBPD Port PDO Structure definition - * - */ - -/* USER CODE END typedef */ - -/* Exported define -----------------------------------------------------------*/ - -/* USER CODE BEGIN Exported_Define */ - -#define USBPD_CORE_PDO_SRC_FIXED_MAX_CURRENT 3 -#define USBPD_CORE_PDO_SNK_FIXED_MAX_CURRENT 1500 - -/* USER CODE END Exported_Define */ - -/* Exported constants --------------------------------------------------------*/ - -/* USER CODE BEGIN constants */ - -/* USER CODE END constants */ - -/* Exported macro ------------------------------------------------------------*/ - -/* USER CODE BEGIN macro */ - -/* USER CODE END macro */ - -/* Exported variables --------------------------------------------------------*/ - -/* USER CODE BEGIN variables */ - -/* USER CODE END variables */ - -#ifndef __USBPD_PWR_IF_C -extern const uint32_t PORT0_PDO_ListSRC[USBPD_MAX_NB_PDO]; -extern const uint32_t PORT0_PDO_ListSNK[USBPD_MAX_NB_PDO]; -extern const uint32_t PORT1_PDO_ListSRC[USBPD_MAX_NB_PDO]; -extern const uint32_t PORT1_PDO_ListSNK[USBPD_MAX_NB_PDO]; -#else -/* Definition of Source PDO for Port 0 */ -const uint32_t PORT0_PDO_ListSRC[USBPD_MAX_NB_PDO] = -{ - /* PDO 1 */ - (0x00000000U), - /* PDO 2 */ - (0x00000000U), - /* PDO 3 */ - (0x00000000U), - /* PDO 4 */ - (0x00000000U), - /* PDO 5 */ - (0x00000000U), - /* PDO 6 */ - (0x00000000U), - /* PDO 7 */ - (0x00000000U) -}; - -/* Definition of Sink PDO for Port 0 */ -const uint32_t PORT0_PDO_ListSNK[USBPD_MAX_NB_PDO] = -{ - /* PDO 1 */ - (0x00000000U), - /* PDO 2 */ - (0x00000000U), - /* PDO 3 */ - (0x00000000U), - /* PDO 4 */ - (0x00000000U), - /* PDO 5 */ - (0x00000000U), - /* PDO 6 */ - (0x00000000U), - /* PDO 7 */ - (0x00000000U) -}; - -#endif - -/* Exported functions --------------------------------------------------------*/ - -/* USER CODE BEGIN functions */ - -/* USER CODE END functions */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBPD_PDO_DEF_H_ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Inc/usbpd_pwr_if.h b/Software/VNA_embedded/Inc/usbpd_pwr_if.h deleted file mode 100644 index 138ab81..0000000 --- a/Software/VNA_embedded/Inc/usbpd_pwr_if.h +++ /dev/null @@ -1,229 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file usbpd_pwr_if.h - * @author MCD Application Team - * @brief This file contains the headers of usbpd_pw_if.h. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -#ifndef __USBPD_PW_IF_H_ -#define __USBPD_PW_IF_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbpd_def.h" - -/** @addtogroup STM32_USBPD_APPLICATION - * @{ - */ - -/** @addtogroup STM32_USBPD_APPLICATION_POWER_IF - * @{ - */ - -/* Exported typedef ----------------------------------------------------------*/ -/* Exported define -----------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup USBPD_USER_PWR_IF_Exported_Macros USBPD PWR IF Exported Macros - * @{ - */ - -/* Macros used to convert values into PDO representation */ -#define PWR_V_20MV(_V_) ((uint16_t)(( (_V_) * 1000.0) / 20.0)) /* From Volt to 20mV multiples */ -#define PWR_V_50MV(_V_) ((uint16_t)(( (_V_) * 1000.0) / 50.0)) /* From Volt to 50mV multiples */ -#define PWR_V_100MV(_V_) ((uint16_t)(( (_V_) * 1000.0) / 100.0)) /* From Volt to 100mV multiples */ -#define PWR_A_10MA(_A_) ((uint16_t)(( (_A_) * 1000.0) / 10.0)) /* From Ampere to 10mA multiples */ -#define PWR_A_50MA(_A_) ((uint16_t)(( (_A_) * 1000.0) / 50.0)) /* From Ampere to 50mA multiples */ -#define PWR_W(_W_) ((uint16_t)(( (_W_) * 1000.0) / 250.0)) /* From Watt to 250mW multiples */ - -/* Macros used to get values from PDO representation */ -#define PWR_DECODE_50MV(_Value_) ((uint16_t)(( (float)(_Value_) * 50.0))) /* From 50mV multiples to mV */ -#define PWR_DECODE_100MV(_Value_) ((uint16_t)(( (float)(_Value_) * 100.0))) /* From 100mV multiples to mV */ -#define PWR_DECODE_10MA(_Value_) ((uint16_t)(( (float)(_Value_) * 10.0))) /* From 10mA multiples to mA */ -#define PWR_DECODE_50MA(_Value_) ((uint16_t)(( (float)(_Value_) * 50.0))) /* From 50mA multiples to mA */ -#define PWR_DECODE_MW(_Value_) ((uint16_t)(( (float)(_Value_) * 250.0))) /* From 250mW multiples to mW */ - -#define USBPD_PORT_IsValid(__Port__) ((__Port__) < (USBPD_PORT_COUNT)) - -/** - * @} - */ - -/* Exported variables --------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup STM32_USBPD_APPLICATION_POWER_IF_Exported_Functions USBPD PWR IF Exported Functions - * @{ - */ - -/** - * @brief Initialize structures and variables related to power board profiles - * used by Sink and Source, for all available ports. - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_PWR_IF_Init(void); - -/** - * @brief Sets the required power profile - * @param PortNum Port number - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_PWR_IF_SetProfile(uint8_t PortNum); - -/** - * @brief Resets the Power Board - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_PWR_IF_PowerResetGlobal(void); - -/** - * @brief Resets the Power on a specified port - * @param PortNum Port number - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_PWR_IF_PowerReset(uint8_t PortNum); - -/** - * @brief Checks if the power on a specified port is ready - * @param PortNum Port number - * @param Vsafe Vsafe status based on @ref USBPD_VSAFE_StatusTypeDef - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_PWR_IF_SupplyReady(uint8_t PortNum, USBPD_VSAFE_StatusTypeDef Vsafe); - -/** - * @brief Initialize the power on a specified port - * @param PortNum Port number - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_PWR_IF_InitPower(uint8_t PortNum); - -/** - * @brief Enable VBUS power on a specified port - * @param PortNum Port number - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_PWR_IF_VBUSEnable(uint8_t PortNum); - -/** - * @brief Disable VBUS power on a specified port - * @param PortNum Port number - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_PWR_IF_VBUSDisable(uint8_t PortNum); - -/** - * @brief Disable the SNK to stop current consumption - * @param PortNum Port number - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_PWR_IF_SNKDisable(uint8_t PortNum); - -/** - * @brief Checks if the power on a specified port is enabled - * @param PortNum Port number - * @retval ENABLE or DISABLE - */ -USBPD_FunctionalState USBPD_PWR_IF_VBUSIsEnabled(uint8_t PortNum); - -/** - * @brief Reads the voltage and the current on a specified port - * @param PortNum Port number - * @param pVoltage The Voltage in mV - * @param pCurrent The Current in mA - * @retval ENABLE or DISABLE - */ -USBPD_StatusTypeDef USBPD_PWR_IF_ReadVA(uint8_t PortNum, uint16_t *pVoltage, uint16_t *pCurrent); - -/** - * @brief Enables the VConn on the port. - * @param PortNum Port number - * @param CC Specifies the CCx to be selected based on @ref CCxPin_TypeDef structure - * @retval USBPD Status - */ -USBPD_StatusTypeDef USBPD_PWR_IF_Enable_VConn(uint8_t PortNum, CCxPin_TypeDef CC); - -/** - * @brief Disable the VConn on the port. - * @param PortNum Port number - * @param CC Specifies the CCx to be selected based on @ref CCxPin_TypeDef structure - * @retval USBPD Status - */ -USBPD_StatusTypeDef USBPD_PWR_IF_Disable_VConn(uint8_t PortNum, CCxPin_TypeDef CC); - -/** - * @brief Allow PDO data reading from PWR_IF storage. - * @param PortNum Port number - * @param DataId Type of data to be read from PWR_IF - * This parameter can be one of the following values: - * @arg @ref USBPD_CORE_DATATYPE_SRC_PDO Source PDO reading requested - * @arg @ref USBPD_CORE_DATATYPE_SNK_PDO Sink PDO reading requested - * @param Ptr Pointer on address where PDO values should be written (u8 pointer) - * @param Size Pointer on nb of u32 written by PWR_IF (nb of PDOs) - * @retval None - */ -void USBPD_PWR_IF_GetPortPDOs(uint8_t PortNum, USBPD_CORE_DataInfoType_TypeDef DataId, uint8_t *Ptr, uint32_t *Size); - -/** - * @brief Find out SRC PDO pointed out by a position provided in a Request DO (from Sink). - * @param PortNum Port number - * @param RdoPosition RDO Position in list of provided PDO - * @param Pdo Pointer on PDO value pointed out by RDO position (u32 pointer) - * @retval Status of search - * USBPD_OK : Src PDO found for requested DO position (output Pdo parameter is set) - * USBPD_FAIL : Position is not compliant with current Src PDO for this port (no corresponding PDO value) - */ -USBPD_StatusTypeDef USBPD_PWR_IF_SearchRequestedPDO(uint8_t PortNum, uint32_t RdoPosition, uint32_t *Pdo); - -/** - * @brief the function is called in case of critical issue is detected to switch in safety mode. - * @retval None - */ -void USBPD_PWR_IF_Alarm(void); - -/** - * @brief Function to check validity between SNK PDO and power user settings - * @param PortNum Port number - * @retval USBPD Status - */ -USBPD_StatusTypeDef USBPD_PWR_IF_CheckUpdateSNKPower(uint8_t PortNum); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBPD_PW_IF_H_ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Inc/usbpd_pwr_user.h b/Software/VNA_embedded/Inc/usbpd_pwr_user.h deleted file mode 100644 index dd8d739..0000000 --- a/Software/VNA_embedded/Inc/usbpd_pwr_user.h +++ /dev/null @@ -1,236 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file usbpd_pwr_user.h - * @author MCD Application Team - * @brief Header file for usbpd_pwr_user.c file - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBPD_PWR_USER_H_ -#define __USBPD_PWR_USER_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32g4xx.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup POWER - * @{ - */ - -/** @defgroup POWER_Exported_Types Exported Types - * @{ - */ - -/** - * @brief POWER Status - */ -typedef enum -{ - PWR_OK = 0, - PWR_ERROR -} PWR_StatusTypeDef; - -/** - * @brief Power role - */ -typedef enum -{ - POWER_ROLE_SOURCE = 0, - POWER_ROLE_SINK, - POWER_ROLE_DUAL -} PWR_PowerRoleTypeDef; - -/** - * @brief Voltage control mode - */ -typedef enum -{ - DCDC_CTRL_MODE_UNKNOWN = 0, - DCDC_CTRL_MODE_GPIO, - DCDC_CTRL_MODE_PWM, -} PWR_DCDCCtrlModeTypeDef; - -/** - * @brief VBUS connection status - */ -typedef enum -{ - VBUS_CONNECTED = 0, - VBUS_NOT_CONNECTED -} PWR_VBUSConnectionStatusTypeDef; - -/** - * @brief VBUS Detection Callback - */ -typedef void PWR_VBUSDetectCallbackFunc(uint32_t PortId, - PWR_VBUSConnectionStatusTypeDef VBUSConnectionStatus); - -/** - * @} - */ - -/** @defgroup POWER_Exported_Constants Exported Constants - * @{ - */ -/** - * @brief Number of TypeC ports - */ -#define PWR_TYPEC_PORT_NB 2 - -/** - * @brief Type-C port identifier - */ -#define TYPE_C_PORT_1 0 -#define TYPE_C_PORT_2 1 - -/** - * @brief CC pin identifier - */ -#define TYPE_C_CC1 1 -#define TYPE_C_CC2 2 - -/** - * @brief VBUS disconnection threshold values (in mV) - */ -#define BSP_PWR_HIGH_VBUS_THRESHOLD (4500) -#define BSP_PWR_LOW_VBUS_THRESHOLD (800) - -/** - * @brief VBUS discharge parameters - */ -#define BSP_PWR_DISCHARGE_MARGIN (500) -#define BSP_PWR_DISCHARGE_TIME (6) - -/** - * @brief Calibration settings - */ -#define BSP_PWR_DCDC_PRECISION (40) /* DCDC output precision set to 40mV (Noise)*/ -#define BSP_PWR_CALIBRATION_ENABLED (1) -#define BSP_PWR_CALIBRATION_DISABLED (0) - -/** - * @brief Standard VBUS voltage levels - */ -#define BSP_PWR_VBUS_5V 5000 -#define BSP_PWR_VBUS_9V 9000 -#define BSP_PWR_VBUS_15V 15000 - -/** - * @brief power timeout - */ -#define BSP_PWR_TIMEOUT_PDO 250u -#define BSP_PWR_TIMEOUT_APDO 25u - -/** - * @brief Invalid value set during issue with voltage setting - */ -#define BSP_PWR_INVALID_VALUE 0xFFFFFFFFu - -/** - * @} - */ - -/** @defgroup POWER_Exported_Functions Exported Functions - * @{ - */ -PWR_StatusTypeDef BSP_PWR_VBUSInit(uint32_t PortId); - -PWR_StatusTypeDef BSP_PWR_VBUSDeInit(uint32_t PortId); - -PWR_StatusTypeDef BSP_PWR_VBUSOn(uint32_t PortId); - -PWR_StatusTypeDef BSP_PWR_VBUSOff(uint32_t PortId); - -PWR_StatusTypeDef BSP_PWR_VBUSSetVoltage_Fixed(uint32_t PortNum, - uint32_t VbusTargetInmv, - uint32_t OperatingCurrent, - uint32_t MaxOperatingCurrent); - -PWR_StatusTypeDef BSP_PWR_VBUSSetVoltage_Variable(uint32_t PortNum, - uint32_t VbusTargetMaxInmv, - uint32_t VbusTargetMinInmv, - uint32_t OperatingCurrent, - uint32_t MaxOperatingCurrent); - -PWR_StatusTypeDef BSP_PWR_VBUSSetVoltage_Battery(uint32_t PortId, - uint32_t VbusTargetMin, - uint32_t VbusTargetMax, - uint32_t OperatingPower, - uint32_t MaxOperatingPower); - -PWR_StatusTypeDef BSP_PWR_VBUSSetVoltage_APDO(uint32_t PortId, - uint32_t VbusTargetInmv, - uint32_t OperatingCurrent, - int32_t Delta); - -uint32_t BSP_PWR_VBUSGetVoltage(uint32_t PortId); - -int32_t BSP_PWR_VBUSGetCurrent(uint32_t PortId); - -PWR_StatusTypeDef BSP_PWR_VCONNInit(uint32_t PortId, - uint32_t CCPinId); - -PWR_StatusTypeDef BSP_PWR_VCONNDeInit(uint32_t PortId, - uint32_t CCPinId); - -PWR_StatusTypeDef BSP_PWR_VCONNOn(uint32_t PortId, - uint32_t CCPinId); - -PWR_StatusTypeDef BSP_PWR_VCONNOff(uint32_t PortId, - uint32_t CCPinId); - -void BSP_PWR_SetVBUSDisconnectionThreshold(uint32_t PortId, - uint32_t VoltageThreshold); - -PWR_StatusTypeDef BSP_PWR_RegisterVBUSDetectCallback(uint32_t PortId, - PWR_VBUSDetectCallbackFunc * pfnVBUSDetectCallback); - -uint8_t BSP_PWR_VBUSIsOn(uint32_t PortId); - -uint8_t BSP_PWR_VCONNIsOn(uint32_t PortId, - uint32_t CCPinId); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32G081B_EVAL_POWER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Inc/usbpd_vdm_user.h b/Software/VNA_embedded/Inc/usbpd_vdm_user.h deleted file mode 100644 index edfb684..0000000 --- a/Software/VNA_embedded/Inc/usbpd_vdm_user.h +++ /dev/null @@ -1,61 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file usbpd_vdm_user.h - * @author MCD Application Team - * @brief Header file for usbpd_vdm_user.c file - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -#ifndef __USBPD_VDM_USER_H_ -#define __USBPD_VDM_USER_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -/** @addtogroup STM32_USBPD_APPLICATION - * @{ - */ - -/** @addtogroup STM32_USBPD_APPLICATION_VDM_USER - * @{ - */ - -/* Exported typedef ----------------------------------------------------------*/ -/* Exported define -----------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported variables --------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -USBPD_StatusTypeDef USBPD_VDM_UserInit(uint8_t PortNum); -void USBPD_VDM_UserReset(uint8_t PortNum); - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBPD_VDM_USER_H_ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Makefile b/Software/VNA_embedded/Makefile index ec8f4f3..acfa272 100644 --- a/Software/VNA_embedded/Makefile +++ b/Software/VNA_embedded/Makefile @@ -58,7 +58,7 @@ CXX_SOURCES := $(foreach sdir,$(SOURCES_DIR),$(wildcard $(sdir)/*.cpp)) # ASM sources ASM_SOURCES = \ -startup/startup_stm32g431xx.s +Startup/startup_stm32g431cbux.s ###################################### @@ -156,11 +156,11 @@ CXXFLAGS += -MMD -MP # LDFLAGS ####################################### # link script -LDSCRIPT = STM32G431CBUx_FLASH.ld +LDSCRIPT = STM32G431CBUX_FLASH.ld # libraries -LIBS = -lm -l:USBPDCORE_PD3_FULL_CM4_wc32.a -LIBDIR = -LMiddlewares/ST/STM32_USBPD_Library/Core/lib +LIBS = -lm #-l:USBPDCORE_PD3_FULL_CM4_wc32.a +#LIBDIR = -LMiddlewares/ST/STM32_USBPD_Library/Core/lib LDFLAGS = $(MCU) -specs=nosys.specs -specs=nano.specs $(LIBDIR) -T$(LDSCRIPT) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map -Wl,--gc-sections -fno-exceptions -fno-rtti # default action: build all diff --git a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_core.h b/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_core.h deleted file mode 100644 index 084fd0d..0000000 --- a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_core.h +++ /dev/null @@ -1,939 +0,0 @@ -/** - ****************************************************************************** - * @file usbpd_core.h - * @author MCD Application Team - * @brief This file contains the core stack API. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -#ifndef __USBPD_CORE_H_ -#define __USBPD_CORE_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbpd_def.h" -#if defined(USBPDCORE_TCPM_SUPPORT) -#include "tcpc.h" -#endif /* USBPDCORE_TCPM_SUPPORT */ - -/** @addtogroup STM32_USBPD_LIBRARY - * @{ - */ - -/** @addtogroup USBPD_CORE - * @{ - */ - -/** @addtogroup USBPD_CORE_CAD - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup USBPD_CORE_CAD_Exported_Types USBPD CORE CAD Exported Types - * @{ - */ - -/** - * @brief funtion return value @ref USBPD_CORE_CAD - * @{ - */ -typedef enum -{ - USBPD_CAD_OK, /*!< USBPD CAD Status OK */ - USBPD_CAD_INVALID_PORT, /*!< USBPD CAD Status INVALID PORT */ - USBPD_CAD_ERROR, /*!< USBPD CAD Status ERROR */ - USBPD_CAD_MALLOCERROR, /*!< USBPD CAD Status ERROR MALLOC */ - USBPD_CAD_INVALIDRESISTOR /*!< USBPD CAD Status INVALID RESISTOR */ -} -USBPD_CAD_StatusTypeDef; -/** - * @} - */ - -/** - * @brief activation value @ref USBPD_CORE_CAD - * @{ - */ - typedef enum - { - USBPD_CAD_DISABLE, /*!< USBPD CAD activation status Disable */ - USBPD_CAD_ENABLE /*!< USBPD CAD activation status Enable */ - } USBPD_CAD_activation; -/** - * @} - */ - -/** - * @brief CallBacks exposed by the @ref USBPD_CORE_CAD - */ -typedef struct -{ - /** - * @brief CallBack reporting events on a specified port. - * @param PortNum The handle of the port - * @param State CAD state - * @param Cc The Communication Channel for the USBPD communication - * @retval None - */ - void (*USBPD_CAD_CallbackEvent)(uint8_t PortNum, USBPD_CAD_EVENT State, CCxPin_TypeDef Cc); - /** - * @brief CallBack to wakeup the CAD. - * @retval None - */ - void (*USBPD_CAD_WakeUp)(void); -}USBPD_CAD_Callbacks; - -/** - * @} - */ - -/** @defgroup USBPD_CORE_CAD_Exported_Functions_Grp1 USBPD CORE CAD Exported Functions - * @{ - */ -/** - * @brief Initialize the CAD module for a specified port. - * @param PortNum Index of current used port - * @param CallbackFunctions CAD port callback function - * @param Settings Pointer on @ref USBPD_SettingsTypeDef structure - * @param Params Pointer on @ref USBPD_ParamsTypeDef structure - * @retval USBPD_CAD status - */ -USBPD_CAD_StatusTypeDef USBPD_CAD_Init(uint8_t PortNum, const USBPD_CAD_Callbacks *CallbackFunctions, USBPD_SettingsTypeDef *Settings, USBPD_ParamsTypeDef *Params); - -/** - * @brief Main CAD task. - * @retval Timing in ms - */ -uint32_t USBPD_CAD_Process(void); - -/** - * @brief Enable or Disable CAD port. - * @param PortNum Index of current used port - * @param State The new state of the port - * @retval None - */ -void USBPD_CAD_PortEnable(uint8_t PortNum, USBPD_CAD_activation State); - -/** - * @brief Set as SNK. - * @param PortNum Index of current used port - * @retval None - */ -void USBPD_CAD_AssertRd(uint8_t PortNum); - -/** - * @brief Set as SRC. - * @param PortNum Index of current used port - * @retval None - */ -void USBPD_CAD_AssertRp(uint8_t PortNum); - -/** - * @brief Set type C state machine in error recovery state - * @param PortNum Index of current used port - * @retval None - */ -void USBPD_CAD_EnterErrorRecovery(uint8_t PortNum); - -/** - * @brief Set the default Rd resistor - * @param PortNum Index of current used port - * @param RdValue - * @retval USBPD_CAD_OK or USBPD_CAD_INVALIDRESISTOR - */ -USBPD_CAD_StatusTypeDef USBPD_CAD_SetRpResistor(uint8_t PortNum, CAD_RP_Source_Current_Adv_Typedef RdValue); -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup USBPD_CORE_TRACE - * @{ - */ - -/** @defgroup USBPD_CORE_TRACE_Exported_Types USBPD CORE TRACE Exported Types - * @{ - */ -typedef enum { - USBPD_TRACE_FORMAT_TLV = 0, - USBPD_TRACE_MESSAGE_IN = 1, - USBPD_TRACE_MESSAGE_OUT = 2, - USBPD_TRACE_CADEVENT = 3, - USBPD_TRACE_PE_STATE = 4, - USBPD_TRACE_CAD_LOW = 5, - USBPD_TRACE_DEBUG = 6, - USBPD_TRACE_SRC = 7, - USBPD_TRACE_SNK = 8, - USBPD_TRACE_NOTIF = 9, - USBPD_TRACE_POWER =10 -} -TRACE_EVENT; - -typedef void (*TRACE_ENTRY_POINT)(TRACE_EVENT type, uint8_t port, uint8_t sop, uint8_t *ptr, uint32_t size); - -extern uint32_t Crc; -extern TRACE_ENTRY_POINT USBPD_Trace; - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup USBPD_CORE_PE - * @{ - */ - -#if defined(USBPDCORE_SVDM) || defined(USBPDCORE_UVDM) || defined(USBPDCORE_CABLE) -/** @defgroup USBPD_CORE_VDM_Exported_Callback USBPD CORE VDM Exported Callback - * @{ - */ - -/** - * @brief CallBacks exposed by the @ref USBPD_CORE_PE - * */ -typedef struct -{ -#if defined(USBPDCORE_SVDM) || defined(USBPDCORE_CABLE) - /** - * @brief VDM Discovery identity callback (answer to Discover Identity message) - * @param PortNum current port number - * @param pIdentity Pointer on USBPD_DiscoveryIdentity_TypeDef structure - * @retval USBPD status : USBPD_ACK or USBPD_BUSY - */ - USBPD_StatusTypeDef (*USBPD_VDM_DiscoverIdentity)(uint8_t PortNum, USBPD_DiscoveryIdentity_TypeDef *pIdentity); - - /** - * @brief VDM Discover SVID callback (retrieve SVID supported by device for answer to Discovery mode) - * @param PortNum current port number - * @param p_SVID_Info Pointer on USBPD_SVIDInfo_TypeDef structure - * @retval USBPD status USBPD_BUSY or USBPD_ACK or USBPD_NAK - */ - USBPD_StatusTypeDef (*USBPD_VDM_DiscoverSVIDs)(uint8_t PortNum, uint16_t **p_SVID_Data, uint8_t *nbSVID); - - /** - * @brief VDM Discover Mode callback (report all the modes supported by SVID) - * @param PortNum current port number - * @param SVID SVID ID - * @param p_ModeTab Pointer on the mode value - * @param NumberOfMode Number of mode available - * @retval USBPD status - */ - USBPD_StatusTypeDef (*USBPD_VDM_DiscoverModes)(uint8_t PortNum, uint16_t SVID, uint32_t **p_ModeTab, uint8_t *NumberOfMode); - - /** - * @brief VDM Mode enter callback - * @param PortNum current port number - * @param SVID SVID ID - * @param ModeIndex Index of the mode to be entered - * @retval USBPD status USBPD_ACK/USBPD_NAK - */ - USBPD_StatusTypeDef (*USBPD_VDM_ModeEnter)(uint8_t PortNum, uint16_t SVID, uint32_t ModeIndex); - - /** - * @brief VDM Mode exit callback - * @param PortNum current port number - * @param SVID SVID ID - * @param ModeIndex Index of the mode to be exited - * @retval USBPD status USBPD_ACK/USBPD_NAK - */ - USBPD_StatusTypeDef (*USBPD_VDM_ModeExit)(uint8_t PortNum, uint16_t SVID, uint32_t ModeIndex); - - /** - * @brief Inform identity callback (Identity information received in Discovery identity answer) - * @param PortNum current port number - * @param SOPType SOP type - * @param CommandStatus Command status based on @ref USBPD_VDM_CommandType_Typedef - * @param pIdentity Pointer on the discovery identity information based on @ref USBPD_DiscoveryIdentity_TypeDef - * @retval USBPD status - */ - void (*USBPD_VDM_InformIdentity)(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, USBPD_DiscoveryIdentity_TypeDef *pIdentity); - - /** - * @brief Inform SVID callback - * @param PortNum current port number - * @param SOPType SOP type - * @param CommandStatus Command status based on @ref USBPD_VDM_CommandType_Typedef - * @param pListSVID Pointer of list of SVID based on @ref USBPD_SVIDInfo_TypeDef - * @retval USBPD status - */ - void (*USBPD_VDM_InformSVID)(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, USBPD_SVIDInfo_TypeDef *pListSVID); - - /** - * @brief Inform Mode callback - * @param PortNum current port number - * @param SOPType SOP type - * @param CommandStatus Command status based on @ref USBPD_VDM_CommandType_Typedef - * @param pModesInfo Pointer of Modes info based on @ref USBPD_ModeInfo_TypeDef - * @retval None - */ - void (*USBPD_VDM_InformMode)(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, USBPD_ModeInfo_TypeDef *pModesInfo); - - /** - * @brief Inform Mode enter callback - * @param PortNum current port number - * @param SOPType SOP type - * @param CommandStatus Command status based on @ref USBPD_VDM_CommandType_Typedef - * @param SVID SVID ID - * @param ModeIndex Index of the mode to be entered - * @retval None - */ - void (*USBPD_VDM_InformModeEnter)(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, uint16_t SVID, uint32_t ModeIndex); - - /** - * @brief Inform Mode exit callback - * @param PortNum current port number - * @param SOPType SOP type - * @param CommandStatus Command status based on @ref USBPD_VDM_CommandType_Typedef - * @param SVID SVID ID - * @param ModeIndex Index of the mode to be exited - * @retval None - */ - void (*USBPD_VDM_InformModeExit)(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, uint16_t SVID, uint32_t ModeIndex); - - /** - * @brief Send VDM Attention message callback - * @param PortNum current port number - * @param pNbData Pointer of number of VDO to send - * @param pVDO Pointer of VDO to send - * @retval None - */ - void (*USBPD_VDM_SendAttention)(uint8_t PortNum, uint8_t *pNbData, uint32_t *pVDO); - - /** - * @brief Receive VDM Attention callback - * @param PortNum current port number - * @param NbData Number of received VDO - * @param VDO Received VDO - * @retval None - */ - void (*USBPD_VDM_ReceiveAttention)(uint8_t PortNum, uint8_t NbData, uint32_t VDO); - - /** - * @brief VDM Send Specific message callback - * @param PortNum current port number - * @param VDMCommand VDM command based on @ref USBPD_VDM_Command_Typedef - * @param pNbData Pointer of number of VDO to send - * @param pVDO Pointer of VDO to send - * @retval None - */ - void (*USBPD_VDM_SendSpecific)(uint8_t PortNum, USBPD_VDM_Command_Typedef VDMCommand, uint8_t *pNbData, uint32_t *pVDO); - - /** - * @brief VDM Receive Specific message callback - * @param PortNum Current port number - * @param VDMCommand VDM command based on @ref USBPD_VDM_Command_Typedef - * @param pNbData Pointer of number of received VDO and used for the answer - * @param pVDO Pointer of received VDO and use for the answer - * @retval status - */ - USBPD_StatusTypeDef (*USBPD_VDM_ReceiveSpecific)(uint8_t PortNum, USBPD_VDM_Command_Typedef VDMCommand, uint8_t *pNbData, uint32_t *pVDO); - - /** - * @brief VDM Specific message callback to inform user of reception of VDM specific message - * @param PortNum current port number - * @param VDMCommand VDM command based on @ref USBPD_VDM_Command_Typedef - * @param pNbData Pointer of number of received VDO - * @param pVDO Pointer of received VDO - * @retval None - */ - void (*USBPD_VDM_InformSpecific)(uint8_t PortNum, USBPD_VDM_Command_Typedef VDMCommand, uint8_t *pNbData, uint32_t *pVDO); -#endif /* USBPDCORE_SVDM || defined(USBPDCORE_CABLE)*/ - -#if defined(USBPDCORE_UVDM) - /** - * @brief VDM Send Unstructured message callback - * @param PortNum current port number - * @param pUVDM_Header Pointer on UVDM header based on @ref USBPD_UVDMHeader_TypeDef - * @param pNbData Pointer of number of VDO to send - * @param pVDO Pointer of VDO to send - * @retval None - */ - void (*USBPD_VDM_SendUVDM)(uint8_t PortNum, USBPD_UVDMHeader_TypeDef *pUVDM_Header, uint8_t *pNbData, uint32_t *pVDO); - - /** - * @brief Unstructured VDM message callback to inform user of reception of UVDM message - * @param PortNum current port number - * @param UVDM_Header UVDM header based on @ref USBPD_UVDMHeader_TypeDef - * @param pNbData Pointer of number of received VDO - * @param pVDO Pointer of received VDO - * @retval status - */ - USBPD_StatusTypeDef (*USBPD_VDM_ReceiveUVDM)(uint8_t PortNum, USBPD_UVDMHeader_TypeDef UVDM_Header, uint8_t *pNbData, uint32_t *pVDO); -#endif /* USBPDCORE_UVDM */ -}USBPD_VDM_Callbacks; - -/** - * @} - */ - -#endif /* USBPDCORE_SVDM || USBPDCORE_UVDM || USBPDCORE_CABLE */ - -/** @defgroup USBPD_CORE_PE_Exported_TypesDefinitions USBPD CORE PE Exported Types Definitions - * @{ - */ - -/** @defgroup PE_CallBacks_structure_definition PE CallBacks structure definition - * @brief PE CallBacks exposed by the PE to the DMP - * @{ - */ -typedef struct -{ - /** - * @brief Request the DPM to setup the new power level. - * @param PortNum Port number - * @retval USBPD_ACCEPT, USBPD_REJECT, USBPD_WAIT - */ - USBPD_StatusTypeDef (*USBPD_PE_RequestSetupNewPower)(uint8_t PortNum); - - /** - * @brief Inform the DPM to HardReset status. - * @param PortNum Port number - * @param Role of the board - * @param Status HR Status update - * @retval None - */ - void (*USBPD_PE_HardReset)(uint8_t PortNum, USBPD_PortPowerRole_TypeDef CurrentRole, USBPD_HR_Status_TypeDef Status); - - /** - * @brief Get evaluation of swap request from DPM. - * @param PortNum Port number - * @retval USBPD_ACCEPT, USBPD_WAIT, USBPD_REJECT - */ - USBPD_StatusTypeDef (*USBPD_PE_EvaluatPRSwap)(uint8_t PortNum); - - /** - * @brief Callback to be used by PE to notify a generic event, clear for the specific DPM - * @param PortNum Port number - * @param EventVal @ref USBPD_NotifyEventValue_TypeDef - * @retval none - */ - void (*USBPD_PE_Notify)(uint8_t PortNum, USBPD_NotifyEventValue_TypeDef EventVal); - - /** - * @brief Inform DPM that an extended message has been received. - * @param PortNum port number value - * @param MsgId extended message id - * @param ptrData : pointer on the data - * @param DataSize : size of the data - * @retval None - */ - void (*USBPD_PE_ExtendedMessage)(uint8_t PortNum, USBPD_ExtendedMsg_TypeDef MsgId, uint8_t *ptrData, uint16_t DataSize); - - /** - * @brief Allow PE to retrieve information from DPM/PWR_IF. - * @param PortNum Port number - * @param DataId Type of data to be read from DPM based on @ref USBPD_CORE_DataInfoType_TypeDef - * @param Ptr Pointer on address where DPM data should be written (u8 pointer) - * @param Size Pointer on nb of bytes written by DPM - * @retval None - */ - void (*USBPD_PE_GetDataInfo)(uint8_t PortNum, USBPD_CORE_DataInfoType_TypeDef DataId , uint8_t *Ptr, uint32_t *Size); - - /** - * @brief Allow PE to update information in DPM/PWR_IF. - * @param PortNum Port number - * @param DataId Type of data to be read from DPM based on @ref USBPD_CORE_DataInfoType_TypeDef - * @param Ptr Pointer on address where DPM data to be updated could be read (u8 pointer) - * @param Size Nb of byte to be updated in DPM - * @retval None - */ - void (*USBPD_PE_SetDataInfo)(uint8_t PortNum, USBPD_CORE_DataInfoType_TypeDef DataId , uint8_t *Ptr, uint32_t Size); - - /** - * @brief Callback to be used by PE to evaluate a Request from Sink - * @param PortNum Port number - * @param PtrPowerObject Pointer on the power data object - * @retval USBPD_ACCEPT, USBPD_REJECT, USBPD_WAIT, USBPD_GOTOMIN - */ - USBPD_StatusTypeDef (*USBPD_PE_SRC_EvaluateRequest)(uint8_t PortNum, USBPD_CORE_PDO_Type_TypeDef *PtrPowerObject); - - /** - * @brief Callback to be used by PE to evaluate a Source Capabilities from Source - * @param PortNum Port number - * @param PtrRequestData Pointer on selected request data object - * @param PtrPowerObject Pointer on the power data object - * @retval None - */ - void (*USBPD_PE_SNK_EvaluateCapabilities)(uint8_t PortNum, uint32_t *RequestData, USBPD_CORE_PDO_Type_TypeDef *PtrPowerObject); - - /** - * @brief Callback to be used during power role swap - * @param PortNum Port number - * @param Role of the board - * @param Status HR Status update - * @retval None - */ - void (*USBPD_PE_PowerRoleSwap)(uint8_t PortNum, USBPD_PortPowerRole_TypeDef CurrentRole, USBPD_PRS_Status_TypeDef Status); - - /** - * @brief Callback to be used by PE to wakeup the state machine - * @param PortNum Port number - * @retval None - */ - void (*USBPD_PE_WakeupCallback)(uint8_t PortNum); - - /** - * @brief Callback to be used by PE to evaluate a Vconn swap - * @param PortNum Port number - * @retval USBPD_ACCEPT, USBPD_REJECT, USBPD_WAIT - */ - USBPD_StatusTypeDef (*USBPD_PE_EvaluateVconnSwap)(uint8_t PortNum); - - /** - * @brief Callback to be used by PE to manage VConn - * @param PortNum Port number - * @param State Enable or Disable VConn on CC lines - * @retval USBPD_ACCEPT, USBPD_REJECT - */ - USBPD_StatusTypeDef (*USBPD_PE_VconnPwr)(uint8_t PortNum, USBPD_FunctionalState State); - - /** - * @brief Callback to be used by PE to manage VConn - * @param PortNum Port number - * @retval None - */ - void (*USBPD_PE_EnterErrorRecovery)(uint8_t PortNum); - - /** - * @brief Callback to be used by PE to know application status about DataRoleSwap - * @param PortNum Port number - * @retval USBPD_REJECT, USBPD_ACCEPT - */ - USBPD_StatusTypeDef (*USBPD_PE_DataRoleSwap)(uint8_t PortNum); - - /** - * @brief Callback to be used by PE to check is VBUS is ready or present - * @param PortNum Port number - * @param Vsafe Vsafe status based on @ref USBPD_VSAFE_StatusTypeDef - * @retval USBPD_DISABLE or USBPD_ENABLE - */ - USBPD_FunctionalState (*USBPD_PE_IsPowerReady)(uint8_t PortNum, USBPD_VSAFE_StatusTypeDef Vsafe); - -}USBPD_PE_Callbacks; - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup USBPD_CORE_PE_Exported_Functions USBPD CORE PE Exported Functions - * @{ - */ - -/** @defgroup USBPD_CORE_PE_Exported_Functions_Group1 USBPD CORE PE Exported Functions to DPM CORE - * @{ - */ -/** - * @brief Initialize Policy Engine layer for a Port with a specified role - * @param PortNum Index of current used port - * @param pSettings Pointer on @ref USBPD_SettingsTypeDef structure - * @param pParams Pointer on @ref USBPD_ParamsTypeDef structure - * @param PECallbacks Callback function to be passed to PRL layer - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_PE_Init(uint8_t PortNum, USBPD_SettingsTypeDef *pSettings, USBPD_ParamsTypeDef *pParams, const USBPD_PE_Callbacks *PECallbacks); - -/** - * @brief Check coherence between lib slected and the lib include inside the project - * @param LibId Value fix defined with the switch lib. - * @retval USBPD_TRUE or USBPD_FALSE - */ -uint32_t USBPD_PE_CheckLIB(uint32_t LibId); - -/** - * @brief Return the need of the stack in terms of dynamique allocation - * @note This value correspond to worst case 2 port os if application manage - * only one port divide the value by 2 - * @retval Memory size - */ -uint32_t USBPD_PE_GetMemoryConsumption(void); - -/** - * @brief Set the trace pointer - * @param Ptr function on trace - * @param Debug Trace debug level - * @retval None - */ -void USBPD_PE_SetTrace(TRACE_ENTRY_POINT Ptr, uint8_t Debug); - -#if defined(USBPDCORE_SRC) || defined(USBPDCORE_DRP) -/** - * @brief Policy Engine Source port main state machine - * @param PortNum Index of current used port - * @retval Timing in ms - */ -uint32_t USBPD_PE_StateMachine_SRC(uint8_t PortNum); -#endif /* USBPDCORE_SRC || USBPDCORE_DRP */ - -#if defined(USBPDCORE_SNK) || defined(USBPDCORE_DRP) -/** - * @brief Policy Engine Sink port main state machine - * @param PortNum Index of current used port - * @retval Timing in ms - */ -uint32_t USBPD_PE_StateMachine_SNK(uint8_t PortNum); -#endif /* USBPDCORE_SNK || USBPDCORE_DRP */ - -#ifdef USBPDCORE_DRP -/** - * @brief Policy Engine dual role port main state machine - * @param PortNum Index of current used port - * @retval Timing in ms - */ -uint32_t USBPD_PE_StateMachine_DRP(uint8_t PortNum); -#endif /* USBPDCORE_DRP */ - -/** - * @brief Function called by DPM to set the cable status connected or disconnected. - * @param PortNum Index of current used port - * @param IsConnected Cable connection status: 1 if connected and 0 is disconnected - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_PE_IsCableConnected(uint8_t PortNum, uint8_t IsConnected); - -/** - * @brief Increment PE Timers tick - * @param PortNum Index of current used port - * @retval None - */ -void USBPD_PE_TimerCounter(uint8_t PortNum); - -/** - * @} - */ - -#if defined(USBPDCORE_SVDM) || defined(USBPDCORE_UVDM) || defined(USBPDCORE_CABLE) -/** @defgroup USBPD_CORE_PE_Exported_Functions_Group2 USBPD CORE PE Exported Functions to VDM USER - * @{ - */ -/** - * @brief Initialize VDM callback functions in PE - * @param PortNum Index of current used port - * @param VDMCallbacks Pointer on VDM callbacks based on @ref USBPD_VDM_Callbacks - * @retval None - */ -void USBPD_PE_InitVDM_Callback(uint8_t PortNum, USBPD_VDM_Callbacks *VDMCallbacks); -/** - * @} - */ -#endif /* USBPDCORE_SVDM || USBPDCORE_UVDM || USBPDCORE_CABLE*/ - -/** @defgroup USBPD_CORE_PE_Exported_Functions_Group3 USBPD CORE PE Exported Functions to DPM USER - * @{ - */ - -/** - * @brief Generic function to send a control message - * @param PortNum Index of current used port - * @param CtrlMsg Control message id - * @param SOPType SOP Type based on @ref USBPD_SOPType_TypeDef - * @retval USBPD status USBPD_BUSY, USBPD_ERROR, USBPD_FAIL - */ -USBPD_StatusTypeDef USBPD_PE_Request_CtrlMessage(uint8_t PortNum, USBPD_ControlMsg_TypeDef CtrlMsg, USBPD_SOPType_TypeDef SOPType); - -/** - * @brief Generic function to send a data message - * @param PortNum Index of current used port - * @param DataMsg Data message id based on @ref USBPD_DataMsg_TypeDef - * @param pData Pointer of PDO to send - * @retval USBPD status USBPD_BUSY, USBPD_ERROR, USBPD_FAIL - */ -USBPD_StatusTypeDef USBPD_PE_Request_DataMessage(uint8_t PortNum, USBPD_DataMsg_TypeDef DataMsg, uint32_t *pData); - -/** - * @brief Called by DPM to request PE to perform a Hard Reset. - * @param PortNum Index of current used port - * @retval USBPD status USBPD_OK USBPD_BUSY USBPD_FAIL, USBPD_NOTSUPPORTED - */ -USBPD_StatusTypeDef USBPD_PE_Request_HardReset(uint8_t PortNum); - -#if defined(USBPDCORE_SNK) || defined(USBPDCORE_DRP) -/** - * @brief Evaluate received Capabilities Message from Source port and prepare the request message - * @param PortNum Index of current used port - * @param Rdo Requested data object - * @param PWobject Power Object - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_PE_Send_Request(uint8_t PortNum, uint32_t Rdo, USBPD_CORE_PDO_Type_TypeDef PWobject); -#endif /* USBPDCORE_SNK || USBPDCORE_DRP */ - -#ifdef USBPDCORE_SVDM -/** - * @brief Called by DPM to request the PE to perform a VDM identity request. - * @note On PD2.0, SVDM Identity cannot be sent by UFP. - * @param PortNum Index of current used port - * @param SOPType SOP Type (Only SOP or SOP') - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_PE_SVDM_RequestIdentity(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType); - -/** - * @brief Called by DPM to request the PE to perform a VDM SVID request. - * @param PortNum Index of current used port - * @param SOPType SOP Type (only valid for SOP or SOP') - * @retval USBPD status : USBPD_BUSY, USBPD_OK, USBPD_FAIL - */ -USBPD_StatusTypeDef USBPD_PE_SVDM_RequestSVID(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType); - -/** - * @brief Called by DPM to request the PE to perform a VDM Discovery mode message on one SVID. - * @param PortNum Index of current used port - * @param SOPType SOP Type - * @param SVID SVID used for discovery mode message - * @retval USBPD status : USBPD_BUSY, USBPD_OK, USBPD_FAIL - */ -USBPD_StatusTypeDef USBPD_PE_SVDM_RequestMode(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, uint16_t SVID); - -/** - * @brief Called by DPM to request the PE to perform a VDM Discovery mode message on one SVID. - * @param PortNum Index of current used port - * @param SOPType SOP Type - * @param SVID SVID used for discovery mode message - * @param ModeIndex Index of the mode to be entered - * @retval USBPD status : USBPD_BUSY, USBPD_OK, USBPD_FAIL - */ -USBPD_StatusTypeDef USBPD_PE_SVDM_RequestModeEnter(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, uint16_t SVID, uint8_t ModeIndex); - -/** - * @brief Called by DPM to request the PE to perform a VDM mode exit. - * @param PortNum Index of current used port - * @param SOPType SOP Type - * @param SVID SVID used for discovery mode message - * @param ModeIndex Index of the mode to be exit - * @retval USBPD status : USBPD_BUSY, USBPD_OK, USBPD_FAIL - */ -USBPD_StatusTypeDef USBPD_PE_SVDM_RequestModeExit(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, uint16_t SVID, uint8_t ModeIndex); - -/** - * @brief Called by DPM to request the PE to perform a VDM Attention. - * @param PortNum Index of current used port - * @param SOPType Received message type based on @ref USBPD_SOPType_TypeDef - * @param SVID Used SVID - * @retval USBPD status : USBPD_BUSY, USBPD_OK, USBPD_FAIL - */ -USBPD_StatusTypeDef USBPD_PE_SVDM_RequestAttention(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, uint16_t SVID); - -/** - * @brief Called by DPM to request the PE to send a specific SVDM message. - * @param PortNum Index of current used port - * @param SOPType Received message type based on @ref USBPD_SOPType_TypeDef - * @param Command VDM command based on @ref USBPD_VDM_Command_Typedef - * @param SVID Used SVID - * @retval USBPD status : USBPD_BUSY, USBPD_OK, USBPD_FAIL - */ -USBPD_StatusTypeDef USBPD_PE_SVDM_RequestSpecific(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_Command_Typedef Command, uint16_t SVID); -#endif /* USBPDCORE_SVDM */ - -#if defined(USBPDCORE_UVDM) -/** - * @brief Called by DPM to request the PE to send a UVDM message. - * @param PortNum Index of current used port - * @param SOPType Received message type based on @ref USBPD_SOPType_TypeDef - * @retval USBPD status : USBPD_BUSY, USBPD_OK, USBPD_FAIL - */ -USBPD_StatusTypeDef USBPD_PE_UVDM_RequestMessage(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType); -#endif /* USBPDCORE_UVDM */ - -#if defined(USBPD_REV30_SUPPORT) -/** - * @brief Send an chunked extended message and store data received inside a buffer - * @param PortNum Port number value - * @param SOPType Message type based on @ref USBPD_SOPType_TypeDef - * @param MessageType Extended Msg type @ref USBPD_ExtendedMsg_TypeDef - * @param Ptrdata Data pointer to PRL layer - * @param DataSize Size of the data - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_PE_SendExtendedMessage(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_ExtendedMsg_TypeDef MessageType, uint8_t *Ptrdata, uint16_t DataSize); - -#if defined(USBPDCORE_FASTROLESWAP) -/** - * @brief Execute an FRS signalling. - * @param PortNum - * @retval Timing in ms. - */ -void USBPD_PE_ExecFastRoleSwapSignalling(uint8_t PortNum); -#endif -#endif /* USBPD_REV30_SUPPORT */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup USBPD_CORE_PRL - * @{ - */ - -/** @defgroup USBPD_CORE_PRL_Exported_Functions USBPD CORE PRL Exported Functions - * @{ - */ - -/** @defgroup USBPD_CORE_PRL_Exported_Functions_Group1 USBPD CORE PRL Interface function for timer - * @{ - */ - -/** - * @brief Decrement The PRL Timers values - * @param PortNum port number value - * @retval None - */ -void USBPD_PRL_TimerCounter(uint8_t PortNum); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#if defined(USBPDCORE_TCPM_SUPPORT) -/** @addtogroup USBPD_CORE_TCPM - * @{ - */ - -/** @defgroup USBPD_CORE_TCPM_Exported_Functions USBPD CORE TCPM Exported Functions - * @{ - */ - -/** @defgroup USBPD_CORE_TCPM_Exported_Functions_Grp1 USBPD CORE TCPM Exported Functions to applications (DPM and PWR_IF) - * @{ - */ - -/** - * @brief Initialize TCPC devices - * @param PortNum Port number value - * @param TCPC_ToggleRole Indication if TCPC should perform a role toggle or not - * @param Params Pointer on PE parameters based on @ref USBPD_ParamsTypeDef - * @param CallbackFunctions Pointer on CAD callbacks - * @param TCPC_Driver Pointer on TCPC drivers based on @ref TCPC_DrvTypeDef - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_TCPM_HWInit(uint8_t PortNum, uint8_t TCPC_ToggleRole, USBPD_ParamsTypeDef *Params, USBPD_CAD_Callbacks *CallbackFunctions, TCPC_DrvTypeDef * TCPC_Driver); - -/** - * @brief Set CC line for PD connection - * @param PortNum Port number value - * @param Pull Power role can be one of the following values: - * @arg @ref TYPEC_CC_RA - * @arg @ref TYPEC_CC_RP - * @arg @ref TYPEC_CC_RD - * @arg @ref TYPEC_CC_OPEN - * @param State Activation or deactivation of connection - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_TCPM_set_cc(uint32_t PortNum, TCPC_CC_Pull_TypeDef Pull, USBPD_FunctionalState State); - -/** - * @brief Enable or disable VCONN - * @param PortNum Port number value - * @param State Activation or deactivation of VCONN - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_TCPM_set_vconn(uint32_t PortNum, USBPD_FunctionalState State); - -/** - * @brief Enable VBUS - * @param PortNum The port handle. - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_TCPM_VBUS_Enable(uint32_t PortNum); - -/** - * @brief Disable VBUS - * @param PortNum The port handle. - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_TCPM_VBUS_Disable(uint32_t PortNum); - -/** - * @brief Get VBUS voltage - * @param PortNum The port handle. - * @retval VBUS value in mV - */ -uint16_t USBPD_TCPM_VBUS_GetVoltage(uint32_t PortNum); - -/** - * @brief Retrieve the VBUS VSafe0 status for a specified port. - * @param PortNum The port handle. - * @retval USBPD_StatusTypeDef - */ -USBPD_StatusTypeDef USBPD_TCPM_VBUS_IsVsafe0V(uint32_t PortNum); - -/** - * @brief Retrieve the VBUS Vsafe5V status for a specified port. - * @param PortNum The port handle. - * @retval USBPD_StatusTypeDef - */ -USBPD_StatusTypeDef USBPD_TCPM_VBUS_IsVsafe5V(uint32_t PortNum); - -/** - * @brief Management of ALERT - * @param Event Event reported by application - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_TCPM_alert(uint32_t Event); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* USBPDCORE_TCPM_SUPPORT */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBPD_CORE_H_ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_def.h b/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_def.h deleted file mode 100644 index 506dcb3..0000000 --- a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_def.h +++ /dev/null @@ -1,2808 +0,0 @@ -/** - ****************************************************************************** - * @file usbpd_def.h - * @author MCD Application Team - * @brief Global defines for USB-PD libarary - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -#ifndef __USBPD_DEF_H_ -#define __USBPD_DEF_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#if defined ( __CC_ARM ) -#define __ASM __asm /*!< asm keyword for ARM Compiler */ -#define __INLINE __inline /*!< inline keyword for ARM Compiler */ -#define __STATIC_INLINE static __inline -#define __PACKEDSTRUCTBEGIN __packed struct -#define __PACKEDSTRUCTEND -#elif defined ( __ICCARM__ ) -#define __ASM __asm /*!< asm keyword for IAR Compiler */ -#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ -#define __STATIC_INLINE static inline -#define __PACKEDSTRUCTBEGIN __packed struct -#define __PACKEDSTRUCTEND -#elif defined ( __GNUC__ ) -#define __ASM __asm /*!< asm keyword for GNU Compiler */ -#define __INLINE inline /*!< inline keyword for GNU Compiler */ -#define __STATIC_INLINE static inline -#ifndef __packed -#define __packed __attribute__((__packed__)) -#endif /* __packed */ -#define __PACKEDSTRUCTBEGIN struct -#define __PACKEDSTRUCTEND __packed -#endif - -#include -#include - -/** @addtogroup STM32_USBPD_LIBRARY - * @{ - */ - -/** @addtogroup USBPD_CORE - * @{ - */ - -/** @addtogroup USBPD_CORE_DEF - * @{ - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup USBPD_CORE_DEF_Exported_Macros USBPD CORE DEF Exported Macros - * @{ - */ -/** - * @brief Compare two variables and return the smallest - * @param __VAR1__ First variable to be compared - * @param __VAR2__ Second variable to be compared - * @retval Returns the smallest variable - */ -#define USBPD_MIN(__VAR1__, __VAR2__) (((__VAR1__) > (__VAR2__))?(__VAR2__):(__VAR1__)) - -/** - * @brief Compare two variables and return the biggest - * @param __VAR1__ First variable to be compared - * @param __VAR2__ Second variable to be compared - * @retval Returns the biggest variable - */ -#define USBPD_MAX(__VAR1__, __VAR2__) (((__VAR1__) < (__VAR2__))?(__VAR2__):(__VAR1__)) - -/** - * @brief Check if the requested voltage is valid - * @param __MV__ Requested voltage in mV units - * @param __MAXMV__ Max Requested voltage in mV units - * @param __MINMV__ Min Requested voltage in mV units - * @retval 1 if valid voltage else 0 - */ -#define USBPD_IS_VALID_VOLTAGE(__MV__, __MAXMV__, __MINMV__) ((((__MV__) <= (__MAXMV__)) && ((__MV__) >= (__MINMV__)))? 1u: 0u) - -#define DIV_ROUND_UP(x, y) (((x) + ((y) - 1u)) / (y)) -#define MV2ADC(__X__) ( (__X__*4095) / 3300 ) -#define ADC2MV(__X__) ( (__X__*3300) / 4095 ) - -/* Macros for integer division with various rounding variants default integer - division rounds down. */ -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) -#define MAX(a, b) (((a) > (b)) ? (a) : (b)) - -#define USPBPD_WRITE32(addr,data) do { \ - uint8_t bindex; \ - for(bindex = 0u; bindex < 4u; bindex++) \ - { \ - ((uint8_t *)addr)[bindex] = ((uint8_t)(data >> (8u * bindex)) & 0x000000FFu); \ - } \ - } while(0u); - -#define LE16(addr) (((uint16_t)(*((uint8_t *)(addr))))\ - + (((uint16_t)(*(((uint8_t *)(addr)) + 1u))) << 8u)) - -#define LE32(addr) ((((uint32_t)(*(((uint8_t *)(addr)) + 0u))) + \ - (((uint32_t)(*(((uint8_t *)(addr)) + 1u))) << 8u) + \ - (((uint32_t)(*(((uint8_t *)(addr)) + 2u))) << 16u) + \ - (((uint32_t)(*(((uint8_t *)(addr)) + 3u))) << 24))) - -/** - * @} - */ - -/* Exported defines --------------------------------------------------------*/ -/** @defgroup USBPD_CORE_DEF_Exported_Defines USBPD CORE DEF Exported Defines - * @{ - */ -#define USBPD_TRUE 1u -#define USBPD_FALSE 0u - -#define __DEBUG_PESTATEMACHINE - -/** @defgroup USBPD_CORE_DEF_Exported_Defines_Swiches USBPD Compilations switches - * @brief List of compilation switches which can be used to reduce size of the CORE library - * @{ - */ - -/* Default Switch */ -#define USBPDCORE_GOTOMIN -#define USBPDCORE_BIST -#define USBPDCORE_GETSNKCAP -#define USBPDCORE_GETSRCCAP -#define USBPDCORE_GIVESNKCAP - -#if defined(USBPDCORE_LIB_PD3_FULL) || defined(USBPDCORE_LIB_PD3_CONFIG_1) || defined(USBPD_TCPM_LIB_PD3_FULL) || defined(USBPD_TCPM_LIB_PD3_CONFIG_1) -/* - USBPDCORE_LIB_PD3_FULL - USBPDCORE_LIB_PD3_CONFIG_1 : NO VDM - USBPD_TCPM_LIB_PD3_FULL : PD3.0 TCPM FULL - USBPD_TCPM_LIB_PD3_CONFIG_1 : PD3.0 TCPM FULL without VDM -*/ -#define USBPDCORE_SRC -#define USBPDCORE_SNK -#define USBPDCORE_DRP -#define USBPDCORE_SNK_CAPA_EXT - -#if defined(USBPDCORE_LIB_PD3_FULL) || defined(USBPD_TCPM_LIB_PD3_FULL) -#define USBPDCORE_SVDM -#endif /* USBPDCORE_LIB_PD3_FULL || USBPD_TCPM_LIB_PD3_FULL */ - -#define USBPDCORE_UVDM -#define USBPD_REV30_SUPPORT -#define USBPDCORE_CABLE -#define USBPDCORE_FASTROLESWAP -#define USBPDCORE_PPS -#define USBPDCORE_ALERT -#define USBPDCORE_SRC_CAPA_EXT -#define USBPDCORE_STATUS -#define USBPDCORE_BATTERY -#define USBPDCORE_MANU_INFO -#define USBPDCORE_SECURITY_MSG -#define USBPDCORE_FWUPD -#define USBPDCORE_COUNTRY_MSG -#define USBPDCORE_VCONN_SUPPORT -#define USBPDCORE_DATA_SWAP -#define USBPDCORE_ERROR_RECOVERY -#define USBPDCORE_UNCHUNCKED_MODE -#define USBPDCORE_PING_SUPPORT - -#if defined(USBPD_TCPM_LIB_PD3_FULL) || defined(USBPD_TCPM_LIB_PD3_CONFIG_1) -#define USBPDCORE_TCPM_SUPPORT -#endif /* TCPM */ - -#endif /* PD3.0 */ - -/* List of compilation switches which can be used to reduce size of the CORE librairy */ -#if defined(USBPDCORE_LIB_PD2_FULL) || defined(USBPDCORE_LIB_PD2_CONFIG_1) || defined(USBPDCORE_LIB_PD2_CONFIG_MINSRC) || defined(USBPDCORE_LIB_PD2_CONFIG_MINSNK) || defined(USBPD_TCPM_LIB_PD2_FULL) || defined(USBPD_TCPM_LIB_PD2_CONFIG_1) || defined(USBPD_TCPM_LIB_PD2_MINSRC) || defined(USBPD_TCPM_LIB_PD2_MINSNK) -/* - USBPDCORE_LIB_PD2_FULL - USBPDCORE_LIB_PD2_CONFIG_1 : NO VDM - USBPDCORE_LIB_PD2_CONFIG_MINSRC : ONLY SRC and NO option - USBPDCORE_LIB_PD2_CONFIG_MINSNK : ONLY SNK, and NO option - USBPD_TCPM_LIB_PD2_FULL : PD2.0 TCPM FULL - USBPD_TCPM_LIB_PD2_CONFIG_1 : PD2.0 TCPM FULL without VDM - USBPD_TCPM_LIB_PD2_MINSRC : PD2.0 TCPM Only SRC - USBPD_TCPM_LIB_PD2_MINSNK : PD2.0 TCPM Only SNK -*/ -#define USBPD_REV20_SUPPORT - -#if !defined(USBPDCORE_LIB_PD2_CONFIG_MINSNK) && !defined(USBPD_TCPM_LIB_PD2_MINSNK) -#define USBPDCORE_SRC -#endif - -#if !defined(USBPDCORE_LIB_PD2_CONFIG_MINSRC) && !defined(USBPD_TCPM_LIB_PD2_MINSRC) -#define USBPDCORE_SNK -#endif - -#if defined(USBPDCORE_LIB_PD2_CONFIG_MINSRC) || defined(USBPDCORE_LIB_PD2_CONFIG_MINSNK) || defined(USBPD_TCPM_LIB_PD2_MINSRC) || defined(USBPD_TCPM_LIB_PD2_MINSNK) -#else -#define USBPDCORE_DRP -#define USBPDCORE_VCONN_SUPPORT -#define USBPDCORE_DATA_SWAP -#define USBPDCORE_CABLE -#define USBPDCORE_ERROR_RECOVERY -#define USBPDCORE_UVDM -#endif - -#if defined(USBPDCORE_LIB_PD2_FULL) || defined(USBPD_TCPM_LIB_PD2_FULL) -#define USBPDCORE_SVDM -#endif /* USBPDCORE_LIB_PD3_FULL || USBPD_TCPM_LIB_PD2_FULL */ - -#if defined(USBPD_TCPM_LIB_PD2_FULL) || defined(USBPD_TCPM_LIB_PD2_CONFIG_1) || defined(USBPD_TCPM_LIB_PD2_MINSRC) || defined(USBPD_TCPM_LIB_PD2_MINSNK) -#define USBPDCORE_TCPM_SUPPORT -#endif /* TCPM */ - -#endif /* PD2.0 */ - -#if defined(USBPDCORE_LIB_PD3_CONFIG_2) -#undef USBPDCORE_GOTOMIN -#undef USBPDCORE_BIST -#undef USBPDCORE_GETSNKCAP -#undef USBPDCORE_GETSRCCAP -#undef USBPDCORE_GIVESNKCAP -#undef USBPDCORE_SNK_CAPA_EXT - -#define USBPDCORE_SNK -#define USBPD_REV30_SUPPORT -#define USBPDCORE_FWUPD -#define USBPDCORE_UVDM -#define USBPDCORE_UNCHUNCKED_MODE -#endif /* USBPDCORE_LIB_PD3_CONFIG_2 */ - -/* _LIB_ID definition */ -/* - _LIB_ID constructs like this: 0xXYVVVWWW - * X: 3 (PD3.0) or 2 (PD2.0) - * Y: 0 (CORE) or 1 (TCPM) - * VVV: Stack version (ex 200 for Stack 2.0.0) - * WWW: 0 (FULL VERSION) or config_x -*/ -/* Defines for PD revision */ -#define LIB_PD_VERSION_POS 28u -#define LIB_PD_VERSION_MSK (0xFu << LIB_PD_VERSION_POS) -#define LIB_PD2 (2u << LIB_PD_VERSION_POS) -#define LIB_PD3 (3u << LIB_PD_VERSION_POS) -/* Defines for CORE or TCPM */ -#define LIB_CORE_TCPM_POS 24u -#define LIB_CORE_TCPM_MSK (0xFu << LIB_CORE_TCPM_POS) -#define LIB_CORE (0u << LIB_CORE_TCPM_POS) -#define LIB_TCPM (1u << LIB_CORE_TCPM_POS) -/* Defines for STACK version */ -#define LIB_STACK_VER_POS 12u -#define LIB_STACK_VER_MSK (0xFFFu << LIB_STACK_VER_POS) -#define LIB_STACK_VER (0x250u << LIB_STACK_VER_POS) -/* Defines for configuration */ -#define LIB_CONFIG_MSK 0xFFFu -#define LIB_FULL 0x000u -#define LIB_CONFIG_1 0x001u -#define LIB_CONFIG_MINSRC 0x002u -#define LIB_CONFIG_MINSNK 0x004u -#define LIB_CONFIG_2 0x010u - -#ifdef USBPDCORE_LIB_PD3_FULL -#define _LIB_ID (LIB_PD3 | LIB_CORE | LIB_STACK_VER | LIB_FULL) -#endif -#ifdef USBPDCORE_LIB_PD3_CONFIG_1 -#define _LIB_ID (LIB_PD3 | LIB_CORE | LIB_STACK_VER | LIB_CONFIG_1) -#endif -#ifdef USBPDCORE_LIB_PD2_FULL -#define _LIB_ID (LIB_PD2 | LIB_CORE | LIB_STACK_VER | LIB_FULL) -#endif -#ifdef USBPDCORE_LIB_PD2_CONFIG_1 -#define _LIB_ID (LIB_PD2 | LIB_CORE | LIB_STACK_VER | LIB_CONFIG_1) -#endif -#ifdef USBPDCORE_LIB_PD2_CONFIG_MINSRC -#define _LIB_ID (LIB_PD2 | LIB_CORE | LIB_STACK_VER | LIB_CONFIG_MINSRC) -#endif -#ifdef USBPDCORE_LIB_PD2_CONFIG_MINSNK -#define _LIB_ID (LIB_PD2 | LIB_CORE | LIB_STACK_VER | LIB_CONFIG_MINSNK) -#endif -#ifdef USBPD_TCPM_LIB_PD2_FULL -#define _LIB_ID (LIB_PD2 | LIB_TCPM | LIB_STACK_VER | LIB_FULL) -#endif -#ifdef USBPD_TCPM_LIB_PD2_MINSRC -#define _LIB_ID (LIB_PD2 | LIB_TCPM | LIB_STACK_VER | LIB_CONFIG_MINSRC) -#endif -#ifdef USBPD_TCPM_LIB_PD2_MINSNK -#define _LIB_ID (LIB_PD2 | LIB_TCPM | LIB_STACK_VER | LIB_CONFIG_MINSNK) -#endif -#ifdef USBPD_TCPM_LIB_PD2_CONFIG_1 -#define _LIB_ID (LIB_PD2 | LIB_TCPM | LIB_STACK_VER | LIB_CONFIG_1) -#endif -#ifdef USBPD_TCPM_LIB_PD3_CONFIG_1 -#define _LIB_ID (LIB_PD3 | LIB_TCPM | LIB_STACK_VER | LIB_CONFIG_1) -#endif -#ifdef USBPD_TCPM_LIB_PD3_FULL -#define _LIB_ID (LIB_PD3 | LIB_TCPM | LIB_STACK_VER | LIB_FULL) -#endif -#if defined(USBPDCORE_LIB_PD3_CONFIG_2) -#define _LIB_ID (LIB_PD3 | LIB_TCPM | LIB_STACK_VER | LIB_CONFIG_2) -#endif -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -#define USBPD_PORT_0 (0U) /*!< Port 0 identifier */ -#define USBPD_PORT_1 (1U) /*!< Port 1 identifier */ - -#define USBPD_MAX_NB_PDO (7U) /*!< Maximum number of supported Power Data Objects: fix by the Specification */ -#define BIST_CARRIER_MODE_MS (50U) /*!< Time in ms of the BIST signal*/ - -/* - * Maximum size of a Power Delivery packet (in bits on the wire) : - * 16-bit header + 0..7 32-bit data objects (+ 4b5b encoding) - * 64-bit preamble + SOP (4x 5b) + header (16-bit) + message in 4b5b + 32-bit CRC + EOP (1x 5b) - * = 64bit + 4*5bit + 16bit * 5/4 + 7 * 32bit * 5/4 + 32bit * 5/4 + 5 - */ -#define PHY_BIT_LEN ((uint16_t)429u) -#define PHY_MAX_RAW_SIZE ((uint16_t)((PHY_BIT_LEN*2u) + 3u)) -#define PHY_MAX_RAW_BYTE_SIZE ((uint8_t)60u) /*! 70ns (>~7m) for P2.0 or 1000ns (~100m) for P3.0 */ -#if defined(USBPD_REV30_SUPPORT) - ,CABLE_LATENCY_2000NS = 9u, /*!< 2000ns (~200m) */ - CABLE_LATENCY_3000NS = 10u /*!< 3000ns (~300m) */ -#endif /* USBPD_REV30_SUPPORT */ -} USBPD_CableLatency; - -/** - * @} - */ - -/** - * @brief Cable maximun VBUS voltage - * @{ - */ -#define VBUS_MAX_20V 0u -#define VBUS_MAX_30V 1u -#define VBUS_MAX_40V 2u -#define VBUS_MAX_50V 3u - -typedef uint32_t USBPD_CableMaxVoltage; - -/** - * @} - */ - -/** - * @brief Cable Termination Type in Active/Passive cable - * @{ - */ -#define CABLE_TERM_BOTH_PASSIVE_NO_VCONN 0u /*!< VCONN not required (PD2.0 only) */ -#define CABLE_TERM_BOTH_PASSIVE_VCONN 1u /*!< VCONN required (PD2.0 only) */ -#if defined(USBPD_REV30_SUPPORT) -#define CABLE_TERM_ONE_EACH_VCONN 2u /*!< One end Active, one end passive, VCONN required */ -#define CABLE_TERM_BOTH_ACTIVE_VCONN 3u /*!< Both ends Active, VCONN required */ -#endif /* USBPD_REV30_SUPPORT */ - -typedef uint32_t USBPD_CableTermType; - -/** - * @} - */ - -#if defined(USBPD_REV30_SUPPORT) -/** - * @brief Maximum Cable VBUS Voltage in Active/Passive cable - * @{ - */ -#define VBUS_20V 0u /*!< Maximum Cable VBUS Voltage 20V */ -#define VBUS_30V 1u /*!< Maximum Cable VBUS Voltage 30V */ -#define VBUS_40V 2u /*!< Maximum Cable VBUS Voltage 40V */ -#define VBUS_50V 3u /*!< Maximum Cable VBUS Voltage 50V */ - -typedef uint32_t USBPD_VBUSMaxVoltage; - -/** - * @} - */ -#endif /* USBPD_REV30_SUPPORT */ - -/** - * @brief configurability of SS Directionality in Active/Passive cable and AMA VDO (PD2.0 only) - * @{ - */ -#define SS_DIR_FIXED 0u /*!< SSTX Directionality Support Fixed */ -#define SS_DIR_CONFIGURABLE 1u /*!< SSTX Directionality Support Configurable */ - -typedef uint32_t USBPD_SsDirectionality; - -/** - * @} - */ - -/** - * @brief SVDM commands definition - */ -#define SVDM_RESERVEDCOMMAND 0x00u -#define SVDM_DISCOVER_IDENTITY 0x01u -#define SVDM_DISCOVER_SVIDS 0x02u -#define SVDM_DISCOVER_MODES 0x03u -#define SVDM_ENTER_MODE 0x04u -#define SVDM_EXIT_MODE 0x05u -#define SVDM_ATTENTION 0x06u -#define SVDM_SPECIFIC_1 0x10u -#define SVDM_SPECIFIC_2 0x11u -#define SVDM_SPECIFIC_3 0x12u -#define SVDM_SPECIFIC_4 0x13u -#define SVDM_SPECIFIC_5 0x14u -#define SVDM_SPECIFIC_6 0x15u -#define SVDM_SPECIFIC_7 0x16u -#define SVDM_SPECIFIC_8 0x17u -#define SVDM_SPECIFIC_9 0x18u -#define SVDM_SPECIFIC_10 0x19u -#define SVDM_SPECIFIC_11 0x1Au -#define SVDM_SPECIFIC_12 0x1Bu -#define SVDM_SPECIFIC_13 0x1Cu -#define SVDM_SPECIFIC_14 0x1Du -#define SVDM_SPECIFIC_15 0x1Eu -#define SVDM_SPECIFIC_16 0x1Fu - -typedef uint32_t USBPD_VDM_Command_Typedef; - -/** - * @brief VBUS Current Handling Capability in Active/Passive cable VDO - * @{ - */ -#define VBUS_3A 1u /*!< VBUS Current Handling Capability 3A */ -#define VBUS_5A 2u /*!< VBUS Current Handling Capability 5A */ - -typedef uint32_t USBPD_VBUSCurrentHandCap; - -/** - * @} - */ - -/** - * @brief USB Superspeed Signaling Support in Active/Passive cable VDO - * @{ - */ -#define USB2P0_ONLY 0u /*!< USB2.0 only*/ -#define USB3P1_GEN1 1u /*!< USB3.1 Gen1 and USB2.0 */ -#define USB3P1_GEN1N2 2u /*!< USB3.1 Gen1, Gen2 and USB2.0*/ - -typedef uint32_t USBPD_UsbSsSupport; -/** - * @} - */ - -/** - * @brief Power needed by adapter for full functionality in AMA VDO header - * @{ - */ -typedef enum -{ - VCONN_1W = 0u, /*!< VCONN power 1W */ - VCONN_1P5W = 1u, /*!< VCONN power 1.5W */ - VCONN_2W = 2u, /*!< VCONN power 2W */ - VCONN_3W = 3u, /*!< VCONN power 3W */ - VCONN_4W = 4u, /*!< VCONN power 4W */ - VCONN_5W = 5u, /*!< VCONN power 5W */ - VCONN_6W = 6u, /*!< VCONN power 6W */ -} USBPD_VConnPower; - -/** - * @} - */ - -/** - * @brief VCONN being required by an adapter in AMA VDO header - * @{ - */ -typedef enum -{ - VCONN_NOT_REQUIRED = 0u, /*!< VCONN not required */ - VCONN_REQUIRED = 1u, /*!< VCONN required */ -} USBPD_VConnRequirement; - -/** - * @} - */ - -/** - * @brief VBUS being required by an adapter in AMA VDO header - * @{ - */ -typedef enum -{ - VBUS_NOT_REQUIRED = 0u, /*!< VBUS not required */ - VBUS_REQUIRED = 1u, /*!< VBUS required */ -} USBPD_VBusRequirement; - -/** - * @} - */ - -#define SVDM_INITIATOR 0x00u -#define SVDM_RESPONDER_ACK 0x01u -#define SVDM_RESPONDER_NAK 0x02u -#define SVDM_RESPONDER_BUSY 0x03u - -typedef uint32_t USBPD_VDM_CommandType_Typedef; - -/** - * @brief AMA USB Superspeed Signaling Support in AMA VDO header - * @{ - */ -typedef enum -{ - AMA_USB2P0_ONLY = 0u, /*!< USB2.0 only */ - AMA_USB3P1_GEN1 = 1u, /*!< USB3.1 Gen1 and USB2.0 */ - AMA_USB3P1_GEN1N2 = 2u, /*!< USB3.1 Gen1, Gen2 and USB2.0 */ - AMA_USB2P0_BILLBOARD = 3u, /*!< USB2.0 billboard only */ -} USBPD_AmaUsbSsSupport; - -/** - * @} - */ - -/** - * @} - */ - -#if defined(USBPDCORE_FWUPD) -/** - * @brief USBPD Firmware Update Status Information - * @{ - */ -typedef enum -{ - USBPD_FWUPD_STATUS_OK = 0x00u, /*!< Request completed successfully or delayed */ - USBPD_FWUPD_STATUS_ERR_TARGET = 0x01u, /*!< FW not targeted for this device */ - USBPD_FWUPD_STATUS_ERR_FILE = 0x02u, /*!< Fails vendor-specific verification test */ - USBPD_FWUPD_STATUS_ERR_WRITE = 0x03u, /*!< Unable to write memory */ - USBPD_FWUPD_STATUS_ERR_ERASE = 0x04u, /*!< Memory erase function failed */ - USBPD_FWUPD_STATUS_ERR_CHECK_ERASED = 0x05u, /*!< Memory erase check failed */ - USBPD_FWUPD_STATUS_ERR_PROG = 0x06u, /*!< Program memory function failed */ - USBPD_FWUPD_STATUS_ERR_VERIFY = 0x07u, /*!< Program memory failed verification */ - USBPD_FWUPD_STATUS_ERR_ADDRESS = 0x08u, /*!< Received address is out of range */ - USBPD_FWUPD_STATUS_ERR_NOTDONE = 0x09u, /*!< Received PDFU_DATA Request with a zero length Data Block, but the - PDFU Responder expects more data */ - USBPD_FWUPD_STATUS_ERR_FIRMWARE = 0x0Au, /*!< Device's firmware is corrupt. It cannot return to normal operations. */ - USBPD_FWUPD_STATUS_ERR_POR = 0x0Du, /*!< Unexpected power on reset */ - USBPD_FWUPD_STATUS_ERR_UNKNOWN = 0x0Eu, /*!< Something went wrong */ - USBPD_FWUPD_STATUS_ERR_UNEXPECTED_HARD_RESET = 0x80u, /*!< Used when firmware update starts after a hard reset (enumeration, etc.) - that occurred in the middle of firmware update */ - USBPD_FWUPD_STATUS_ERR_UNEXPECTED_SOFT_RESET = 0x81u, /*!< Used when firmware update starts after soft reset (new power contract, etc.) - that occurred in the middle of firmware update */ - USBPD_FWUPD_STATUS_ERR_UNEXPECTED_REQUEST = 0x82u, /*!< PDFU Responder received a request that is not appropriate for the current Phase */ - USBPD_FWUPD_STATUS_ERR_REJECT_PAUSE = 0x83u, /*!< PDFU Responder is unable or unwilling to pause a firmware image transfer */ -} USBPD_FWUPD_Status_TypeDef; -/** - * @} - */ -#endif /* USBPDCORE_FWUPD */ - -/** @defgroup USBPD_CORE_DataInfoType_TypeDef USB CORE Data information type - * @brief Data Infor types used in PE callbacks (USBPD_PE_GetDataInfo and USBPD_PE_SetDataInfo) - * @{ - */ -typedef enum -{ - USBPD_CORE_DATATYPE_SRC_PDO = 0x00u, /*!< Handling of port Source PDO */ - USBPD_CORE_DATATYPE_SNK_PDO = 0x01u, /*!< Handling of port Sink PDO */ - USBPD_CORE_DATATYPE_RDO_POSITION = 0x02u, /*!< Storage of requested DO position in PDO list */ - USBPD_CORE_DATATYPE_REQ_VOLTAGE = 0x03u, /*!< Storage of requested voltage value */ - USBPD_CORE_DATATYPE_RCV_SRC_PDO = 0x04u, /*!< Storage of Received Source PDO values */ - USBPD_CORE_DATATYPE_RCV_SNK_PDO = 0x05u, /*!< Storage of Received Sink PDO values */ - USBPD_CORE_DATATYPE_RCV_REQ_PDO = 0x06u, /*!< Storage of Received Sink Request PDO value */ - USBPD_CORE_DATATYPE_REQUEST_DO = 0x07u, /*!< Storage of DO to be used in request message (from Sink to Source) */ - USBPD_CORE_EXTENDED_CAPA = 0x08u, /*!< Extended capability */ - USBPD_CORE_INFO_STATUS = 0x09u, /*!< Information status */ - USBPD_CORE_PPS_STATUS = 0x0Au, /*!< PPS Status data */ - USBPD_CORE_ALERT , /*!< Alert */ - USBPD_CORE_GET_MANUFACTURER_INFO , /*!< Get Manufacturer Info */ - USBPD_CORE_MANUFACTURER_INFO , /*!< Manufacturer Info */ - USBPD_CORE_GET_BATTERY_STATUS , /*!< Get Battery Status */ - USBPD_CORE_BATTERY_STATUS , /*!< Battery Status */ - USBPD_CORE_GET_BATTERY_CAPABILITY , /*!< Get Battery Capability */ - USBPD_CORE_BATTERY_CAPABILITY , /*!< Battery Capability */ - USBPD_CORE_UNSTRUCTURED_VDM , /*!< Unstructured VDM messag */ -#if defined(USBPDCORE_SNK_CAPA_EXT) - USBPD_CORE_SNK_EXTENDED_CAPA , /*!< Sink Extended capability */ -#endif /* USBPDCORE_SNK_CAPA_EXT */ -} USBPD_CORE_DataInfoType_TypeDef; -/** - * @} - */ - -/** - * @} - */ - -/* Exported typedef ----------------------------------------------------------*/ - -/** @defgroup USBPD_CORE_DEF_Exported_TypeDef USBPD CORE DEF Exported TypeDef - * @{ - */ - -#if defined(USBPD_REV30_SUPPORT) && defined(USBPDCORE_PPS) -/** - * @brief USB PD Programmable Power Supply APDO Structure definition (same for SRC and SNK) - * - */ -typedef struct -{ - uint32_t MaxCurrentIn50mAunits : 7u; /*!< Maximum Current in 50mA increments */ - uint32_t Reserved1 : 1u; /*!< Reserved - Shall be set to zero */ - uint32_t MinVoltageIn100mV : 8u; /*!< Minimum Voltage in 100mV increments */ - uint32_t Reserved2 : 1u; /*!< Reserved - Shall be set to zero */ - uint32_t MaxVoltageIn100mV : 8u; /*!< Maximum Voltage in 100mV increments */ - uint32_t Reserved3 : 3u; /*!< Reserved - Shall be set to zero */ - uint32_t ProgrammablePowerSupply: 2u; /*!< 00b - Programmable Power Supply */ - uint32_t PPS_APDO : 2u; /*!< 11b - Augmented Power Data Object (APDO) */ -} USBPD_ProgrammablePowerSupplyAPDO_TypeDef; - -#endif /*_USBPD_REV30_SUPPORT && PPS*/ - -/** - * @brief USB PD Source Fixed Supply Power Data Object Structure definition - * - */ -typedef struct -{ - uint32_t MaxCurrentIn10mAunits : 10u; - uint32_t VoltageIn50mVunits : 10u; - USBPD_CORE_PDO_PeakCurr_TypeDef PeakCurrent : 2u; -#if defined(USBPD_REV30_SUPPORT) - uint32_t Reserved22_23 : 2u; - uint32_t UnchunkedExtendedMessage : 1u; -#else - uint32_t Reserved22_24 : 3u; -#endif /* USBPD_REV30_SUPPORT */ - USBPD_CORE_PDO_DRDataSupport_TypeDef DataRoleSwap : 1u; - USBPD_CORE_PDO_USBCommCapable_TypeDef USBCommunicationsCapable : 1u; - USBPD_CORE_PDO_ExtPowered_TypeDef ExternallyPowered : 1u; - USBPD_CORE_PDO_USBSuspendSupport_TypeDef USBSuspendSupported : 1u; - USBPD_CORE_PDO_DRPowerSupport_TypeDef DualRolePower : 1u; - USBPD_CORE_PDO_Type_TypeDef FixedSupply : 2u; - -} USBPD_SRCFixedSupplyPDO_TypeDef; - -/** - * @brief USB PD Source Variable Supply Power Data Object Structure definition - * - */ -typedef struct -{ - uint32_t MaxCurrentIn10mAunits : - 10u; - uint32_t MinVoltageIn50mVunits : - 10u; - uint32_t MaxVoltageIn50mVunits : - 10u; - uint32_t VariableSupply : - 2u; -} USBPD_SRCVariableSupplyPDO_TypeDef; - -/** - * @brief USB PD Source Battery Supply Power Data Object Structure definition - * - */ -typedef struct -{ - uint32_t MaxAllowablePowerIn250mWunits : - 10u; - uint32_t MinVoltageIn50mVunits : - 10u; - uint32_t MaxVoltageIn50mVunits : - 10u; - uint32_t Battery : - 2u; -} USBPD_SRCBatterySupplyPDO_TypeDef; - -/** - * @brief USB PD Sink Fixed Supply Power Data Object Structure definition - * - */ -typedef struct -{ - uint32_t OperationalCurrentIn10mAunits : - 10u; - uint32_t VoltageIn50mVunits : - 10u; -#if defined(USBPD_REV30_SUPPORT) - uint32_t FastRoleSwapRequiredCurrent : - 2u; - uint32_t Reserved20_22 : - 3u; -#else - uint32_t Reserved20_24 : - 5u; -#endif /* USBPD_REV30_SUPPORT */ - uint32_t DataRoleSwap : - 1u; - uint32_t USBCommunicationsCapable : - 1; - uint32_t ExternallyPowered : - 1u; - uint32_t HigherCapability : - 1u; - uint32_t DualRolePower : - 1u; - uint32_t FixedSupply : - 2u; -} USBPD_SNKFixedSupplyPDO_TypeDef; - -/** - * @brief USB PD Sink Variable Supply Power Data Object Structure definition - * - */ -typedef struct -{ - uint32_t OperationalCurrentIn10mAunits : - 10u; - uint32_t MinVoltageIn50mVunits : - 10u; - uint32_t MaxVoltageIn50mVunits : - 10u; - uint32_t VariableSupply : - 2u; -} USBPD_SNKVariableSupplyPDO_TypeDef; - -/** - * @brief USB PD Sink Battery Supply Power Data Object Structure definition - * - */ -typedef struct -{ - uint32_t OperationalPowerIn250mWunits : - 10u; - uint32_t MinVoltageIn50mVunits : - 10u; - uint32_t MaxVoltageIn50mVunits : - 10u; - uint32_t Battery : - 2u; -} USBPD_SNKBatterySupplyPDO_TypeDef; - -/** - * @brief USB PD Sink Generic Power Data Object Structure definition - * - */ -typedef struct -{ - uint32_t Bits_0_10 : 10u; /*!< Specific Power Capabilities are described by the (A)PDOs in the following sections. */ - uint32_t VoltageIn50mVunits : 10u; /*!< Maximum Voltage in 50mV units valid for all PDO (not APDO) */ - uint32_t Bits_20_29 : 10u; /*!< Specific Power Capabilities are described by the (A)PDOs in the following sections. */ - USBPD_CORE_PDO_Type_TypeDef PowerObject : 2u; /*!< (A) Power Data Object */ -} USBPD_GenericPDO_TypeDef; - -/** - * @brief USB PD Power Data Object Structure definition - * - */ -typedef union -{ - uint32_t d32; - - USBPD_GenericPDO_TypeDef GenericPDO; /*!< Generic Power Data Object Structure */ - - USBPD_SRCFixedSupplyPDO_TypeDef SRCFixedPDO; /*!< Fixed Supply PDO - Source */ - - USBPD_SRCVariableSupplyPDO_TypeDef SRCVariablePDO; /*!< Variable Supply (non-Battery) PDO - Source */ - - USBPD_SRCBatterySupplyPDO_TypeDef SRCBatteryPDO; /*!< Battery Supply PDO - Source */ - - USBPD_SNKFixedSupplyPDO_TypeDef SNKFixedPDO; /*!< Fixed Supply PDO - Sink */ - - USBPD_SNKVariableSupplyPDO_TypeDef SNKVariablePDO; /*!< Variable Supply (non-Battery) PDO - Sink */ - - USBPD_SNKBatterySupplyPDO_TypeDef SNKBatteryPDO; /*!< Battery Supply PDO - Sink */ - -#if defined(USBPD_REV30_SUPPORT) -#ifdef USBPDCORE_PPS - USBPD_ProgrammablePowerSupplyAPDO_TypeDef SRCSNKAPDO;/*!< Programmable Power Supply APDO - Source / Sink */ -#endif /* USBPDCORE_PPS */ -#endif /* USBPD_REV30_SUPPORT */ - -} USBPD_PDO_TypeDef; - -/** - * @brief USB PD Sink Fixed and Variable Request Data Object Structure definition - * - */ -typedef struct -{ - uint32_t MaxOperatingCurrent10mAunits : /*!< Corresponding to min if GiveBackFlag = 1 */ - 10u; - uint32_t OperatingCurrentIn10mAunits : - 10u; -#if defined(USBPD_REV30_SUPPORT) - uint32_t Reserved20_22 : - 3u; - uint32_t UnchunkedExtendedMessage : - 1u; -#else - uint32_t Reserved20_23 : - 4u; -#endif /* USBPD_REV30_SUPPORT */ - uint32_t NoUSBSuspend : - 1u; - uint32_t USBCommunicationsCapable : - 1u; - uint32_t CapabilityMismatch : - 1u; - uint32_t GiveBackFlag : - 1u; - uint32_t ObjectPosition : - 3u; - uint32_t Reserved31 : - 1u; -} USBPD_SNKFixedVariableRDO_TypeDef; - -/** - * @brief USB PD Sink Battery Request Data Object Structure definition - * - */ -typedef struct -{ - uint32_t MaxOperatingPowerIn250mWunits : - 10u; - uint32_t OperatingPowerIn250mWunits : - 10u; -#if defined(USBPD_REV30_SUPPORT) - uint32_t Reserved20_22 : - 3u; - uint32_t UnchunkedExtendedMessage : - 1u; /*!< Unchunked Extended Messages Supported */ -#else - uint32_t Reserved20_23 : - 4u; -#endif /* USBPD_REV30_SUPPORT */ - uint32_t NoUSBSuspend : - 1u; - uint32_t USBCommunicationsCapable : - 1u; - uint32_t CapabilityMismatch : - 1u; - uint32_t GiveBackFlag : - 1u; - uint32_t ObjectPosition : - 3u; - uint32_t Reserved31 : - 1u; -} USBPD_SNKBatteryRDO_TypeDef; - -#if defined(USBPD_REV30_SUPPORT) -/** - * @brief USB PD Sink Programmable Request Data Object Structure definition - * - */ -typedef struct -{ - uint32_t OperatingCurrentIn50mAunits : 7u; /*!< Operating Current 50mA units */ - uint32_t Reserved1 : 2u; /*!< Reserved - Shall be set to zero */ - uint32_t OutputVoltageIn20mV : 11; /*!< Output Voltage in 20mV units */ - uint32_t Reserved2 : 3u; /*!< Reserved - Shall be set to zero */ - uint32_t UnchunkedExtendedMessage : 1u; /*!< Unchunked Extended Messages Supported */ - uint32_t NoUSBSuspend : 1u; /*!< No USB Suspend */ - uint32_t USBCommunicationsCapable : 1u; /*!< USB Communications Capable */ - uint32_t CapabilityMismatch : 1u; /*!< Capability Mismatch */ - uint32_t Reserved3 : 1u; /*!< Reserved - Shall be set to zero */ - uint32_t ObjectPosition : 3u; /*!< Object position (000b is Reserved and Shall Not be used) */ - uint32_t Reserved4 : 1u; /*!< USB Communications Capable */ -} USBPD_SNKProgrammableRDO_TypeDef; -#endif /* USBPD_REV30_SUPPORT */ - - -/** - * @brief USB PD Sink Generic Request Data Object Structure definition - * - */ -typedef struct -{ -#if defined(USBPD_REV30_SUPPORT) - uint32_t Bits_0_22 : 23; /*!< Bits 0 to 22 of RDO */ - uint32_t UnchunkedExtendedMessage : 1u; /*!< Unchunked Extended Messages Supported */ -#else - uint32_t Bits_0_23 : 24u; /*!< Bits 0 to 23 of RDO */ -#endif /* USBPD_REV30_SUPPORT */ - uint32_t NoUSBSuspend : 1u; /*!< No USB Suspend */ - uint32_t USBCommunicationsCapable : 1u; /*!< USB Communications Capable */ - uint32_t CapabilityMismatch : 1u; /*!< Capability Mismatch */ - uint32_t Bit_27 : 1u; /*!< Reserved - Shall be set to zero */ - uint32_t ObjectPosition : 3u; /*!< Object position (000b is Reserved and Shall Not be used) */ - uint32_t Bit_31 : 1u; /*!< USB Communications Capable */ -} USBPD_SNKGenericRDO_TypeDef; - -/** - * @brief USB PD Sink Request Data Object Structure definition - * - */ -typedef union -{ - uint32_t d32; - - USBPD_SNKGenericRDO_TypeDef GenericRDO; /*!< Generic Request Data Object Structure */ - - USBPD_SNKFixedVariableRDO_TypeDef FixedVariableRDO; /*!< Fixed and Variable Request Data Object Structure */ - - USBPD_SNKBatteryRDO_TypeDef BatteryRDO; /*!< Battery Request Data Object Structure */ - -#if defined(USBPD_REV30_SUPPORT) - USBPD_SNKProgrammableRDO_TypeDef ProgRDO; /*!< Programmable Request Data Object Structure */ -#endif /* USBPD_REV30_SUPPORT */ - -} USBPD_SNKRDO_TypeDef; - -#if defined(USBPD_REV30_SUPPORT) && defined(USBPDCORE_PPS) -/** - * @brief USBPD Port APDO Structure definition - * - */ -typedef struct -{ - uint32_t *ListOfAPDO; /*!< Pointer on Augmented Power Data Objects list, defining - port capabilities */ - uint8_t NumberOfAPDO; /*!< Number of Augmented Power Data Objects defined in ListOfAPDO - This parameter must be set at max to @ref USBPD_MAX_NB_PDO value */ -}USBPD_PortAPDO_TypeDef; -#endif /* USBPD_REV30_SUPPORT && USBPDCORE_PPS */ - -/** - * @brief USB PD BIST Data Object Structure definition - * - */ -typedef union -{ - uint32_t d32; - struct - { - uint32_t BistErrorCounter : - 16u; - uint32_t Reserved16_27 : - 12u; - uint32_t BistMode : - 4u; - } - b; -} USBPD_BISTDataObject_TypeDef; - -/** @brief Sink requested power profile Structure definition - * - */ -typedef struct -{ - uint32_t MaxOperatingCurrentInmAunits; /*!< Sink board Max operating current in mA units */ - uint32_t OperatingVoltageInmVunits; /*!< Sink board operating voltage in mV units */ - uint32_t MaxOperatingVoltageInmVunits; /*!< Sink board Max operating voltage in mV units */ - uint32_t MinOperatingVoltageInmVunits; /*!< Sink board Min operating voltage in mV units */ - uint32_t OperatingPowerInmWunits; /*!< Sink board operating power in mW units */ - uint32_t MaxOperatingPowerInmWunits; /*!< Sink board Max operating power in mW units */ -} USBPD_SNKPowerRequest_TypeDef; - - -/** @defgroup USBPD_CORE_VDM_Exported_Structures USBPD CORE VDM Exported Structures - * @{ - */ - -/** @defgroup USBPD_ProductVdo_TypeDef USB PD VDM Product VDO - * @brief USB PD Product VDO Structure definition - * @{ - */ -typedef union -{ - uint32_t d32; - struct - { - uint32_t bcdDevice : /*!< Device version */ - 16u; - uint32_t USBProductId : /*!< USB Product ID */ - 16u; - } - b; -}USBPD_ProductVdo_TypeDef; - -/** - * @} - */ - -/** @defgroup USBPD_IDHeaderVDOStructure_definition USB SVDM ID header VDO Structure definition - * @brief USB SVDM ID header VDO Structure definition - * @{ - */ -typedef union -{ - uint32_t d32; - struct - { - uint32_t VID : 16u; /*!< SVDM Header's SVDM Version */ - uint32_t Reserved : 10u; /*!< Reserved */ - USBPD_ModalOp_TypeDef ModalOperation : 1u; /*!< Modal Operation Supported based on - @ref USBPD_ModalOp_TypeDef */ - USBPD_ProductType_TypeDef ProductTypeUFPorCP : 3u; /*!< Product Type (UFP or Cable Plug)based on - @ref USBPD_ProductType_TypeDef */ - USBPD_USBCapa_TypeDef USBDevCapability : 1u; /*!< USB Communications Capable as a USB Device based on - @ref USBPD_USBCapa_TypeDef */ - USBPD_USBCapa_TypeDef USBHostCapability : 1u; /*!< USB Communications Capable as USB Host based on - @ref USBPD_USBCapa_TypeDef */ - }b20; -#if defined(USBPD_REV30_SUPPORT) - struct - { - uint32_t VID : 16u; /*!< SVDM Header's SVDM Version */ - uint32_t Reserved : 7u; /*!< Reserved */ - uint32_t ProductTypeDFP : 3u; /*!< Product Type (DFP) based on - @ref USBPD_ProductType_TypeDef */ - USBPD_ModalOp_TypeDef ModalOperation : 1u; /*!< Modal Operation Supported based on - @ref USBPD_ModalOp_TypeDef */ - USBPD_ProductType_TypeDef ProductTypeUFPorCP : 3u; /*!< Product Type (UFP or Cable Plug)based on - @ref USBPD_ProductType_TypeDef */ - USBPD_USBCapa_TypeDef USBDevCapability : 1u; /*!< USB Communications Capable as a USB Device based on - @ref USBPD_USBCapa_TypeDef */ - USBPD_USBCapa_TypeDef USBHostCapability : 1u; /*!< USB Communications Capable as USB Host based on - @ref USBPD_USBCapa_TypeDef */ - }b30; -#endif /* USBPD_REV30_SUPPORT */ -}USBPD_IDHeaderVDO_TypeDef; -/** - * @} - */ - -typedef union -{ - struct /* PD 2.0*/ - { - USBPD_SsDirectionality SSRX2_DirSupport : 1u; /*!< SSRX2 Directionality Support (PD2.0) */ - USBPD_SsDirectionality SSRX1_DirSupport : 1u; /*!< SSRX1 Directionality Support (PD2.0) */ - USBPD_SsDirectionality SSTX2_DirSupport : 1u; /*!< SSTX2 Directionality Support (PD2.0) */ - USBPD_SsDirectionality SSTX1_DirSupport : 1u; /*!< SSTX1 Directionality Support (PD2.0) */ - } - pd_v20; -#if defined(USBPD_REV30_SUPPORT) - struct /* PD 3.0*/ - { - uint8_t Reserved : 2u; /*!< Reserved */ - USBPD_VBUSMaxVoltage MaxVBUS_Voltage : 2u; /*!< Maximum Cable VBUS Voltage */ - } - pd_v30; -#endif /* USBPD_REV30_SUPPORT */ -} USBPD_CableVdo_Field1TypeDef; - -/** @defgroup USBPD_AttentionInfo_TypeDef USB PD Attention Info object Structure definition - * @brief USB PD Attention Info object Structure definition - * @{ - */ -typedef struct -{ - uint32_t VDO; - uint16_t SVID; - USBPD_VDM_Command_Typedef Command; - uint8_t ModeIndex; -}USBPD_AttentionInfo_TypeDef; - -/** - * @} - */ - -typedef union -{ - struct /* PD 2.0*/ - { - uint8_t Reserved : 4u; /*!< Reserved */ - } - pd_v20; -#if defined(USBPD_REV30_SUPPORT) - struct /* PD 3.0*/ - { - uint8_t VDOVersion : 3u; /*!< Version Number of the VDO */ - uint8_t Reserved : 1u; /*!< Reserved */ - } - pd_v30; -#endif /* USBPD_REV30_SUPPORT */ -}USBPD_CableVdo_Field2TypeDef; - -#define VDM_UNSTRUCTUREDVDM_TYPE 0x0u -#define VDM_STRUCTUREDVDM_TYPE 0x1u - -typedef uint32_t USBPD_VDM_VDMType_Typedef; - -/** @defgroup USBPD_SVDMHeaderStructure_definition USB SVDM Message header Structure definition - * @brief USB SVDM Message header Structure definition - * @{ - */ -typedef union -{ - uint32_t d32; - struct - { - USBPD_VDM_Command_Typedef Command : /*!< SVDM Header's Command */ - 5u; - uint32_t Reserved5 : /*!< Reserved */ - 1u; - USBPD_VDM_CommandType_Typedef CommandType : /*!< SVDM Header's Command Type */ - 2u; - uint32_t ObjectPosition : /*!< SVDM Header's Object Position */ - 3u; - uint32_t Reserved11 : /*!< Reserved */ - 2u; - uint32_t SVDMVersion : /*!< SVDM Header's SVDM Version */ - 2u; - USBPD_VDM_VDMType_Typedef VDMType : /*!< SVDM Header's VDM Type */ - 1u; - uint32_t SVID : /*!< SVDM Header's SVID */ - 16u; - } - b; -}USBPD_SVDMHeader_TypeDef; - -/** - * @} - */ - -#ifdef USBPDCORE_UVDM -/** @defgroup USBPD_UVDMHeaderStructure_definition USB UVDM Message header Structure definition - * @brief USB UVDM Message header Structure definition - * @{ - */ -typedef union -{ - uint32_t d32; - struct - { - uint32_t VendorUse : 15u; /*!< Content of this field is defined by the vendor. */ - USBPD_VDM_VDMType_Typedef VDMType : 1u; /*!< VDM Type */ - uint32_t VID : 16u; /*!< Vendor ID (VID) */ - } - b; -}USBPD_UVDMHeader_TypeDef; - -/** - * @} - */ -#endif /* USBPDCORE_UVDM */ - -/** @defgroup USBPD_CableVdo_TypeDef USB PD VDM Cable VDO - * @brief USB PD Cable VDO Structure definition - * @{ - */ -typedef union -{ - uint32_t d32; - struct - { - USBPD_UsbSsSupport USB_SS_Support : 3u; /*!< USB SuperSpeed Signaling Support */ - uint32_t reserved : 2u; - USBPD_VBUSCurrentHandCap VBUS_CurrentHandCap : 2u; /*!< VBUS Current Handling Capability */ - uint32_t Fields1 : 2u; /*!< Based on @ref USBPD_CableVdo_Field1TypeDef */ - USBPD_CableMaxVoltage CableMaxVoltage : 2u; /*!< Cable maximun voltage */ - USBPD_CableTermType CableTermType : 2u; /*!< Cable Termination Type */ - uint32_t CableLatency : 4u; /*!< Cable Latency */ - uint32_t Reserved : 1u; /*!< Reserved */ - USBPD_CableToType CableToType : 2u; /*!< USB Type-C plug to USB Type-A/B/C/Captive (PD 2.0) - USB Type-C plug to USB Type-C/Captive (PD 3.0) */ - uint32_t Fields2 : 1u; /*!< Based on @ref USBPD_CableVdo_Field2TypeDef */ - uint32_t VDO_Version : 3u; /*!< Version number of the VDO */ - uint32_t CableFWVersion : 4u; /*!< Cable FW version number (vendor defined) */ - uint32_t CableHWVersion : 4u; /*!< Cable HW version number (vendor defined) */ - } - b; -}USBPD_CableVdo_TypeDef; - -/** - * @} - */ - -/** @defgroup USBPD_CertStatVdo_TypeDef USB PD VDM Cert stat VDO - * @brief USB PD Cert stat VDO Structure definition - * @{ - */ -typedef union -{ - uint32_t d32; - struct - { - uint32_t XID : /*!< USB-IF assigned XID */ - 32; - } - b; -}USBPD_CertStatVdo_TypeDef; - -/** - * @} - */ - -/** @defgroup USBPD_AMAVdo_TypeDef USB PD VDM Alternate Mode Adapter VDO - * @brief USB PD Alternate Mode Adapter VDO Structure definition - * @{ - */ -typedef union -{ - uint32_t d32; - struct - { - uint32_t AMA_USB_SS_Support : 3u; /*!< AMA USB SuperSpeed Signaling Support based on - @ref USBPD_AmaUsbSsSupport */ - uint32_t VBUSRequirement : 1u; /*!< VBUS required based on - @ref USBPD_VBusRequirement */ - uint32_t VCONNRequirement : 1u; /*!< VCONN required based on - @ref USBPD_VConnRequirement */ - uint32_t VCONNPower : 3u; /*!< VCONN power based on - @ref USBPD_VConnPower */ -#if defined(USBPD_REV30_SUPPORT) - uint32_t Reserved : 13; /*!< Reserved */ - uint32_t VDO_Version : 3u; /*!< Version Number of the VDO */ -#else - uint32_t SSRX2_DirSupport : 1u; /*!< SSRX2 Directionality Support (PD2.0) based on - @ref USBPD_SsDirectionality */ - uint32_t SSRX1_DirSupport : 1u; /*!< SSRX1 Directionality Support (PD2.0) based on - @ref USBPD_SsDirectionality */ - uint32_t SSTX2_DirSupport : 1u; /*!< SSTX2 Directionality Support (PD2.0) based on - @ref USBPD_SsDirectionality */ - uint32_t SSTX1_DirSupport : 1u; /*!< SSTX1 Directionality Support (PD2.0) based on - @ref USBPD_SsDirectionality */ - uint32_t Reserved : 12u; /*!< Reserved */ -#endif /* USBPD_REV30_SUPPORT */ - uint32_t AMAFWVersion : 4u; /*!< AMA FW version number (vendor defined) */ - uint32_t AMAHWVersion : 4u; /*!< AMA HW version number (vendor defined) */ - } - b; -}USBPD_AMAVdo_TypeDef; -/** - * @} - */ - -/** @defgroup USBPD_DiscoveryIdentity_TypeDef USB PD Discovery identity Structure definition - * @brief Data received from Discover Identity messages - * @{ - */ -typedef struct -{ - - USBPD_IDHeaderVDO_TypeDef IDHeader; /*!< ID Header VDO */ - USBPD_CertStatVdo_TypeDef CertStatVDO; /*!< Cert Stat VDO */ - USBPD_ProductVdo_TypeDef ProductVDO; /*!< Product VDO */ - USBPD_CableVdo_TypeDef CableVDO; /*!< Passive Cable VDO */ - USBPD_AMAVdo_TypeDef AMA_VDO; /*!< Alternate Mode Adapter VDO */ - uint8_t CableVDO_Presence:1u; /*!< Indicate Passive Cable VDO presence or not */ - uint8_t AMA_VDO_Presence:1u; /*!< Indicate Alternate Mode Adapter VDO presence or not */ - uint8_t Reserved:6u; /*!< Reserved bits */ -} USBPD_DiscoveryIdentity_TypeDef; -/** - * @} - */ - -/** @defgroup USBPD_ModeInfo_TypeDef USB PD Mode Info object Structure definition - * @brief USB PD Mode Info object Structure definition - * @{ - */ -typedef struct -{ - uint32_t NumModes; - uint32_t Modes[MAX_MODES_PER_SVID]; - uint16_t SVID; -}USBPD_ModeInfo_TypeDef; - -/** - * @} - */ - -/** @defgroup USBPD_SVID_TypeDef USB PD Discovery SVID Structure definition - * @brief Data received from Discover Identity messages - * @{ - */ -/* - * Structure to SVID supported by the devices - */ -typedef struct -{ - uint16_t SVIDs[12u]; - uint8_t NumSVIDs; - uint8_t AllSVID_Received; /*!< Flag to indicate that all the SVIDs have been received. - No need to send new SVDM Discovery SVID message */ -}USBPD_SVIDInfo_TypeDef; -/** - * @} - */ - -#if defined(USBPD_REV30_SUPPORT) -/** - * @brief USBPD Alert Data Object Structure definition - * - */ -typedef union -{ - uint32_t d32; - struct - { - uint32_t Reserved : 16u; /*!< Reserved */ - uint32_t HotSwappableBatteries: 4u; /*!< Hot Swappable Batteries is a combination of @ref USBPD_ADO_HOT_SWAP_BATT */ - uint32_t FixedBatteries : 4u; /*!< Fixed Batteries is a combination of @ref USBPD_ADO_FIXED_BATT */ - uint32_t TypeAlert : 8u; /*!< Type of Alert is a combination of @ref USBPD_ADO_TYPE_ALERT */ - } - b; -} USBPD_ADO_TypeDef; - -/** - * @brief USBPD Battery Status Data Object Structure definition - * - */ -typedef union -{ - uint32_t d32; - struct - { - uint32_t Reserved: 8u; - uint32_t BatteryInfo: 8u; /*!< Based on @ref USBPD_BSDO_BATT_INFO */ - uint32_t BatteryPC: 16u; - } - b; -} USBPD_BSDO_TypeDef; - -/** - * @brief USBPD Source Capabilities Extended Message Structure definition - * - */ -typedef struct USBPD_SCEDB_TypeDef -{ - uint16_t VID; /*!< Vendor ID (assigned by the USB-IF) */ - uint16_t PID; /*!< Product ID (assigned by the manufacturer) */ - uint32_t XID; /*!< Value provided by the USB-IF assigned to the product */ - uint8_t FW_revision; /*!< Firmware version number */ - uint8_t HW_revision; /*!< Hardware version number */ - uint8_t Voltage_regulation; /*!< Voltage Regulation */ - uint8_t Holdup_time; /*!< Holdup Time */ - uint8_t Compliance; /*!< Compliance */ - uint8_t TouchCurrent; /*!< Touch Current */ - uint16_t PeakCurrent1; /*!< Peak Current1 */ - uint16_t PeakCurrent2; /*!< Peak Current2 */ - uint16_t PeakCurrent3; /*!< Peak Current3 */ - uint8_t Touchtemp; /*!< Touch Temp */ - uint8_t Source_inputs; /*!< Source Inputs */ - uint8_t NbBatteries; /*!< Number of Batteries/Battery Slots */ - uint8_t SourcePDP; /*!< Source PDP */ -} USBPD_SCEDB_TypeDef; - -#if defined(USBPDCORE_SNK_CAPA_EXT) -/** - * @brief SKEDB - Sink Load Characteristics structure definition - * - */ -typedef union -{ - uint16_t Value; - struct - { - uint16_t PercentOverload : 5u; /*!< Percent overload in 10% increments Values higher than 25 (11001b) are clipped to 250%. - 00000b is the default. */ - uint16_t OverloadPeriod : 6u; /*!< Overload period in 20ms when bits 0-4 non-zero. */ - uint16_t DutyCycle : 4u; /*!< Duty cycle in 5% increments when bits 0-4 are non-zero. */ - uint16_t VBusVoltageDrop : 1u; /*!< Can tolerate VBUS Voltage drop. */ - } b; -} USBPD_SKEDB_SinkLoadCharac_TypeDef; -/** - * @brief USBPD Sink Capabilities Extended Message Structure definition - * - */ -typedef struct USBPD_SKEDB_TypeDef -{ - uint16_t VID; /*!< Vendor ID (assigned by the USB-IF) */ - uint16_t PID; /*!< Product ID (assigned by the manufacturer) */ - uint32_t XID; /*!< Value provided by the USB-IF assigned to the product */ - uint8_t FW_revision; /*!< Firmware version number */ - uint8_t HW_revision; /*!< Hardware version number */ - uint8_t SKEDB_Version; /*!< SKEDB Version (not the specification Version) based on - @ref USBPD_SKEDB_VERSION */ - uint8_t LoadStep; /*!< Load Step based on @ref USBPD_SKEDB_LOADSTEP */ - USBPD_SKEDB_SinkLoadCharac_TypeDef SinkLoadCharac; /*!< Sink Load Characteristics */ - uint8_t Compliance; /*!< Compliance based on combination of @ref USBPD_SKEDB_COMPLIANCE */ - uint8_t Touchtemp; /*!< Touch Temp based on @ref USBPD_SKEDB_TOUCHTEMP */ - uint8_t BatteryInfo; /*!< Battery info */ - uint8_t SinkModes; /*!< Sink Modes based on combination of @ref USBPD_SKEDB_SINKMODES */ - uint8_t SinkMinimumPDP; /*!< The Minimum PDP required by the Sink to operate without - consuming any power from its Battery(s) should it have one */ - uint8_t SinkOperationalPDP; /*!< The PDP the Sink requires to operate normally. For Sinks with - a Battery, it is the PDP Rating of the charger supplied with - it or recommended for it. */ - uint8_t SinkMaximumPDP; /*!< The Maximum PDP the Sink can consume to operate and - charge its Battery(s) should it have one. */ -} USBPD_SKEDB_TypeDef; -#endif /* USBPDCORE_SNK_CAPA_EXT */ - -/** - * @brief USBPD Source Status Extended Message Structure definition - * - */ -typedef __PACKEDSTRUCTBEGIN -{ - uint8_t InternalTemp; /*!< Source or Sink internal temperature in degrees centigrade */ - uint8_t PresentInput; /*!< Present Input */ - uint8_t PresentBatteryInput; /*!< Present Battery Input */ - uint8_t EventFlags; /*!< Event Flags */ - uint8_t TemperatureStatus; /*!< Temperature */ - uint8_t PowerStatus; /*!< Power Status based on combination of @ref USBPD_SDB_POWER_STATUS */ -} __PACKEDSTRUCTEND USBPD_SDB_TypeDef; - -/** - * @brief USBPD Get Battery Capabilities Data Block Extended Message Structure definition - * - */ -typedef __PACKEDSTRUCTBEGIN -{ - uint8_t BatteryCapRef; /*!< Number of the Battery indexed from zero */ -} __PACKEDSTRUCTEND USBPD_GBCDB_TypeDef; - -/** - * @brief USBPD Get Battery Status Data Block Extended Message Structure definition - * - */ -typedef __PACKEDSTRUCTBEGIN -{ - uint8_t BatteryStatusRef; /*!< Number of the Battery indexed from zero */ -} __PACKEDSTRUCTEND USBPD_GBSDB_TypeDef; - -/** - * @brief USBPD Battery Capability Data Block Extended Message Structure definition - * - */ -typedef __PACKEDSTRUCTBEGIN -{ - uint16_t VID; /*!< Vendor ID (assigned by the USB-IF) */ - uint16_t PID; /*!< Product ID (assigned by the manufacturer) */ - uint16_t BatteryDesignCapa; /*!< Battery Design Capacity */ - uint16_t BatteryLastFullChargeCapa; /*!< Battery last full charge capacity */ - uint8_t BatteryType; /*!< Battery Type */ -} __PACKEDSTRUCTEND USBPD_BCDB_TypeDef; - -/** - * @brief USBPD Get Manufacturer Info Info Data Block Extended Message Structure definition - * - */ -typedef __PACKEDSTRUCTBEGIN -{ - uint8_t ManufacturerInfoTarget; /*!< Manufacturer Info Target based on @ref USBPD_MANUFINFO_TARGET */ - uint8_t ManufacturerInfoRef; /*!< Manufacturer Info Ref between Min_Data=0 and Max_Data=7 (@ref USBPD_MANUFINFO_REF) */ -} __PACKEDSTRUCTEND USBPD_GMIDB_TypeDef; - -/** - * @brief USBPD Manufacturer Info Data Block Extended Message Structure definition - * - */ -typedef struct -{ - uint16_t VID; /*!< Vendor ID (assigned by the USB-IF) */ - uint16_t PID; /*!< Product ID (assigned by the manufacturer) */ - uint8_t ManuString[22]; /*!< Vendor defined byte array */ -} USBPD_MIDB_TypeDef; - -#if defined(USBPDCORE_FWUPD) -/** - * @brief USBPD Firmware Update GET_FW_ID Response Payload Structure definition - * - */ -typedef __PACKEDSTRUCTBEGIN -{ - USBPD_FWUPD_Status_TypeDef Status; /*!< Status Information during Firmware Update */ - uint16_t VID; /*!< USB-IF assigned Vendor ID */ - uint16_t PID; /*!< USB-IF assigned Product ID */ - uint8_t HWVersion; /*!< Hardware Version */ - uint8_t SiVersion; /*!< Silicon Version */ - uint16_t FWVersion1; /*!< Most significant component of the firmware version */ - uint16_t FWVersion2; /*!< Second-most significant component of the firmware version */ - uint16_t FWVersion3; /*!< Third-most significant component of the firmware version */ - uint16_t FWVersion4; /*!< Least significant component of the firmware version */ - uint8_t ImageBank; /*!< Image bank for which firmware is requested */ - uint8_t Flags1; /*!< Flags1 */ - uint8_t Flags2; /*!< Flags2 */ - uint8_t Flags3; /*!< Flags3 */ - uint8_t Flags4; /*!< Flags4 */ -} __PACKEDSTRUCTEND USBPD_FWUPD_GetFwIDRspPayload_TypeDef; - -/** - * @brief USBPD Firmware Update PDFU_INITIATE Request Payload Structure definition - * - */ -typedef __PACKEDSTRUCTBEGIN -{ - uint16_t FWVersion1; /*!< Most significant component of the firmware version */ - uint16_t FWVersion2; /*!< Second-most significant component of the firmware version */ - uint16_t FWVersion3; /*!< Third-most significant component of the firmware version */ - uint16_t FWVersion4; /*!< Least significant component of the firmware version */ -} __PACKEDSTRUCTEND USBPD_FWUPD_PdfuInitReqPayload_TypeDef; - -/** - * @brief USBPD Firmware Update PDFU_INITIATE Response Payload Structure definition - * - */ -typedef __PACKEDSTRUCTBEGIN -{ - USBPD_FWUPD_Status_TypeDef Status; /*!< Status Information during Firmware Update */ - uint8_t WaitTime; /*!< Wait time */ - uint8_t MaxImageSize[3u]; /*!< Max image size */ -} __PACKEDSTRUCTEND USBPD_FWUPD_PdfuInitRspPayload_TypeDef; - -/** - * @brief USBPD Firmware Update PDFU_DATA Response Payload Structure definition - * - */ -typedef __PACKEDSTRUCTBEGIN -{ - USBPD_FWUPD_Status_TypeDef Status; /*!< Status Information during Firmware Update */ - uint8_t WaitTime; /*!< Wait time */ - uint8_t NumDataNR; /*!< Number of PDFU_DATA_NR Requests */ - uint16_t DataBlockNum; /*!< Data Block Number of the next PDFU_DATA or PDFU_DATA_NR */ -} __PACKEDSTRUCTEND USBPD_FWUPD_PdfuDataRspPayload_TypeDef; - -/** - * @brief USBPD Firmware Update PDFU_VALIDATE Response Payload Structure definition - * - */ -typedef __PACKEDSTRUCTBEGIN -{ - USBPD_FWUPD_Status_TypeDef Status; /*!< Status Information during Firmware Update */ - uint8_t WaitTime; /*!< Wait time */ - uint8_t Flags; /*!< Flags */ -} __PACKEDSTRUCTEND USBPD_FWUPD_PdfuValidateRspPayload_TypeDef; - -/** - * @brief USBPD Firmware Update PDFU_DATA_PAUSE Response Payload Structure definition - * - */ -typedef __PACKEDSTRUCTBEGIN -{ - USBPD_FWUPD_Status_TypeDef Status; /*!< Status Information during Firmware Update */ -} __PACKEDSTRUCTEND USBPD_FWUPD_PdfuDataPauseRspPayload_TypeDef; - -/** - * @brief USBPD Firmware Update VENDOR_SPECIFIC Request Payload Structure definition - * - */ -typedef __PACKEDSTRUCTBEGIN -{ - uint16_t VID; /*!< USB-IF assigned Vendor ID */ - uint8_t VendorDefined[256]; /*!< Vendor defined */ -} __PACKEDSTRUCTEND USBPD_FWUPD_VendorSpecificReqPayload_TypeDef; - -/** - * @brief USBPD Firmware Update VENDOR_SPECIFIC Response Payload Structure definition - * - */ -typedef __PACKEDSTRUCTBEGIN -{ - USBPD_FWUPD_Status_TypeDef Status; /*!< Status Information during Firmware Update */ - uint16_t VID; /*!< USB-IF assigned Vendor ID */ - uint8_t VendorDefined[255]; /*!< Vendor defined */ -} __PACKEDSTRUCTEND USBPD_FWUPD_VendorSpecificRspPayload_TypeDef; - -/** - * @brief USBPD Firmware Update Request Data Block Extended Message Structure definition - * - */ -typedef __PACKEDSTRUCTBEGIN -{ - uint8_t ProtocolVersion; /*!< Protocol Version (@ref USBPD_FWUPD_PROT_VER) */ - uint8_t MessageType; /*!< Firmware Update Message type (@ref USBPD_FWUPD_MSGTYPE) */ - uint8_t Payload[258]; /*!< Payload */ -} __PACKEDSTRUCTEND USBPD_FRQDB_TypeDef; - -#endif /* USBPDCORE_FWUPD */ - -#ifdef USBPDCORE_PPS -/** - * @brief USBPD PPS Status Data Block Extended Message Structure definition - * - */ -typedef union -{ - uint32_t d32; - struct - { - uint16_t OutputVoltageIn20mVunits; /*!< Source output voltage in 20mV units. - When set to 0xFFFF, the Source does not support this field. */ - uint8_t OutputCurrentIn50mAunits; /*!< Source output current in 50mA units. - When set to 0xFF, the Source does not support this field. */ - uint8_t RealTimeFlags; /*!< Real Time Flags, combination of @ref USBPD_CORE_DEF_REAL_TIME_FLAGS */ - } fields; -} USBPD_PPSSDB_TypeDef; -#endif /* USBPDCORE_PPS */ - -/** - * @brief USBPD Country Code Data Block Extended Message Structure definition - * - */ -typedef struct -{ - uint32_t Length; /*!< Number of country codes in the message */ - uint16_t *PtrCountryCode; /*!< Pointer of the country codes (1 to n) */ -} USBPD_CCDB_TypeDef; - -/** - * @brief USBPD Country Info Data Block Extended Message Structure definition - * - */ -typedef struct -{ - uint16_t CountryCode; /*!< 1st and 2nd character of the Alpha-2 Country Code defined by [ISO 3166] */ - uint32_t Reserved; /*!< Reserved - Shall be set to 0. */ - uint8_t PtrCountrySpecificData; /*!< Pointer on Content defined by the country authority (0 t 256 bytes). */ -} USBPD_CIDB_TypeDef; - -#endif /* USBPD_REV30_SUPPORT */ - -/** - * @} - */ - -/** @defgroup USBPD_CORE_SETTINGS_Exported_Structures USBPD CORE Settings Exported Structures - * @brief USBPD Settings Structure definition - * @{ - */ -#if defined(USBPD_REV30_SUPPORT) -typedef union { - uint16_t PD3_Support; - struct { - uint16_t PE_UnchunkSupport : 1u; /*!< Unchunked support */ - uint16_t PE_FastRoleSwapSupport : 1u; /*!< Fast role swap support (not yet implemented) */ - uint16_t Is_GetPPSStatus_Supported : 1u; /*!< Get PPS status message supported by PE */ - uint16_t Is_SrcCapaExt_Supported : 1u; /*!< Source_Capabilities_Extended message supported by PE */ - uint16_t Is_Alert_Supported : 1u; /*!< Alert message supported by PE */ - uint16_t Is_GetStatus_Supported : 1u; /*!< Get_Status message supported by PE (Is_Alert_Supported should be enabled) */ - uint16_t Is_GetManufacturerInfo_Supported : 1u; /*!< Manufacturer_Info message supported by PE */ - uint16_t Is_GetCountryCodes_Supported : 1u; /*!< Get_Country_Codes message supported by PE */ - uint16_t Is_GetCountryInfo_Supported : 1u; /*!< Get_Country_Info message supported by PE */ - uint16_t Is_SecurityRequest_Supported : 1u; /*!< Security_Response message supported by PE */ - uint16_t Is_FirmUpdateRequest_Supported : 1u; /*!< Firmware update response message supported by PE */ - uint16_t Is_SnkCapaExt_Supported : 1u; /*!< Sink_Capabilities_Extended message supported by PE */ - uint16_t reserved : 3u; /*!< Reserved bits */ - } d; -}USBPD_PD3SupportTypeDef; -#endif /* USBPD_REV30_SUPPORT */ - -typedef struct -{ - USBPD_SupportedSOP_TypeDef PE_SupportedSOP; /*!< Corresponds to the message managed by the stack and this should be set depending if you want discuss with the cable - So if VconnSupport is enabling this field must be set to - @ref USBPD_SUPPORTED_SOP_SOP | @ref USBPD_SUPPORTED_SOP_SOP1 | @ref USBPD_SUPPORTED_SOP_SOP2 - else - @ref USBPD_SUPPORTED_SOP_SOP - */ - USBPD_SpecRev_TypeDef PE_SpecRevision : 2u; /*!< Spec revision value based on @ref USBPD_SpecRev_TypeDef */ - USBPD_PortPowerRole_TypeDef PE_DefaultRole: 1u; /*!< Default port role based on @ref USBPD_PortPowerRole_TypeDef */ - uint32_t PE_RoleSwap : 1u; /*!< If enabled, allows the port to have DRP behavior */ - uint32_t _empty1 : 1u; /*!< Reserved bit */ - uint32_t PE_VDMSupport : 1u; /*!< Support VDM: If not enabled any VDM message received is replied "not supported" */ - uint32_t PE_PingSupport : 1u; /*!< support Ping (only for PD3.0): If enabled allows DPM to send ping message */ - uint32_t PE_CapscounterSupport : 1u; /*!< If enabled after an amount of message source capabilities not replied, the stack stop the message send.*/ - uint32_t PE_RespondsToDiscovSOP : 1u; /*!< Can respond successfully to a Discover Identity */ - uint32_t PE_AttemptsDiscovSOP : 1u; /*!< Can send a Discover Identity */ - uint32_t CAD_TryFeature : 2u; /*!< Not yet implemented */ - uint32_t CAD_AccesorySupport : 1u; /*!< Not yet implemented */ - uint32_t CAD_RoleToggle : 1u; /*!< If enabled allows the detection state machine switch Rp/Rd means toggle the presented role between source and sink */ - CAD_RP_Source_Current_Adv_Typedef CAD_DefaultResistor : 2u; /*!< Default RP resistor based on @ref CAD_RP_Source_Current_Adv_Typedef */ - uint32_t CAD_SNKToggleTime : 8u; /*!< Sink toggle time in ms */ - uint32_t CAD_SRCToggleTime : 8u; /*!< Source toggle time in ms */ -#if defined(USBPD_REV30_SUPPORT) - USBPD_PD3SupportTypeDef PE_PD3_Support; /*!< PD3 structure support flags based on @ref USBPD_PD3SupportTypeDef */ -#else - uint16_t reserved : 16u; /*!< Reserved bits */ -#endif /* USBPD_REV30_SUPPORT */ -} USBPD_SettingsTypeDef; - -/** - * @} - */ - -/** @defgroup USBPD_CORE_PARAMS_Exported_Structures USBPD CORE Params Exported Structures - * @brief USBPD Params Structure definition - * @{ - */ -typedef struct -{ - - USBPD_SpecRev_TypeDef PE_SpecRevision : 2u; /*!< PE Specification revision */ - USBPD_PortPowerRole_TypeDef PE_PowerRole : 1u; /*!< PE Power role */ - USBPD_PortDataRole_TypeDef PE_DataRole : 1u; /*!< PE Data role */ - uint32_t PE_SwapOngoing : 1u; /*!< Power role swap ongoing flag */ - USBPD_VDMVersion_TypeDef VDM_Version : 1u; /*!< VDM version */ - CCxPin_TypeDef ActiveCCIs : 2u; /*!< Active CC line based on @ref CCxPin_TypeDef */ - USBPD_POWER_StateTypedef PE_Power : 3u; /*!< Power status based on @ref USBPD_POWER_StateTypedef */ - uint32_t DPM_Initialized : 1u; /*!< DPM initialized flag */ - uint32_t PE_IsConnected : 1u; /*!< USB-PD PE stack is connected to CC line */ - CCxPin_TypeDef VconnCCIs : 2u; /*!< VConn CC line based on @ref CCxPin_TypeDef */ - uint32_t VconnStatus : 1u; /*!< VConnStatus USBP_TRUE = vconn on USBPD_FALSE = vconn off */ - CAD_RP_Source_Current_Adv_Typedef RpResistor : 2u; /*!< RpResistor presented */ -#if defined(USBPD_REV30_SUPPORT) && defined(USBPDCORE_UNCHUNCKED_MODE) - uint32_t PE_UnchunkSupport: 1u; /*!< Unchunked support */ - uint32_t Reserved : 13u; /*!< Reserved bits */ -#else - uint32_t Reserved : 14u; /*!< Reserved bits */ -#endif /* USBPD_REV30_SUPPORT && USBPDCORE_UNCHUNCKED_MODE */ -} USBPD_ParamsTypeDef; - -/** - * @} - */ - -/** - * @} - */ - -/* Exported variables --------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBPD_DEF_H_ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_tcpm.h b/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_tcpm.h deleted file mode 100644 index a0019b9..0000000 --- a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_tcpm.h +++ /dev/null @@ -1,309 +0,0 @@ -/** - ****************************************************************************** - * @file usbpd_tcpm.h - * @author MCD Application Team - * @brief Header file containing functions prototypes of USBPD TCPM library. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBPD_TCPM_H -#define __USBPD_TCPM_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#if defined(USBPDCORE_TCPM_SUPPORT) - -#include "string.h" -#include "usbpd_cad.h" -#include "usbpd_def.h" -#include "tcpc.h" - -/** @addtogroup STM32_USBPD_LIBRARY - * @{ - */ - -/** @addtogroup USBPD_CORE - * @{ - */ - -/** @addtogroup USBPD_CORE_TCPM - * @{ - */ - -/* Exported constants --------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/** @defgroup USBPD_CORE_TCPM_Exported_TypesDefinitions USBPD CORE TCPM Exported Types Definitions - * @{ - */ -/** - * @brief CallBacks exposed by the @ref USBPD_CORE_TCPM to the @ref USBPD_CORE_PRL - */ -typedef struct -{ - /** - * @brief Reports that a message has been received on a specified port. - * @param hport: The handle of the port - * @param Type: The type of the message received - * @retval None - * @note Received data are stored inside hport->pRxBuffPtr - */ - void (*USBPD_TCPM_MessageReceived)(uint8_t hport, USBPD_SOPType_TypeDef Type); - - /** - * @brief Reports to the PRL that a Reset received from channel. - * @param hport: The handle of the port - * @param Type: The type of reset performed - * @retval None - */ - void (*USBPD_TCPM_ResetIndication)(uint8_t hport, USBPD_SOPType_TypeDef Type); - - /** - * @brief Reports to the PRL that a Reset operation has been completed. - * @param hport: The handle of the port - * @param Type: The type of reset performed - * @retval None - */ - void (*USBPD_TCPM_ResetCompleted)(uint8_t hport, USBPD_SOPType_TypeDef Type); - - /** - * @brief Reports to the PRL that a Bist operation has been completed. - * @param hport: The handle of the port - * @param Type: The type of Bist performed - * @retval None - */ - void (*USBPD_TCPM_BistCompleted)(uint8_t hport, USBPD_BISTMsg_TypeDef bistmode); - - /** - * @brief USB-PD message sent callback from TCPC - * @param PortNum port number value - * @param Status Status of the transmission - * @retval None - */ - void (*USBPD_TCPM_MessageReceivedTC)(uint8_t PortNum, uint32_t status); - -} USBPD_PHY_Callbacks; - -/** - * @brief Initialization structure exposed by the @ref USBPD_CORE_TCPM to the @ref USBPD_CORE_PRL - */ -typedef struct -{ - uint8_t *pRxBuffer; /*!< Pointer to @ref USBPD_CORE_PRL RX Buffer for the current port */ - const USBPD_PHY_Callbacks *pCallbacks; /*!< TCPM Callbacks */ -} USBPD_TCPM_HandleTypeDef; -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup USBPD_CORE_TCPM_Exported_Functions - * @{ - */ - -/** @defgroup USBPD_CORE_TCPM_Exported_Functions_Grp2 USBPD CORE TCPM Exported Functions to PRL - * @{ - */ -/** - * @brief Initialize TCPC devices - * @param PortNum Number of the port - * @param pCallbacks TCPM callbacks - * @param pRxBuffer Pointer on the RX buffer - * @param PowerRole Power role can be one of the following values: - * @arg @ref USBPD_PORTPOWERROLE_SNK - * @arg @ref USBPD_PORTPOWERROLE_SRC - * @param SupportedSOP Supported SOP - * @retval HAL status - */ -USBPD_StatusTypeDef USBPD_PHY_Init(uint8_t PortNum, const USBPD_PHY_Callbacks *pCallbacks, uint8_t *pRxBuffer, USBPD_PortPowerRole_TypeDef PowerRole, uint32_t SupportedSOP); - -/** - * @brief Reset the PHY of a specified port. - * @param PortNum Number of the port. - * @retval None - */ -void USBPD_PHY_Reset(uint8_t PortNum); - -/** - * @brief function to set the supported SOP - * @param PortNum Number of the port. - * @param SOPSupported List of the supported SOP - * @retval None. - */ -void USBPD_PHY_SOPSupported(uint8_t PortNum,uint32_t SOPSupported); - -/** - * @brief De-initialize TCPC devices - * @param PortNum Number of the port - * @retval None - */ -void USBPD_TCPM_DeInit(uint8_t PortNum); - -/** - * @brief Get CC line for PD connection - * @param PortNum Number of the port - * @param CC1_Level Pointer of status of the CC1 line - * @param CC2_Level Pointer of status of the CC2 line - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_TCPM_get_cc(uint32_t PortNum, uint32_t *CC1_Level, uint32_t *CC2_Level); - -/** - * @brief Set the polarity of the CC lines - * @param PortNum Number of the port - * @param Polarity Polarity - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_TCPM_set_polarity(uint32_t PortNum, uint32_t Polarity); - -/** - * @brief Set power and data role et PD message header - * @param PortNum Number of the port - * @param PowerRole Power role - * @param DataRole Data role - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_TCPM_set_msg_header(uint32_t PortNum, USBPD_PortPowerRole_TypeDef PowerRole, USBPD_PortDataRole_TypeDef DataRole); - -/** - * @brief Enable or disable PD reception - * @param PortNum Number of the port - * @param Pull Value of the CC pin to configure based on @ref TCPC_CC_Pull_TypeDef - * @param State Activation or deactivation of RX - * @param SupportedSOP Supported SOP by PRL - * @param HardReset Hard reset status based on @ref TCPC_hard_reset - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_TCPM_set_rx_state(uint32_t PortNum, TCPC_CC_Pull_TypeDef Pull, USBPD_FunctionalState State, uint32_t SupportedSOP, TCPC_hard_reset HardReset); - -/** - * @brief Retrieve the PD message - * @param PortNum Number of the port - * @param Payload Pointer on the payload - * @param Type Pointer on the message type - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_TCPM_get_message(uint32_t PortNum, uint8_t *Payload, uint8_t *Type); - -/** - * @brief Transmit the PD message - * @param PortNum Number of the port - * @param Type Message type - * @param pData Pointer on the data message - * @param RetryNumber Number of retry - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_TCPM_transmit(uint32_t PortNum, USBPD_SOPType_TypeDef Type, const uint8_t *pData, uint32_t RetryNumber); - -/** - * @brief Send bist pattern. - * @param PortNum Number of the port - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_PHY_Send_BIST_Pattern(uint32_t PortNum); - -/** - * @brief Request a Reset on a specified port. - * @param PortNum Number of the port - * @param Type The type of reset (hard or cable reset). - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_PHY_ResetRequest(uint8_t PortNum, USBPD_SOPType_TypeDef Type); - -/** - * @brief Request TCPC to enter a specific BIST test mode. - * @param PortNum Number of the port - * @param State Enable BIST carrier mode 2 - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_TCPM_Send_BIST_Pattern(uint8_t PortNum, USBPD_FunctionalState State); - -/** - * @brief function to set the SinkTxNg - * @param PortNum Number of the port. - * @retval none. - */ -void USBPD_PHY_SetResistor_SinkTxNG(uint8_t PortNum); - -/** - * @brief function to set the SinkTxOK - * @param PortNum Number of the port. - * @retval none. - */ -void USBPD_PHY_SetResistor_SinkTxOK(uint8_t PortNum); - -/** - * @brief function to check if SinkTxOK - * @param PortNum Number of the port. - * @retval USBPD status based on @ref USBPD_StatusTypeDef - */ -USBPD_StatusTypeDef USBPD_PHY_IsResistor_SinkTxOk(uint8_t PortNum); - -/** - * @brief Trigger in Fast role swap signalling - * @param PortNum Number of the port. - * @retval None - */ -void USBPD_PHY_FastRoleSwapSignalling(uint8_t PortNum); - -/** - * @brief Enable RX - * @param PortNum Number of the port. - * @retval None - */ -void USBPD_PHY_EnableRX(uint8_t PortNum); - -/** - * @brief Disable RX - * @param PortNum Number of the port. - * @retval None - */ -void USBPD_PHY_DisableRX(uint8_t PortNum); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* USBPDCORE_TCPM_SUPPORT */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __USBPD_TCPM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_trace.h b/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_trace.h deleted file mode 100644 index 9af3652..0000000 --- a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_trace.h +++ /dev/null @@ -1,95 +0,0 @@ -/** - ****************************************************************************** - * @file usbpd_trace.h - * @author MCD Application Team - * @brief This file contains the headers of usbpd_cad.h for Cable Attach-Detach - * controls. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -#ifndef __USBPD_TRACE_H_ -#define __USBPD_TRACE_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -/** @addtogroup STM32_USBPD_LIBRARY - * @{ - */ - -/** @addtogroup USBPD_CORE - * @{ - */ - -/** @addtogroup USBPD_CORE_TRACE - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported define -----------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported variables --------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup USBPD_CORE_TRACE_Exported_Functions USBPD CORE TRACE Exported Functions - * @{ - */ -/** - * @brief Initialize the TRACE module - * @retval None - */ -void USBPD_TRACE_Init(void); - -/** - * @brief Add information in debug trace buffer - * @param Type Trace Type based on @ref TRACE_EVENT - * @param PortNum Port number value - * @param Sop SOP type - * @param Ptr Pointer on the data to send - * @param Size Size of the data to send - * @retval None. - */ -void USBPD_TRACE_Add(TRACE_EVENT Type, uint8_t PortNum, uint8_t Sop, uint8_t *Ptr, uint32_t Size); - -/** - * @brief Process to send the data - * @retval None. - */ -uint32_t USBPD_TRACE_TX_Process(void); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBPD_CAD_H_ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Core/lib/USBPDCORE_PD3_FULL_CM4_wc32.a b/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Core/lib/USBPDCORE_PD3_FULL_CM4_wc32.a deleted file mode 100644 index 6b9b1b7..0000000 Binary files a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Core/lib/USBPDCORE_PD3_FULL_CM4_wc32.a and /dev/null differ diff --git a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Core/src/usbpd_trace.c b/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Core/src/usbpd_trace.c deleted file mode 100644 index c6658bf..0000000 --- a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Core/src/usbpd_trace.c +++ /dev/null @@ -1,204 +0,0 @@ -/** - ****************************************************************************** - * @file usbpd_trace.c - * @author MCD Application Team - * @brief This file contains trace control functions. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#if defined(_TRACE) -#define USBPD_TRACE_C - -#include "stdint.h" -#include "usbpd_def.h" -#include "usbpd_core.h" -#include "usbpd_trace.h" -#ifdef _TRACE -#include "tracer_emb.h" -#endif - -/** @addtogroup STM32_USBPD_LIBRARY - * @{ - */ - -/** @addtogroup USBPD_CORE - * @{ - */ - -/** @addtogroup USBPD_CORE_TRACE - * @{ - */ - -/* Private enums -------------------------------------------------------------*/ -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup USBPD_CORE_TRACE_Private_Defines USBPD TRACE Private Defines - * @{ - */ - -#define TRACE_SIZE_HEADER_TRACE 9u /* Type + Time x 2 + PortNum + Sop + Size */ - -#define TRACE_PORT_BIT_POSITION 5u /* Bit position of port number in TAG id */ - -#define TLV_SOF (uint8_t)0xFDu -#define TLV_EOF (uint8_t)0xA5u -#define TLV_SIZE_MAX 256u -#define TLV_HEADER_SIZE 3u /* Size of TLV header (TAG(1) + LENGTH(2) */ -#define TLV_SOF_SIZE 4u /* TLV_SOF * 4 */ -#define TLV_EOF_SIZE 4u /* TLV_EOF * 4 */ - -#define DEBUG_STACK_MESSAGE 0x12u -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup USBPD_CORE_TRACE_Private_Macros USBPD TRACE Private Macros - * @{ - */ -#define __TRACE_SET_TAG_ID(_PORT_, _TAG_) (((_PORT_) << TRACE_PORT_BIT_POSITION) | (_TAG_)) - -#define TRACER_EMB_WRITE_DATA(_POSITION_,_DATA_) TRACER_EMB_WriteData((_POSITION_),(_DATA_));\ - (_POSITION_) = ((_POSITION_) + 1u); - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup USBPD_CORE_TRACE_Private_Variables USBPD TRACE Private Variables - * @{ - */ -extern uint32_t HAL_GetTick(void); - -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - - -/** @addtogroup USBPD_CORE_TRACE_Exported_Functions - * @{ - */ -void USBPD_TRACE_Init(void) -{ - /* initialize tracer module */ - TRACER_EMB_Init(); - - /* Initialize PE trace */ - USBPD_PE_SetTrace(USBPD_TRACE_Add, 3u); -} - -void USBPD_TRACE_Add(TRACE_EVENT Type, uint8_t PortNum, uint8_t Sop, uint8_t *Ptr, uint32_t Size) -{ - uint32_t _time; - int32_t _writepos; - uint16_t _writepos2; - uint8_t *data_to_write; - uint32_t index; - uint32_t total_size; - -#if !defined(_TRACE) - /* Do not send debug traces */ - return; -#endif - - TRACER_EMB_Lock(); - - /* Data are encapsulate inside a TLV string*/ - /* Allocate buffer Size */ - total_size = Size + TRACE_SIZE_HEADER_TRACE + TLV_HEADER_SIZE + TLV_SOF_SIZE + TLV_EOF_SIZE; - _writepos = TRACER_EMB_AllocateBufer(total_size); - - /* Check allocation */ - if (_writepos != -1) - { - _writepos2 = (uint16_t)_writepos; - data_to_write = Ptr; - - /* Copy SOF bytes */ - for(index = 0u; index < TLV_SOF_SIZE; index++) - { - TRACER_EMB_WRITE_DATA(_writepos2, TLV_SOF); - } - /* Copy the TAG */ - TRACER_EMB_WRITE_DATA(_writepos2, __TRACE_SET_TAG_ID((PortNum + 1u), DEBUG_STACK_MESSAGE)); - /* Copy the LENGTH */ - TRACER_EMB_WRITE_DATA(_writepos2, (uint8_t)((total_size - TLV_HEADER_SIZE - TLV_SOF_SIZE - TLV_EOF_SIZE) >> 8u)); - TRACER_EMB_WRITE_DATA(_writepos2, (uint8_t)(total_size - TLV_HEADER_SIZE - TLV_SOF_SIZE - TLV_EOF_SIZE)); - TRACER_EMB_WRITE_DATA(_writepos2, (uint8_t)Type); - - _time = HAL_GetTick(); - - TRACER_EMB_WRITE_DATA(_writepos2, (uint8_t)_time); - TRACER_EMB_WRITE_DATA(_writepos2, (uint8_t)(_time >> 8u)); - TRACER_EMB_WRITE_DATA(_writepos2, (uint8_t)(_time >> 16u)); - TRACER_EMB_WRITE_DATA(_writepos2, (uint8_t)(_time >> 24u)); - - TRACER_EMB_WRITE_DATA(_writepos2, PortNum); - TRACER_EMB_WRITE_DATA(_writepos2, Sop); - - TRACER_EMB_WRITE_DATA(_writepos2, (uint8_t)(Size >> 8u)); - TRACER_EMB_WRITE_DATA(_writepos2, (uint8_t)Size); - - /* initialize the Ptr for Read/Write */ - for (index = 0u; index < Size; index++) - { - TRACER_EMB_WRITE_DATA(_writepos2, data_to_write[index]); - } - - /* Copy EOF bytes */ - for(index = 0u; index < TLV_EOF_SIZE; index++) - { - TRACER_EMB_WRITE_DATA(_writepos2, TLV_EOF); - } - } - - TRACER_EMB_UnLock(); -} - -uint32_t USBPD_TRACE_TX_Process(void) -{ - return TRACER_EMB_TX_Process(); -} - -/** - * @} - */ - -/** @defgroup USBPD_CORE_TRACE_Private_Functions USBPD TRACE Private Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* _TRACE */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_cad_hw_if.h b/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_cad_hw_if.h deleted file mode 100644 index 7d4ddfe..0000000 --- a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_cad_hw_if.h +++ /dev/null @@ -1,80 +0,0 @@ -/** - ****************************************************************************** - * @file usbpd_cad_hw_if.h - * @author MCD Application Team - * @brief This file contains the headers of usbpd_cad.h for Cable Attach-Detach - * controls. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -#ifndef __USBPD_CAD_HW_IF_H_ -#define __USBPD_CAD_HW_IF_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ - -/** @addtogroup STM32_USBPD_LIBRARY - * @{ - */ - -/** @addtogroup USBPD_DEVICE - * @{ - */ - -/** @addtogroup USBPD_DEVICE_CAD_HW_IF - * @{ - */ - - -/* Exported types ------------------------------------------------------------*/ -/* Exported define -----------------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported variables --------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup USBPD_DEVICE_CAD_HW_IF_Exported_Functions - * @{ - */ -void CAD_Init(uint8_t PortNum, USBPD_SettingsTypeDef *Settings, USBPD_ParamsTypeDef *Params, void (*PtrWakeUp)(void)); -uint32_t CAD_StateMachine(uint8_t PortNum, USBPD_CAD_EVENT *Event, CCxPin_TypeDef *CCXX); -void CAD_Enter_ErrorRecovery(uint8_t PortNum); -uint32_t CAD_Set_ResistorRp(uint8_t PortNum, CAD_RP_Source_Current_Adv_Typedef RpValue); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBPD_CAD_HW_IF_H_ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_hw.h b/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_hw.h deleted file mode 100644 index 2ddde65..0000000 --- a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_hw.h +++ /dev/null @@ -1,36 +0,0 @@ -/** - ****************************************************************************** - * @file usbpd_hw.h - * @author MCD Application Team - * @brief This file contains interface hw control. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ - -#ifndef USBPD_HW_H -#define USBPD_HW_H -/* Includes ------------------------------------------------------------------*/ -/* Private typedef -----------------------------------------------------------*/ -/* Variable containing ADC conversions results */ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -UCPD_TypeDef *USBPD_HW_GetUSPDInstance(uint8_t PortNum); -DMA_Channel_TypeDef *USBPD_HW_Init_DMARxInstance(uint8_t PortNum); -void USBPD_HW_DeInit_DMARxInstance(uint8_t PortNum); -DMA_Channel_TypeDef *USBPD_HW_Init_DMATxInstance(uint8_t PortNum); -void USBPD_HW_DeInit_DMATxInstance(uint8_t PortNum); -uint32_t USBPD_HW_GetRpResistorValue(uint8_t Portnum); -void USBPD_HW_SetFRSSignalling(uint8_t Portnum, uint8_t cc); -#endif /* USBPD_BSP_HW_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_hw_if.h b/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_hw_if.h deleted file mode 100644 index 0bb10a3..0000000 --- a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_hw_if.h +++ /dev/null @@ -1,377 +0,0 @@ -/** - ****************************************************************************** - * @file usbpd_hw_if.h - * @author MCD Application Team - * @brief This file contains the headers of usbpd_hw_if.h for USB-PD Hardware - Interface layer. This file is specific for each device. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ - -#ifndef __USBPD_HW_IF_H_ -#define __USBPD_HW_IF_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbpd_def.h" -#include "usbpd_devices_conf.h" - -/** @addtogroup STM32_USBPD_LIBRARY - * @{ - */ - -/** @addtogroup USBPD_DEVICE - * @{ - */ - -/** @addtogroup USBPD_DEVICE_HW_IF - * @{ - */ - -/* Exported typedef ----------------------------------------------------------*/ -/** @defgroup USBPD_DEVICE_DEVICE_HW_IF_Exported_Types USBPD DEVICE HW_IF Exported Types - * @{ - */ - -/** - * @brief Enum used to get the status of decoding - */ -typedef enum -{ - USBPD_PHY_RX_STATUS_NONE, - USBPD_PHY_RX_STATUS_OK, - USBPD_PHY_RX_STATUS_SOP_DETECTING, - USBPD_PHY_RX_STATUS_DATA, - USBPD_PHY_RX_STATUS_MESSAGE_READY, - USBPD_PHY_RX_STATUS_ERROR, - USBPD_PHY_RX_STATUS_ERROR_UNSUPPORTED_SOP, - USBPD_PHY_RX_STATUS_ERROR_INVALID_SOP, - USBPD_PHY_RX_STATUS_ERROR_INVALID_SYMBOL, - USBPD_PHY_RX_STATUS_ERROR_EOP_NOT_FOUND, - USBPD_PHY_RX_STATUS_ERROR_CRC_FAILED, -} -USBPD_PHY_RX_Status_TypeDef; - -/** - * @brief CallBacks exposed by the HW_IF to the PHY - */ -typedef struct -{ - /** - * @brief The message transfer has been completed - * @param PortNum The current port number - * @retval None - */ - void (*USBPD_HW_IF_TxCompleted)(uint8_t PortNum); - /** - * @brief Bist data sent callback from PHY_HW_IF - * @param PortNum Index of current used port - * @param bistmode: Bist mode - * @retval None - */ - void (*USBPD_HW_IF_BistCompleted)(uint8_t PortNum, USBPD_BISTMsg_TypeDef bistmode); - /** - * @brief A new message is incoming, need to reset the status. - * @param PortNum The current port number - * @retval The status of the decoding process - */ - USBPD_PHY_RX_Status_TypeDef(*USBPD_HW_IF_RX_Reset)(uint8_t PortNum); - - /** - * @brief The reception phase of an hard reset is completed notify it. - * @param PortNum The current port number - * @retval None - */ - void (*USBPD_HW_IF_RX_ResetIndication)(uint8_t PortNum); - - /** - * @brief The reception phase of the current message is completed and notify it. - * @param PortNum The current port number - * @retval None - */ - void (*USBPD_HW_IF_RX_Completed)(uint8_t PortNum, uint32_t MsgType, uint16_t RxPaySize); - - /** - * @brief The emission of HRST has been completed. - * @param PortNum The current port number - * @retval None - */ - void (*USBPD_HW_IF_TX_HardResetCompleted)(uint8_t PortNum, USBPD_SOPType_TypeDef Type); - -} USBPD_HW_IF_Callbacks; - -/** @defgroup USBPD_PORT_HandleTypeDef USB PD handle Structure definition for USBPD_PHY_HW_IF - * @brief USBPD PORT handle Structure definition - * @{ - */ -typedef struct -{ - UCPD_TypeDef *husbpd; /*!< UCPD Handle parameters */ - DMA_Channel_TypeDef *hdmatx; /*!< Tx DMA Handle parameters */ - DMA_Channel_TypeDef *hdmarx; /*!< Rx DMA Handle parameters */ - - USBPD_SettingsTypeDef *settings; - USBPD_ParamsTypeDef *params; - USBPD_HW_IF_Callbacks cbs; /*!< USBPD_PHY_HW_IF callbacks */ - - __IO uint32_t PIN_CC1; /*!< CC1 detection state */ - __IO uint32_t PIN_CC2; /*!< CC2 detection state */ - - void (*USBPD_CAD_WakeUp)(void); /*!< function used to wakeup cad task */ - - uint8_t *ptr_RxBuff; /*!< Pointer to Raw Rx transfer Buffer */ - - CCxPin_TypeDef CCx; /*!< CC pin used for communication */ -} USBPD_PORT_HandleTypeDef; - -extern USBPD_PORT_HandleTypeDef Ports[USBPD_PORT_COUNT]; - -/** - * @} - */ - -/** - * @} - */ - -/* Exported define -----------------------------------------------------------*/ - -/** @defgroup USBPD_DEVICE_DEVICE_HW_IF_Exported_Defines USBPD DEVICE HW_IF Exported Defines - * @{ - */ - -#define SIZE_MAX_PD_TRANSACTION_CHUNK 30u -#define SIZE_MAX_PD_TRANSACTION_UNCHUNK (260u + 4u) - -/** - * @} - */ - -/* Exported variables --------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup USBPD_DEVICE_DEVICE_HW_IF_Exported_Functions USBPD DEVICE HW_IF Exported Functions - * @{ - */ - -/** - * @brief Enable the interrupt for the reception. - * @param PortNum The handle of the port. - * @retval None - */ -void USBPDM1_RX_EnableInterrupt(uint8_t PortNum); - -/** - * @brief stop bist carrier mode 2. - * @param PortNum The port handle. - * @retval None - */ -void USBPD_HW_IF_StopBISTMode2(uint8_t PortNum); - -/** - * @brief Initialize specific peripheral for the APP. - * @retval None - */ -void USBPD_HW_IF_GlobalHwInit(void); - -/** - * @brief Send a Buffer . - * @note The data will be converted in bmc and send through the line - * @param PortNum The port handle. - * @param Type SOP Message Type based on @ref USBPD_SOPType_TypeDef - * @param pBuffer Data buffer to be transmitted - * @param Bitsize The number of bits to be transmitted - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_HW_IF_SendBuffer(uint8_t PortNum, USBPD_SOPType_TypeDef Type, uint8_t *pBuffer, uint32_t Bitsize); - -#if defined(_SRC) || defined(_DRP) -/** - * @brief Enable the VBUS on a specified port. - * @param PortNum The port handle. - * @param State ENABLE or DISABLE. - * @param Cc CC pin based on @ref CCxPin_TypeDef - * @param VconnState VCONN State activation - * @param role The role of the port. - * @retval USBPD status - */ -USBPD_StatusTypeDef HW_IF_PWR_Enable(uint8_t PortNum, USBPD_FunctionalState State, CCxPin_TypeDef Cc, uint32_t VconnState, USBPD_PortPowerRole_TypeDef role); -#endif /* _SRC || _DRP */ - -/** - * @brief Retrieve the VBUS status for a specified port. - * @param PortNum The port handle. - * @retval FunctionalState - */ -USBPD_FunctionalState HW_IF_PWR_VBUSIsEnabled(uint8_t PortNum); - -/** - * @brief Set the VBUS voltage level on a specified port. - * @param PortNum The port handle. - * @param Voltage voltage value to be set. - * @retval USBPD status - */ -USBPD_StatusTypeDef HW_IF_PWR_SetVoltage(uint8_t PortNum, uint16_t Voltage); - -/** - * @brief Get the voltage level on a specified port. - * @param PortNum The port handle. - * @retval The voltage value - */ -uint16_t HW_IF_PWR_GetVoltage(uint8_t PortNum); - -/** - * @brief Get the current level on a specified port. - * @param PortNum The port handle. - * @retval The current value - */ -int16_t HW_IF_PWR_GetCurrent(uint8_t PortNum); - -/** - * @brief Connect the Rp resitors on the CC lines - * @param PortNum The port handle. - * @retval none - */ -void USBPDM1_AssertRp(uint8_t PortNum); - -/** - * @brief Disconnect the Rp resitors on the CC lines - * @param PortNum The port handle. - * @retval none - */ -void USBPDM1_DeAssertRp(uint8_t PortNum); - -/** - * @brief Connect the Rd resitors on the CC lines - * @param PortNum The port handle. - * @retval none - */ -void USBPDM1_AssertRd(uint8_t PortNum); - -/** - * @brief Disconnect the Rd resitors on the CC lines - * @param PortNum The port handle. - * @retval none - */ -void USBPDM1_DeAssertRd(uint8_t PortNum); - -/** - * @brief Set the CCx pin. - * @param PortNum The port handle. - * @param cc Specify the ccx to be selected. - * @retval None - */ -void USBPDM1_Set_CC(uint8_t PortNum, CCxPin_TypeDef cc); - -/** - * @brief Sends the BIST pattern - * @param PortNum The port handle. - * @retval none - */ -void USBPD_HW_IF_Send_BIST_Pattern(uint8_t PortNum); - -/** - * @brief Sends a detachemnt signal. - * @param PortNum The port handle. - * @retval none - */ -void HW_SignalDetachment(uint8_t PortNum); - -/** - * @brief Sends an Attachement signal. - * @param PortNum The port handle. - * @param cc the PD pin. - * @retval none - */ -void HW_SignalAttachement(uint8_t PortNum, CCxPin_TypeDef cc); - -/** - * @brief Set SinkTxNG resistor. - * @param PortNum The port handle. - * @retval none - */ -void USBPD_HW_IF_SetResistor_SinkTxNG(uint8_t PortNum); - -/** - * @brief Set SinkTxOk resistor. - * @param PortNum The port handle. - * @retval none - */ -void USBPD_HW_IF_SetResistor_SinkTxOK(uint8_t PortNum); - -/** - * @brief Is SinkTxOk resistor. - * @param PortNum The port handle. - * @retval TRUE FALSE - */ -uint8_t USBPD_HW_IF_IsResistor_SinkTxOk(uint8_t PortNum); - -/** - * @brief send a Fast Role swap signalling. - * @param PortNum The port handle. - * @retval None - */ -void USBPD_HW_IF_FastRoleSwapSignalling(uint8_t PortNum); - -/** - * @brief enter in error recovery state. - * @param PortNum The port handle. - * @retval None - */ -void USBPDM1_EnterErrorRecovery(uint8_t PortNum); - - -void USBPD_PORT0_IRQHandler(void); -void USBPD_PORT1_IRQHandler(void); - -/** - * @brief Enable RX - * @param PortNum The port handle. - * @retval None - */ -void USBPD_HW_IF_EnableRX(uint8_t PortNum); - -/** - * @brief Disable RX - * @param PortNum The port handle. - * @retval None - */ -void USBPD_HW_IF_DisableRX(uint8_t PortNum); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBPD_HW_IF_H_ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_phy.h b/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_phy.h deleted file mode 100644 index 26a06e5..0000000 --- a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_phy.h +++ /dev/null @@ -1,146 +0,0 @@ -/** - ****************************************************************************** - * @file usbpd_phy.h - * @author MCD Application Team - * @brief This file contains the headers of usbpd_phy.h. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ - -#ifndef __USBPD_PHY_H_ -#define __USBPD_PHY_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ - -/** @addtogroup STM32_USBPD_LIBRARY - * @{ - */ - -/** @addtogroup USBPD_DEVICE - * @{ - */ - -/** @addtogroup USBPD_DEVICE_PHY - * @{ - */ - -/* Exported typedef ----------------------------------------------------------*/ -/** @defgroup USBPD_DEVICE_PHY_Exported_TypeDef USBPD DEVICE PHY Exported TypeDef - * @{ - */ -/** - * @brief CallBacks exposed by the @ref USBPD_DEVICE_PHY to the USBPD_CORE_PRL - */ -typedef struct -{ - /** - * @brief Reports that a message has been received on a specified port. - * @note Received data are stored inside PortNum->pRxBuffPtr - * function called in the interrupt context - * @param PortNum The handle of the port - * @param Type The type of the message received @ref USBPD_SOPType_TypeDef - * @retval None - */ - void (*USBPD_PHY_MessageReceived)(uint8_t PortNum, USBPD_SOPType_TypeDef Type); - - /** - * @brief Reports to the PRL that a Reset received from channel. - * @param PortNum The handle of the port - * @param Type The type of reset performed @ref USBPD_SOPTYPE_HARD_RESET or @ref USBPD_SOPTYPE_CABLE_RESET - * @retval None - */ - void (*USBPD_PHY_ResetIndication)(uint8_t PortNum, USBPD_SOPType_TypeDef Type); - - /** - * @brief Reports to the PRL that a Reset operation has been completed. - * @param PortNum The handle of the port - * @param Type The type of reset performed @ref USBPD_SOPTYPE_HARD_RESET or @ref USBPD_SOPTYPE_CABLE_RESET - * @retval None - */ - void (*USBPD_PHY_ResetCompleted)(uint8_t PortNum, USBPD_SOPType_TypeDef Type); - - /** - * @brief Reports to the PRL that a Bist operation has been completed. - * @param PortNum The handle of the port - * @param Type The type of Bist performed @ref USBPD_BISTMsg_TypeDef - * @retval None - */ - void (*USBPD_PHY_BistCompleted)(uint8_t PortNum, USBPD_BISTMsg_TypeDef bistmode); - - /** - * @brief Reports to the PRL that a tx operation has been completed. - * @param PortNum: The handle of the port - * @retval None - */ - void (*USBPD_PHY_TxCompleted)(uint8_t PortNum); - -} USBPD_PHY_Callbacks; - -/** - * @} - */ - -/* Exported define -----------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported variables --------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup USBPD_DEVICE_PHY_Exported_Functions - * @{ - */ -USBPD_StatusTypeDef USBPD_PHY_Init(uint8_t PortNum, const USBPD_PHY_Callbacks *cbs, uint8_t *pRxBuffer, USBPD_PortPowerRole_TypeDef role, uint32_t SupportedSOP); -void USBPD_PHY_Reset(uint8_t PortNum); -uint16_t USBPD_PHY_GetRetryTimerValue(uint8_t PortNum); - -USBPD_StatusTypeDef USBPD_PHY_ResetRequest(uint8_t PortNum, USBPD_SOPType_TypeDef Type); -USBPD_StatusTypeDef USBPD_PHY_SendMessage(uint8_t PortNum, USBPD_SOPType_TypeDef Type, uint8_t *pBuffer, uint16_t Size); -USBPD_StatusTypeDef USBPD_PHY_Send_BIST_Pattern(uint8_t PortNum); -USBPD_StatusTypeDef USBPD_PHY_ExitTransmit(uint8_t PortNum, USBPD_SOPType_TypeDef BistType); -void USBPD_PHY_SetResistor_SinkTxNG(uint8_t PortNum); -void USBPD_PHY_SetResistor_SinkTxOK(uint8_t PortNum); -uint8_t USBPD_PHY_IsResistor_SinkTxOk(uint8_t PortNum); -void USBPD_PHY_FastRoleSwapSignalling(uint8_t PortNum); -void USBPD_PHY_SOPSupported(uint8_t PortNum, uint32_t SOPSupported); - -void USBPD_PHY_EnableRX(uint8_t PortNum); -void USBPD_PHY_DisableRX(uint8_t PortNum); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBPD_PHY_H_ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_timersserver.h b/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_timersserver.h deleted file mode 100644 index 4f25efc..0000000 --- a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_timersserver.h +++ /dev/null @@ -1,80 +0,0 @@ -/** - ****************************************************************************** - * @file usbpd_timersserver.h - * @author MCD Application Team - * @brief This file contains the headers of usbpd_timerserver.h. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * Redistribution and use in source and binary forms, with or without - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ - -#ifndef __USBPD_TIMERSSERVER_H_ -#define __USBPD_TIMERSSERVER_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -/** @addtogroup STM32_USBPD_LIBRARY - * @{ - */ - -/** @addtogroup USBPD_DEVICE - * @{ - */ - -/** @addtogroup USBPD_DEVICE_TIMESERVER - * @{ - */ - -/* Exported constants --------------------------------------------------------*/ -typedef enum { - TIM_PORT0_CRC, - TIM_PORT0_RETRY, - TIM_PORT1_CRC, - TIM_PORT1_RETRY, - TIM_MAX -} -TIM_identifier; - -#define TIM_MAX_TIME 10000u /*time in us, means 10 ms */ -/* Exported types ------------------------------------------------------------*/ -/* External variables --------------------------------------------------------*/ -/* Exported macros -----------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -void USBPD_TIM_Init(void); -void USBPD_TIM_DeInit(void); -void USBPD_TIM_Start(TIM_identifier Id, uint32_t TimeUs); -uint32_t USBPD_TIM_IsExpired(TIM_identifier Id); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBPD_TIMERSSERVER_H_ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_cad_hw_if.c b/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_cad_hw_if.c deleted file mode 100644 index 5c3615b..0000000 --- a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_cad_hw_if.c +++ /dev/null @@ -1,949 +0,0 @@ -/** - ****************************************************************************** - * @file usbpd_cad_hw_if.c - * @author MCD Application Team - * @brief This file contains power hardware interface cad functions. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#define USBPD_CAD_HW_IF_C -#include "usbpd_devices_conf.h" -#include "usbpd_hw.h" -#include "usbpd_def.h" -#include "usbpd_cad_hw_if.h" -#include "usbpd_hw_if.h" -#include "usbpd_core.h" -#include "usbpd_trace.h" - -/** @addtogroup STM32_USBPD_LIBRARY - * @{ - */ - -/** @addtogroup USBPD_DEVICE - * @{ - */ - -/** @addtogroup USBPD_DEVICE_CAD_HW_IF - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/** - * @brief CAD State value @ref USBPD_DEVICE_CAD_HW_IF - * @{ - */ -#define USBPD_CAD_STATE_RESET 0u /*!< USBPD CAD State Reset */ -#define USBPD_CAD_STATE_DETACHED 1u /*!< USBPD CAD State No cable detected */ -#define USBPD_CAD_STATE_ATTACHED_WAIT 2u /*!< USBPD CAD State Port partner detected */ -#define USBPD_CAD_STATE_ATTACHED 3u /*!< USBPD CAD State Port partner attached */ -#define USBPD_CAD_STATE_EMC 4u /*!< USBPD CAD State Electronically Marked Cable detected */ -#define USBPD_CAD_STATE_ATTEMC 5u /*!< USBPD CAD State Port Partner detected throug EMC */ -#define USBPD_CAD_STATE_ACCESSORY 6u /*!< USBPD CAD State Accessory detected */ -#define USBPD_CAD_STATE_DEBUG 7u /*!< USBPD CAD State Debug detected */ -#define USBPD_CAD_STATE_SWITCH_TO_SRC 8u /*!< USBPD CAD State switch to Source */ -#define USBPD_CAD_STATE_SWITCH_TO_SNK 9u /*!< USBPD CAD State switch to Sink */ -#define USBPD_CAD_STATE_UNKNOW 10u /*!< USBPD CAD State unknow */ -/*USBPD_CAD_STATE_ATTACHED_LEGACY 11u*/ /*!< USBPD CAD State Port partner attached to legacy cable */ -#define USBPD_CAD_STATE_ERRORRECOVERY 12u /*!< USBPD CAD State error recovery */ -#define USBPD_CAD_STATE_ERRORRECOVERY_EXIT 13u /*!< USBPD CAD State to exit error recovery */ - -typedef uint32_t USBPD_CAD_STATE; -/** - * @} - */ - -/** - * @brief USB PD CC lines HW condition - */ -#define HW_Detachment 0x00UL /*!< Nothing attached */ -#define HW_Attachment 0x01UL /*!< Sink attached */ -#define HW_PwrCable_NoSink_Attachment 0x02UL /*!< Powered cable without Sink attached */ -#define HW_PwrCable_Sink_Attachment 0x03UL /*!< Powered cable with Sink or VCONN-powered Accessory attached */ -#define HW_Debug_Attachment 0x04UL /*!< Debug Accessory Mode attached */ -#define HW_AudioAdapter_Attachment 0x05UL /*!< Audio Adapter Accessory Mode attached */ - -typedef uint32_t CAD_HW_Condition_TypeDef; - -/** - * @brief CAD State value @ref USBPD_DEVICE_CAD_HW_IF - * @{ - */ -typedef struct -{ - USBPD_CAD_STATE cstate : 4; /* current state */ - USBPD_CAD_STATE pstate : 4; /* previous state */ - CCxPin_TypeDef cc : 2; - CAD_HW_Condition_TypeDef CurrentHWcondition : 3; - CAD_SNK_Source_Current_Adv_Typedef SNK_Source_Current_Adv : 2; - uint32_t CAD_tDebounce_flag : 1; - uint32_t CAD_ErrorRecoveryflag : 1; -#if defined(_DRP) || defined(_SRC) - uint32_t CAD_ResistorUpdateflag : 1; - uint32_t reserved : 12; -#else - uint32_t reserved : 13; -#endif /* _SRC || _DRP */ - -#if defined(_DRP) - uint32_t CAD_tToogle_start; -#endif /* _DRP */ - uint32_t CAD_tDebounce_start, CAD_tDebounce; /* Variable used for attach or detach debounce timers */ -} CAD_HW_HandleTypeDef; -/** - * @} - */ - -/* Private define ------------------------------------------------------------*/ -#define CAD_TPDDEBOUCE_THRESHOLD 12u /**< tPDDebounce threshold = 20ms */ -#define CAD_TCCDEBOUCE_THRESHOLD 100u /**< tCCDebounce threshold = 100ms */ -#define CAD_TSRCDISCONNECT_THRESHOLD 2u /**< tSRCDisconnect detach threshold between 0 to 20ms */ -#define CAD_INFINITE_TIME 0xFFFFFFFFu /**< infinite time to wait a new interrupt event */ -#define CAD_TERROR_RECOVERY_TIME 26u /**< tErrorRecovery min 25ms */ - -/* Private macro -------------------------------------------------------------*/ - -/* Private variables ---------------------------------------------------------*/ - -/* handle to manage the detection state machine */ -static CAD_HW_HandleTypeDef CAD_HW_Handles[USBPD_PORT_COUNT]; - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup USBPD_DEVICE_CAD_HW_IF_Private_Functions USBPD DEVICE_CAD HW IF Private Functions - * @{ - */ -static void CAD_Check_HW(uint8_t PortNum); -#if defined(_DRP) || defined(_SNK) -static uint8_t CAD_Check_VBus(uint8_t PortNum); -#endif /* _DRP || _SNK */ -static uint32_t ManageStateDetached(uint8_t PortNum); -static uint32_t ManageStateAttachedWait(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX); -static uint32_t ManageStateAttached(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX); -static uint32_t ManageStateEMC(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX); -/** - * @} - */ - -/** @defgroup USBPD_DEVICE_CAD_HW_IF_Exported_Functions USBPD DEVICE_CAD HW IF Exported Functions - * @{ - */ - -/** - * @brief function to initialize the cable detection state machine - * @param PortNum port - * @param pSettings Pointer on PD settings based on @ref USBPD_SettingsTypeDef - * @param pParams Pointer on PD params based on @ref USBPD_ParamsTypeDef - * @param WakeUp Wake-up callback function used for waking up CAD - * @retval None - */ -void CAD_Init(uint8_t PortNum, USBPD_SettingsTypeDef *pSettings, USBPD_ParamsTypeDef *pParams, void (*WakeUp)(void)) -{ - CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; - LL_UCPD_InitTypeDef settings; - - Ports[PortNum].params = pParams; -#ifndef _VALID_RP -#define _VALID_RP vRp_3_0A -#endif - Ports[PortNum].params->RpResistor = _VALID_RP; - Ports[PortNum].settings = pSettings; - _handle->cstate = USBPD_CAD_STATE_RESET; - _handle->cc = CCNONE; - _handle->CurrentHWcondition = HW_Detachment; - _handle->SNK_Source_Current_Adv = vRd_Undefined; - - Ports[PortNum].USBPD_CAD_WakeUp = WakeUp; - - /* Initialise the USBPD_IP */ - Ports[PortNum].husbpd = USBPD_HW_GetUSPDInstance(PortNum); - - /* initialise usbpd */ - LL_UCPD_StructInit(&settings); - (void)LL_UCPD_Init(Ports[PortNum].husbpd, &settings); - LL_UCPD_SetRxOrderSet(Ports[PortNum].husbpd, LL_UCPD_ORDERSET_SOP | LL_UCPD_ORDERSET_SOP1 | LL_UCPD_ORDERSET_SOP2 | LL_UCPD_ORDERSET_CABLERST | LL_UCPD_ORDERSET_HARDRST); -#ifdef _LOW_POWER - LL_UCPD_WakeUpEnable(Ports[PortNum].husbpd); -#endif - - LL_PWR_DisableUSBDeadBattery(); /* PWR->CR3 |= (1 << 14); */ - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB); /* GPIOB enable RCC->AHB2ENR |= 2; */ -#if defined(MB1397) /* in case of eval G4 */ - /* Not needed on MB1397 */ -#elif defined (USE_UNIBOARD) || defined(MB1428) || defined(MB1367) /* in case of Nucleo G4 */ - LL_GPIO_SetPinMode(GPIOB, LL_GPIO_PIN_4, LL_GPIO_MODE_ANALOG); /* PB4 mode = GP analog => CC2 */ -#else - LL_GPIO_SetPinMode(GPIOB, LL_GPIO_PIN_4, LL_GPIO_MODE_OUTPUT); /* PB4 mode = GP output => CC2 */ -#endif - LL_GPIO_SetPinPull(GPIOB, LL_GPIO_PIN_4, LL_GPIO_PULL_NO); - - /* Triming */ - /* Ports[PortNum].husbpd->RESERVED0 = 0x1D0F1D0F;*/ - - /* Enable USBPD IP */ - LL_UCPD_Enable(Ports[PortNum].husbpd); - - /* Controls whether for pull-ups and pull-downs controls related to ANAMODE and ANASUBMODE should be applied to CC1 and CC2 analog PHYs */ - /* Should be done when UCPDEN is 1 */ - LL_UCPD_SetccEnable(Ports[PortNum].husbpd, LL_UCPD_CCENABLE_CC1CC2); - -#if defined(_SRC) || defined(_DRP) - /* Intialise usbpd interrupt */ - if (USBPD_PORTPOWERROLE_SRC == Ports[PortNum].params->PE_PowerRole) - { - USBPDM1_AssertRp(PortNum); - } - else -#endif /* _SRC || _DRP */ - { - USBPDM1_AssertRd(PortNum); - } - -} - -/** - * @brief funtion to force CAD state machine into error recovery state - * @param PortNum Index of current used port - * @retval None - */ -void CAD_Enter_ErrorRecovery(uint8_t PortNum) -{ - /* remove the ucpd resistor */ - USBPDM1_EnterErrorRecovery(PortNum); - /* set the error recovery flag to allow the stack to switch into errorRecovery Flag */ - CAD_HW_Handles[PortNum].CAD_ErrorRecoveryflag = USBPD_TRUE; - Ports[PortNum].USBPD_CAD_WakeUp(); -} - -/** - * @brief function to force the value of the RP resistor - * @note Must be called only if you want change the settings value - * @param PortNum Index of current used port - * @param RpValue RP value to set in devices based on @ref CAD_RP_Source_Current_Adv_Typedef - * @retval 0 success else error - */ -uint32_t CAD_Set_ResistorRp(uint8_t PortNum, CAD_RP_Source_Current_Adv_Typedef RpValue) -{ -#if defined(_DRP) || defined(_SRC) - /* update the information about the default resitor value presented in detach mode */ - Ports[PortNum].params->RpResistor = RpValue; - - /* inform state machine about a resistor update */ - CAD_HW_Handles[PortNum].CAD_ResistorUpdateflag = USBPD_TRUE; - Ports[PortNum].USBPD_CAD_WakeUp(); -#endif /* _SRC || _DRP */ - return 0; -} - -/** - * @brief CAD State machine - * @param PortNum Port - * @param pEvent Pointer on CAD event based on @ref USBPD_CAD_EVENT - * @param pCCXX Pointer on CC Pin based on @ref CCxPin_TypeDef - * @retval Timeout value - */ -uint32_t CAD_StateMachine(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX) -{ - CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; - uint32_t _timing = 2; - - /* set by default event to none */ - *pEvent = USBPD_CAD_EVENT_NONE; - - if (USBPD_TRUE == Ports[PortNum].params->PE_SwapOngoing) - { - return _timing; - } - - if (_handle->CAD_ErrorRecoveryflag == USBPD_TRUE) - { - /* Force the state error recovery */ - _handle->CAD_ErrorRecoveryflag = USBPD_FALSE; - _handle->cstate = USBPD_CAD_STATE_ERRORRECOVERY; -#if defined(__DEBUG_CAD) && defined(_TRACE) - USBPD_TRACE_Add(USBPD_TRACE_CAD_LOW, PortNum, (uint8_t)_handle->cstate, NULL, 0); -#endif - } - - /*Check CAD STATE*/ - switch (_handle->cstate) - { - case USBPD_CAD_STATE_SWITCH_TO_SRC: - case USBPD_CAD_STATE_SWITCH_TO_SNK: - { -#if defined(_DRP) - if (Ports[PortNum].settings->CAD_RoleToggle == USBPD_TRUE) - { - if (USBPD_CAD_STATE_SWITCH_TO_SRC == _handle->cstate) - { - USBPDM1_AssertRp(PortNum); - Ports[PortNum].params->PE_PowerRole = USBPD_PORTPOWERROLE_SRC; - _timing = Ports[PortNum].settings->CAD_SRCToggleTime; - } - if (USBPD_CAD_STATE_SWITCH_TO_SNK == _handle->cstate) - { - USBPDM1_AssertRd(PortNum); - Ports[PortNum].params->PE_PowerRole = USBPD_PORTPOWERROLE_SNK; - _timing = Ports[PortNum].settings->CAD_SNKToggleTime; - } - _handle->CAD_tToogle_start = HAL_GetTick(); - } -#endif /* _DRP */ - /* execute detach to present the new resistor according the configuration selected */ - HW_SignalDetachment(PortNum); - _handle->cstate = USBPD_CAD_STATE_DETACHED; - break; - } - - case USBPD_CAD_STATE_RESET: - { - /* on the first call of the usbpd state machine the interrupt and CC pin are enabled */ - LL_UCPD_EnableIT_TypeCEventCC2(Ports[PortNum].husbpd); - LL_UCPD_EnableIT_TypeCEventCC1(Ports[PortNum].husbpd); -#if defined(_DRP) - if (Ports[PortNum].settings->CAD_RoleToggle == USBPD_TRUE) - { - _handle->CAD_tToogle_start = HAL_GetTick(); - } -#endif /* _DRP */ - if (0 == PortNum) - { - UCPD_INSTANCE0_ENABLEIRQ; - } - _handle->cstate = USBPD_CAD_STATE_DETACHED; - break; - } - - case USBPD_CAD_STATE_DETACHED: - _timing = ManageStateDetached(PortNum); - break; - - /*CAD STATE ATTACHED WAIT*/ - case USBPD_CAD_STATE_ATTACHED_WAIT: - _timing = ManageStateAttachedWait(PortNum, pEvent, pCCXX); - break; - - /* CAD ELECTRONIC CABLE ATTACHED */ - case USBPD_CAD_STATE_EMC : - _timing = ManageStateEMC(PortNum, pEvent, pCCXX); - break; - - /*CAD electronic cable with Sink ATTACHED*/ - case USBPD_CAD_STATE_ATTEMC: - case USBPD_CAD_STATE_ATTACHED: - _timing = ManageStateAttached(PortNum, pEvent, pCCXX); - break; - - /*CAD STATE AUDIO ACCESSORY ATTACHED*/ - case USBPD_CAD_STATE_ACCESSORY: - { - _timing = CAD_INFINITE_TIME; - CAD_Check_HW(PortNum); - if (_handle->CurrentHWcondition != HW_AudioAdapter_Attachment) - { - HW_SignalDetachment(PortNum); - _handle->cstate = USBPD_CAD_STATE_SWITCH_TO_SNK; - *pCCXX = CCNONE; - _handle->cc = CCNONE; - *pEvent = USBPD_CAD_EVENT_DETACHED; - } - break; - } - - /*CAD STATE DEBUG ACCESSORY MODE ATTACHED*/ - case USBPD_CAD_STATE_DEBUG: - { - _timing = CAD_INFINITE_TIME; - CAD_Check_HW(PortNum); - if (_handle->CurrentHWcondition != HW_Debug_Attachment) - { - HW_SignalDetachment(PortNum); - _handle->cstate = USBPD_CAD_STATE_SWITCH_TO_SNK; - *pCCXX = CCNONE; - _handle->cc = CCNONE; - *pEvent = USBPD_CAD_EVENT_DETACHED; - } - break; - } - - case USBPD_CAD_STATE_ERRORRECOVERY : - { - /* Remove the resistor */ - /* Enter recovery = Switch to SRC with no resistor */ - USBPDM1_EnterErrorRecovery(PortNum); - - /* forward detach event to DPM */ - *pCCXX = CCNONE; - _handle->cc = CCNONE; - *pEvent = USBPD_CAD_EVENT_DETACHED; - - /* start tErrorRecovery timeout */ - _handle->CAD_tDebounce_start = HAL_GetTick(); - _timing = CAD_TERROR_RECOVERY_TIME; - _handle->cstate = USBPD_CAD_STATE_ERRORRECOVERY_EXIT; - break; - } - - case USBPD_CAD_STATE_ERRORRECOVERY_EXIT : - { - if ((HAL_GetTick() - _handle->CAD_tDebounce_start) > CAD_TERROR_RECOVERY_TIME) - { - /* reconfigure the port - port source to src - port snk to snk - port drp to src */ -#if defined(_DRP) || defined(_SRC) - if ((USBPD_PORTPOWERROLE_SRC == Ports[PortNum].settings->PE_DefaultRole) || (Ports[PortNum].settings->CAD_RoleToggle == USBPD_TRUE)) - { - USBPDM1_AssertRp(PortNum); - Ports[PortNum].params->PE_PowerRole = USBPD_PORTPOWERROLE_SRC; - } -#if defined(_DRP) - else -#endif /* _DRP */ -#endif /* _DRP || _SRC */ -#if defined(_DRP) || defined(_SNK) - { - USBPDM1_AssertRd(PortNum); - Ports[PortNum].params->PE_PowerRole = USBPD_PORTPOWERROLE_SNK; - } -#endif /* _DRP || _SNK */ - /* switch to state detach */ - _handle->CAD_tDebounce_start = HAL_GetTick(); - _handle->cstate = USBPD_CAD_STATE_DETACHED; - } - break; - } - - default : - break; - } - -#if defined(__DEBUG_CAD) && defined(_TRACE) - if (_handle->cstate != _handle->pstate) - { - _handle->pstate = _handle->cstate; - USBPD_TRACE_Add(USBPD_TRACE_CAD_LOW, PortNum, (uint8_t)_handle->cstate, NULL, 0); - } -#endif /* defined(__DEBUG_CAD) && defined(_TRACE) */ - -#if !defined(_RTOS) - /* Delay added for CC detection issue on NRTOS version */ - HAL_Delay(1); -#endif /*_RTOS*/ - return _timing; -} - -/** - * @} - */ - -/** @addtogroup USBPD_DEVICE_CAD_HW_IF_Private_Functions - * @{ - */ - -#if defined(_DRP) || defined(_SNK) -/** - * @brief Check if VBus is present or not - * @param PortNum port - * @retval Return 1 is VBUS is present (0 otherwise) - */ -uint8_t CAD_Check_VBus(uint8_t PortNum) -{ - return (HW_IF_PWR_GetVoltage(PortNum) > BSP_PWR_HIGH_VBUS_THRESHOLD) ? USBPD_TRUE : USBPD_FALSE; -} -#endif /* _DRP || _SNK */ - -/** - * @brief Check CCx HW condition - * @param PortNum port - * @retval none - */ -void CAD_Check_HW(uint8_t PortNum) -{ - uint32_t CC1_value, CC2_value; -#if !defined(_RTOS) - uint32_t CC1_value_temp, CC2_value_temp; -#endif /* !_RTOS */ - CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; - CCxPin_TypeDef _CCx = CCNONE; - /* - ---------------------------------------------------------------------------- - | ANAMODE | ANASUBMODE[1:0] | Notes | TYPEC_VSTATE_CCx[1:0] | - | | | | 00 | 01 | 10 | 11 | - ---------------------------------------------------------------------------- - | 0: Source | 00: Disabled |Disabled N/A | NA | - | | 01: Default USB Rp| |vRaDef|vRdDef|vOPENDef| | - | | 10: 1.5A Rp | |vRa1.5|vRd1.5|vOPEN1.5| NA | - | | 11: 3.0A Rp | |vRa3.0|vRd3.0|vOPEN3.0| NA | - ----------------------------------------------------------------------------- - | 1: Sink | | |xx vRa|vRdUSB| vRd1.5 |vRd3.0| - ----------------------------------------------------------------------------- - */ - CC1_value = Ports[PortNum].PIN_CC1; - CC2_value = Ports[PortNum].PIN_CC2; - -#if !defined(_RTOS) - /* Workaround linked to issue with Ellisys test TD.PC.E5 - - it seems that in NRTOS version, we detect a glitch during DRP transition SNK to SRC */ - CC1_value_temp = Ports[PortNum].husbpd->SR & UCPD_SR_TYPEC_VSTATE_CC1; /*Ports[PortNum].PIN_CC1;*/ - CC2_value_temp = Ports[PortNum].husbpd->SR & UCPD_SR_TYPEC_VSTATE_CC2; /*Ports[PortNum].PIN_CC2;*/ - if ((CC1_value_temp != CC1_value) || (CC2_value_temp != CC2_value)) - { - _handle->cc = _CCx; - return; - } -#endif /* !_RTOS */ - - _handle->CurrentHWcondition = HW_Detachment; - _handle->SNK_Source_Current_Adv = vRd_Undefined; - -#if defined(_DRP) || defined(_SRC) - if (USBPD_PORTPOWERROLE_SRC == Ports[PortNum].params->PE_PowerRole) - { - uint8_t cc2_index = (uint8_t)(CC2_value >> UCPD_SR_TYPEC_VSTATE_CC2_Pos); - - switch (CC1_value) - { - case LL_UCPD_SRC_CC1_VRA : - { - CAD_HW_Condition_TypeDef _tab_hw1[] = - {HW_AudioAdapter_Attachment, HW_PwrCable_Sink_Attachment, HW_PwrCable_NoSink_Attachment}; - _handle->CurrentHWcondition = _tab_hw1[cc2_index]; - _CCx = CC2; - break; - } - case LL_UCPD_SRC_CC1_VRD : - { - CAD_HW_Condition_TypeDef _tab_hw2[] = - {HW_PwrCable_Sink_Attachment, HW_Debug_Attachment, HW_Attachment}; - _handle->CurrentHWcondition = _tab_hw2[cc2_index]; - _CCx = CC1; - break; - } - case LL_UCPD_SRC_CC1_OPEN: - { - CAD_HW_Condition_TypeDef _tab_hw3[] = - {HW_PwrCable_NoSink_Attachment, HW_Attachment, HW_Detachment}; - _handle->CurrentHWcondition = _tab_hw3[cc2_index]; - if (HW_Detachment != _handle->CurrentHWcondition) - { - _CCx = CC2; - } - break; - } - default: - break; - } - } -#if defined(_DRP) - else /* USBPD_PORTPOWERROLE_SNK */ -#endif /* _DRP */ -#endif /*_DRP || _SRC */ -#if defined(_DRP) || defined(_SNK) - { - if ((CC1_value != LL_UCPD_SNK_CC1_VOPEN) && (CC2_value == LL_UCPD_SNK_CC2_VOPEN)) - { - _handle->CurrentHWcondition = HW_Attachment; - _CCx = CC1; - switch (CC1_value) - { - case LL_UCPD_SNK_CC1_VRP: - _handle->SNK_Source_Current_Adv = vRd_USB; - break; - case LL_UCPD_SNK_CC1_VRP15A: - _handle->SNK_Source_Current_Adv = vRd_1_5A; - break; - case LL_UCPD_SNK_CC1_VRP30A: - _handle->SNK_Source_Current_Adv = vRd_3_0A; - break; - default: - break; - } - } - if ((CC2_value != LL_UCPD_SNK_CC2_VOPEN) && (CC1_value == LL_UCPD_SNK_CC1_VOPEN)) - { - _handle->CurrentHWcondition = HW_Attachment; - _CCx = CC2; - switch (CC2_value) - { - case LL_UCPD_SNK_CC2_VRP: - _handle->SNK_Source_Current_Adv = vRd_USB; - break; - case LL_UCPD_SNK_CC2_VRP15A: - _handle->SNK_Source_Current_Adv = vRd_1_5A; - break; - case LL_UCPD_SNK_CC2_VRP30A: - _handle->SNK_Source_Current_Adv = vRd_3_0A; - break; - default: - break; - } - } - } -#endif /*_DRP || _SNK */ - - _handle->cc = _CCx; -} - -static uint32_t ManageStateDetached(uint8_t PortNum) -{ - uint32_t _timing = 2; - CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; - -#if defined(_DRP) || defined(_SRC) - if ((_handle->CAD_ResistorUpdateflag == USBPD_TRUE) && (USBPD_PORTPOWERROLE_SRC == Ports[PortNum].params->PE_PowerRole)) - { - /* update the reistor value */ - USBPDM1_AssertRp(PortNum); - _handle->CAD_ResistorUpdateflag = USBPD_FALSE; - - /* let time to internal state machine update */ - HAL_Delay(1); - } -#endif /* _DRP || _SRC */ - - CAD_Check_HW(PortNum); - /* Change the status on the basis of the HW event given by CAD_Check_HW() */ - if (_handle->CurrentHWcondition == HW_Detachment) - { -#if defined(_DRP) - /* check if role switch must be perform and set the correct sleep time allowed */ - if (USBPD_TRUE == Ports[PortNum].settings->CAD_RoleToggle) - { - switch (Ports[PortNum].params->PE_PowerRole) - { - case USBPD_PORTPOWERROLE_SRC : - if ((HAL_GetTick() - _handle->CAD_tToogle_start) > Ports[PortNum].settings->CAD_SRCToggleTime) - { - _handle->CAD_tToogle_start = HAL_GetTick(); - Ports[PortNum].params->PE_PowerRole = USBPD_PORTPOWERROLE_SNK; - _timing = Ports[PortNum].settings->CAD_SNKToggleTime; - USBPDM1_AssertRd(PortNum); - } - break; - case USBPD_PORTPOWERROLE_SNK : - if ((HAL_GetTick() - _handle->CAD_tToogle_start) > Ports[PortNum].settings->CAD_SNKToggleTime) - { - _handle->CAD_tToogle_start = HAL_GetTick(); - Ports[PortNum].params->PE_PowerRole = USBPD_PORTPOWERROLE_SRC; - _timing = Ports[PortNum].settings->CAD_SRCToggleTime; - USBPDM1_AssertRp(PortNum); - } - break; - default: - break; - } - } - else -#endif /* _DRP */ - { - _timing = CAD_INFINITE_TIME; - } - } - else - { - if (_handle->CurrentHWcondition == HW_PwrCable_NoSink_Attachment) - { - _handle->cstate = USBPD_CAD_STATE_EMC; - } - else - { - BSP_PWR_VBUSInit(PortNum); - _handle->cstate = USBPD_CAD_STATE_ATTACHED_WAIT; - /* Get the time of this event */ - _handle->CAD_tDebounce_start = HAL_GetTick(); - _timing = CAD_TCCDEBOUCE_THRESHOLD + 1u; - } - } - return _timing; -} - -static uint32_t ManageStateAttachedWait(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX) -{ - uint32_t _timing = 2; - CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; - - /* Evaluate elapsed time in Attach_Wait state */ - _handle->CAD_tDebounce = HAL_GetTick() - _handle->CAD_tDebounce_start; - CAD_Check_HW(PortNum); - - if ((_handle->CurrentHWcondition != HW_Detachment) && (_handle->CurrentHWcondition != HW_PwrCable_NoSink_Attachment)) - { -#if defined(_DRP) || defined(_SRC) - if ((BSP_PWR_VBUSGetVoltage(PortNum) > BSP_PWR_LOW_VBUS_THRESHOLD) - && (USBPD_PORTPOWERROLE_SRC == Ports[PortNum].params->PE_PowerRole)) - { - /* reset the timing because VBUS threshold not yet reached */ - _handle->CAD_tDebounce_start = HAL_GetTick(); - return CAD_TCCDEBOUCE_THRESHOLD; - } -#endif /* _DRP || _SRC */ - - /* Check tCCDebounce */ - if (_handle->CAD_tDebounce > CAD_TCCDEBOUCE_THRESHOLD) - { -#if defined(_DRP) || defined(_SRC) - /* if tCCDebounce has expired state must be changed*/ - if (USBPD_PORTPOWERROLE_SRC == Ports[PortNum].params->PE_PowerRole) - { - switch (_handle->CurrentHWcondition) - { - case HW_Attachment: - HW_SignalAttachement(PortNum, _handle->cc); - _handle->cstate = USBPD_CAD_STATE_ATTACHED; - *pEvent = USBPD_CAD_EVENT_ATTACHED; - *pCCXX = _handle->cc; - break; - - case HW_PwrCable_NoSink_Attachment: - _handle->cstate = USBPD_CAD_STATE_EMC; - *pEvent = USBPD_CAD_EVENT_EMC; - *pCCXX = _handle->cc; - break; - - case HW_PwrCable_Sink_Attachment: - HW_SignalAttachement(PortNum, _handle->cc); - _handle->cstate = USBPD_CAD_STATE_ATTEMC; - *pEvent = USBPD_CAD_EVENT_ATTEMC; - break; - - case HW_Debug_Attachment: - _handle->cstate = USBPD_CAD_STATE_DEBUG; - *pEvent = USBPD_CAD_EVENT_DEBUG; - break; - - case HW_AudioAdapter_Attachment: - _handle->cstate = USBPD_CAD_STATE_ACCESSORY; - *pEvent = USBPD_CAD_EVENT_ACCESSORY; - break; - - case HW_Detachment: - default: - /* could not occurs */ - break; - } /* end of switch */ - *pCCXX = _handle->cc; - _timing = 2; - } -#if defined(_DRP) - else /* Check state transition for SNK role */ -#endif /* _DRP */ -#endif /* _DRP || _SRC */ -#if defined(_DRP) || defined(_SNK) - { - _timing = 2; - if (1u == CAD_Check_VBus(PortNum)) /* Check if Vbus is on */ - { - _handle->cstate = USBPD_CAD_STATE_ATTACHED; - *pEvent = USBPD_CAD_EVENT_ATTACHED; - *pCCXX = _handle->cc; - HW_SignalAttachement(PortNum, _handle->cc); - } - } -#endif /* _DRP || _SNK */ - } - else - { - _timing = CAD_TCCDEBOUCE_THRESHOLD - _handle->CAD_tDebounce; - } - /* reset the flag for CAD_tDebounce */ - _handle->CAD_tDebounce_flag = USBPD_FALSE; - } - else /* CAD_HW_Condition[PortNum] = HW_Detachment */ - { -#if defined(_DRP) || defined(_SNK) - if (USBPD_PORTPOWERROLE_SNK == Ports[PortNum].params->PE_PowerRole) - { - /* start counting of CAD_tDebounce */ - if (USBPD_FALSE == _handle->CAD_tDebounce_flag) - { - _handle->CAD_tDebounce_start = HAL_GetTick(); - _handle->CAD_tDebounce_flag = USBPD_TRUE; - _timing = CAD_TPDDEBOUCE_THRESHOLD; - } - else /* CAD_tDebounce already running */ - { - /* evaluate CAD_tDebounce */ - _handle->CAD_tDebounce = HAL_GetTick() - _handle->CAD_tDebounce_start; - if ((_handle->CAD_tDebounce > CAD_TPDDEBOUCE_THRESHOLD)) - { - _handle->CAD_tDebounce_flag = USBPD_FALSE; - _handle->cstate = USBPD_CAD_STATE_SWITCH_TO_SRC; - HW_SignalDetachment(PortNum); - } - } - } -#if defined(_DRP) - else /* (hcad->PortPowerRole != USBPD_PORTPOWERROLE_SNK)*/ -#endif /* _DRP */ -#endif /* _DRP || _SNK */ -#if defined(_DRP) || defined(_SRC) - { - /* start counting of CAD_tDebounce */ - if (USBPD_FALSE == _handle->CAD_tDebounce_flag) - { - _handle->CAD_tDebounce_start = HAL_GetTick(); - _handle->CAD_tDebounce_flag = USBPD_TRUE; - _timing = CAD_TSRCDISCONNECT_THRESHOLD; - } - else /* CAD_tDebounce already running */ - { - /* evaluate CAD_tDebounce */ - _handle->CAD_tDebounce = HAL_GetTick() - _handle->CAD_tDebounce_start; - if (_handle->CAD_tDebounce > CAD_TSRCDISCONNECT_THRESHOLD) - { - _handle->CAD_tDebounce_flag = USBPD_FALSE; - _handle->cstate = USBPD_CAD_STATE_SWITCH_TO_SNK; - HW_SignalDetachment(PortNum); - } - } - } -#endif /* _DRP || _SRC */ - } - - return _timing; -} - -static uint32_t ManageStateEMC(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX) -{ - uint32_t _timing = CAD_INFINITE_TIME; - CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; - - CAD_Check_HW(PortNum); - /* Change the status on the basis of the HW event given by CAD_Check_HW() */ - switch (_handle->CurrentHWcondition) - { - case HW_Detachment : - _handle->cstate = USBPD_CAD_STATE_SWITCH_TO_SNK; - *pEvent = USBPD_CAD_EVENT_DETACHED; - *pCCXX = CCNONE; - _timing = 1; - break; - case HW_PwrCable_Sink_Attachment: - case HW_Attachment : - _handle->cstate = USBPD_CAD_STATE_ATTACHED_WAIT; - _handle->CAD_tDebounce_start = HAL_GetTick() - 5u; /* this is only to check cable presence */ - _timing = 2; - break; - case HW_PwrCable_NoSink_Attachment: - default : - /* nothing to do still the same status */ -#if defined(_DRP) - if (USBPD_TRUE == Ports[PortNum].settings->CAD_RoleToggle) - { - if ((HAL_GetTick() - _handle->CAD_tToogle_start) > Ports[PortNum].settings->CAD_SRCToggleTime) - { - _handle->cstate = USBPD_CAD_STATE_SWITCH_TO_SNK; - } - _timing = 0; - } -#endif /* _DRP */ - break; - } - return _timing; -} - -static uint32_t ManageStateAttached(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX) -{ - uint32_t _timing = 2; - CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; - -#if defined(_DRP) || defined(_SRC) - if (USBPD_PORTPOWERROLE_SRC == Ports[PortNum].params->PE_PowerRole) - { - uint32_t ccx = (Ports[PortNum].CCx == CC1) ? (Ports[PortNum].husbpd->SR & UCPD_SR_TYPEC_VSTATE_CC1) : (Ports[PortNum].husbpd->SR & UCPD_SR_TYPEC_VSTATE_CC2); - uint32_t comp = (Ports[PortNum].CCx == CC1) ? LL_UCPD_SRC_CC1_OPEN : LL_UCPD_SRC_CC2_OPEN; - - if (comp == ccx) - { - /* start counting of CAD_tDebounce */ - if (USBPD_FALSE == _handle->CAD_tDebounce_flag) - { - _handle->CAD_tDebounce_flag = USBPD_TRUE; - _handle->CAD_tDebounce_start = HAL_GetTick(); - _timing = CAD_TSRCDISCONNECT_THRESHOLD; - } - else /* CAD_tDebounce already running */ - { - /* evaluate CAD_tDebounce */ - _handle->CAD_tDebounce = HAL_GetTick() - _handle->CAD_tDebounce_start; - if (_handle->CAD_tDebounce > CAD_TSRCDISCONNECT_THRESHOLD) - { - HW_SignalDetachment(PortNum); -#ifdef _DRP - USBPDM1_AssertRd(PortNum); -#endif - _handle->CAD_tDebounce_flag = USBPD_FALSE; - /* move inside state DETACH to avoid wrong VCONN level*/ - _handle->cstate = USBPD_CAD_STATE_SWITCH_TO_SNK; - *pEvent = USBPD_CAD_EVENT_DETACHED; - *pCCXX = CCNONE; - _timing = 0; - } - } - } - else - { - /* Reset tPDDebounce flag*/ - _handle->CAD_tDebounce_flag = USBPD_FALSE; - _timing = CAD_INFINITE_TIME; - } - } -#if defined(_DRP) - else /* USBPD_PORTPOWERROLE_SNK case */ -#endif /* _DRP */ -#endif /*_DRP || _SRC */ -#if defined(_DRP) || defined(_SNK) - { - if (CAD_Check_VBus(PortNum) == 0u) /* Check if Vbus is off */ - { - _handle->CurrentHWcondition = HW_Detachment; - HW_SignalDetachment(PortNum); - /* restart the toggle time */ -#if defined(_DRP) - _handle->CAD_tToogle_start = HAL_GetTick(); -#endif /* _DRP */ - _handle->cstate = USBPD_CAD_STATE_SWITCH_TO_SRC; - *pEvent = USBPD_CAD_EVENT_DETACHED; - *pCCXX = CCNONE; - _timing = 0; - } - else - { - _timing = 10; - } - } -#endif /*_DRP || _SNK */ - - return _timing; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_hw.c b/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_hw.c deleted file mode 100644 index ba7d50d..0000000 --- a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_hw.c +++ /dev/null @@ -1,122 +0,0 @@ -/** - ****************************************************************************** - * @file usbpd_phy_hw_if.c - * @author MCD Application Team - * @brief This file contains phy interface control functions. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ - -#define USBPD_HW_C -/* Includes ------------------------------------------------------------------*/ -#include "usbpd_devices_conf.h" -#include "usbpd_hw.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Variable containing ADC conversions results */ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -UCPD_TypeDef *USBPD_HW_GetUSPDInstance(uint8_t PortNum) -{ - return UCPD_INSTANCE0; -} - -DMA_Channel_TypeDef *USBPD_HW_Init_DMARxInstance(uint8_t PortNum) -{ - LL_DMA_InitTypeDef DMA_InitStruct; - - /* Initialise the DMA */ - LL_DMA_StructInit(&DMA_InitStruct); - DMA_InitStruct.Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; - DMA_InitStruct.Mode = LL_DMA_MODE_NORMAL; - DMA_InitStruct.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; - DMA_InitStruct.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT; - DMA_InitStruct.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; - DMA_InitStruct.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; - DMA_InitStruct.NbData = 0; - DMA_InitStruct.MemoryOrM2MDstAddress = 0x0; - DMA_InitStruct.PeriphOrM2MSrcAddress = 0x0; - DMA_InitStruct.Priority = LL_DMA_PRIORITY_HIGH; - - /* Enable the clock */ - UCPDDMA_INSTANCE0_CLOCKENABLE_RX; - - /* Initialise the DMA */ - DMA_InitStruct.PeriphRequest = UCPDDMA_INSTANCE0_REQUEST_RX; - - (void)LL_DMA_Init(UCPDDMA_INSTANCE0_DMA_RX, UCPDDMA_INSTANCE0_LL_CHANNEL_RX, &DMA_InitStruct); - - return UCPDDMA_INSTANCE0_CHANNEL_RX; -} - -void USBPD_HW_DeInit_DMARxInstance(uint8_t PortNum) -{ - (void)PortNum; -} - -DMA_Channel_TypeDef *USBPD_HW_Init_DMATxInstance(uint8_t PortNum) -{ - LL_DMA_InitTypeDef DMA_InitStruct; - - /* Initialise the DMA */ - LL_DMA_StructInit(&DMA_InitStruct); - DMA_InitStruct.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH; - DMA_InitStruct.Mode = LL_DMA_MODE_NORMAL; - DMA_InitStruct.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; - DMA_InitStruct.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT; - DMA_InitStruct.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; - DMA_InitStruct.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; - DMA_InitStruct.NbData = 0; - DMA_InitStruct.MemoryOrM2MDstAddress = 0x0; - DMA_InitStruct.PeriphOrM2MSrcAddress = 0x0; - - /* Enable the clock */ - UCPDDMA_INSTANCE0_CLOCKENABLE_TX; - - DMA_InitStruct.PeriphRequest = UCPDDMA_INSTANCE0_REQUEST_TX; - DMA_InitStruct.Priority = LL_DMA_PRIORITY_MEDIUM; - (void)LL_DMA_Init(UCPDDMA_INSTANCE0_DMA_TX, UCPDDMA_INSTANCE0_LL_CHANNEL_TX, &DMA_InitStruct); - - return UCPDDMA_INSTANCE0_CHANNEL_TX; -} - -void USBPD_HW_DeInit_DMATxInstance(uint8_t PortNum) -{ - (void)PortNum; -} - -uint32_t USBPD_HW_GetRpResistorValue(uint8_t PortNum) -{ - (void)PortNum; - return LL_UCPD_RESISTOR_3_0A; -} - -void USBPD_HW_SetFRSSignalling(uint8_t PortNum, uint8_t cc) -{ - (void)PortNum; - /* Configure the GPIO with the AF corresponding to UCPD */ - if (1u == cc) - { - /* FRS_TX1 PA2 (CC1) */ - UCPDFRS_INSTANCE0_FRSCC1; - } - else - { - /* FRS_TX2 PB0 (CC2) */ - UCPDFRS_INSTANCE0_FRSCC2; - } -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_hw_if_it.c b/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_hw_if_it.c deleted file mode 100644 index c739a87..0000000 --- a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_hw_if_it.c +++ /dev/null @@ -1,188 +0,0 @@ -/** - ****************************************************************************** - * @file usbpd_hw_if_it.c - * @author MCD Application Team - * @brief This file contains HW interface interrupt routines. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbpd_devices_conf.h" -#include "usbpd_core.h" -#include "usbpd_hw_if.h" -#include "usbpd_trace.h" - - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -void PORTx_IRQHandler(uint8_t PortNum); - -void USBPD_PORT0_IRQHandler(void) -{ - PORTx_IRQHandler(USBPD_PORT_0); -} - -void USBPD_PORT1_IRQHandler(void) -{ - PORTx_IRQHandler(USBPD_PORT_1); -} - -void PORTx_IRQHandler(uint8_t PortNum) -{ - UCPD_TypeDef *hucpd = Ports[PortNum].husbpd; - uint32_t _interrupt = LL_UCPD_ReadReg(hucpd, SR); - static uint8_t ovrflag = 0; - - if ((hucpd->IMR & _interrupt) != 0u) - { - /* TXIS no need to enable it all the transfert are done by DMA */ - if (UCPD_SR_TXMSGDISC == (_interrupt & UCPD_SR_TXMSGDISC)) - { - /* the message has been discarded */ - LL_UCPD_ClearFlag_TxMSGDISC(hucpd); - CLEAR_BIT(Ports[PortNum].hdmatx->CCR, DMA_CCR_EN); - return; - } - - if (UCPD_SR_TXMSGSENT == (_interrupt & UCPD_SR_TXMSGSENT)) - { - /* Message has been fully transfered */ - Ports[PortNum].cbs.USBPD_HW_IF_TxCompleted(PortNum); - CLEAR_BIT(Ports[PortNum].hdmatx->CCR, DMA_CCR_EN); - LL_UCPD_ClearFlag_TxMSGSENT(hucpd); - return; - } - - if (UCPD_SR_TXMSGABT == (_interrupt & UCPD_SR_TXMSGABT)) - { - LL_UCPD_ClearFlag_TxMSGABT(hucpd); - CLEAR_BIT(Ports[PortNum].hdmatx->CCR, DMA_CCR_EN); - return; - } - - /* TXUND : tx underrun detected */ - if (UCPD_SR_HRSTDISC == (_interrupt & UCPD_SR_HRSTDISC)) - { - LL_UCPD_ClearFlag_TxHRSTDISC(hucpd); - return; - } - - /* TXUND : tx underrun detected */ - if (UCPD_SR_HRSTSENT == (_interrupt & UCPD_SR_HRSTSENT)) - { - /* Mhum, the stack is not expected to get this answer */ - LL_UCPD_ClearFlag_TxHRSTSENT(hucpd); - Ports[PortNum].cbs.USBPD_HW_IF_TX_HardResetCompleted(PortNum, USBPD_SOPTYPE_HARD_RESET); - return; - } - - /* TXUND : tx underrun detected */ - if (UCPD_SR_TXUND == (_interrupt & UCPD_SR_TXUND)) - { - /* nothing to do the port partner check message integrity with CRC so PRL will repeat the sent - can be used for debug purpose */ - LL_UCPD_ClearFlag_TxUND(hucpd); - return; - } - - /* RXNE : not needeed the stack only perform transfer by DMA */ - - /* RXORDDET: not needed so stack will not enabled this interrupt */ - if (UCPD_SR_RXORDDET == (_interrupt & UCPD_SR_RXORDDET)) - { - LL_UCPD_ClearFlag_RxOrderSet(hucpd); - return; - } - - /* check RXHRSTDET */ - if (UCPD_SR_RXHRSTDET == (_interrupt & UCPD_SR_RXHRSTDET)) - { - Ports[PortNum].cbs.USBPD_HW_IF_RX_ResetIndication(PortNum); - LL_UCPD_ClearFlag_RxHRST(hucpd); - return; - } - - /* check RXOVR */ - if (UCPD_SR_RXOVR == (_interrupt & UCPD_SR_RXOVR)) - { - /* nothing to do the message will be discarded and the port partner retry the send */ - ovrflag = 1; - LL_UCPD_ClearFlag_RxOvr(hucpd); - return; - } - - /* check RXMSGEND an Rx message has been recieved */ - if (UCPD_SR_RXMSGEND == (_interrupt & UCPD_SR_RXMSGEND)) - { - /* for DMA mode add a control to check if the number of data recived is corresponding with the number of - data receive by USBPD */ - uint16_t _datasize = (uint16_t)hucpd->RX_PAYSZ; - LL_UCPD_ClearFlag_RxMsgEnd(hucpd); - - /* disable DMA */ - CLEAR_BIT(Ports[PortNum].hdmarx->CCR, DMA_CCR_EN); - - if (((_interrupt & UCPD_SR_RXERR) == 0u) && (ovrflag == 0u)) - { - /* Rx message has been recieved without error */ - Ports[PortNum].cbs.USBPD_HW_IF_RX_Completed(PortNum, hucpd->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET, _datasize); - } - ovrflag = 0; - - /* Ready for next transaction */ - WRITE_REG(Ports[PortNum].hdmarx->CMAR, (uint32_t)Ports[PortNum].ptr_RxBuff); - WRITE_REG(Ports[PortNum].hdmarx->CNDTR, SIZE_MAX_PD_TRANSACTION_UNCHUNK); - - SET_BIT(Ports[PortNum].hdmarx->CCR, DMA_CCR_EN); - return; - } - - /* check TYPECEVT1IE/TYPECEVT1IE */ - if (UCPD_SR_TYPECEVT1 == (_interrupt & UCPD_SR_TYPECEVT1)) - { - Ports[PortNum].PIN_CC1 = hucpd->SR & UCPD_SR_TYPEC_VSTATE_CC1; - Ports[PortNum].PIN_CC2 = hucpd->SR & UCPD_SR_TYPEC_VSTATE_CC2; - /* clear both interrupt */ - LL_UCPD_ClearFlag_TypeCEventCC1(hucpd); - Ports[PortNum].USBPD_CAD_WakeUp(); - /* Wakeup CAD to check the detection event */ - return; - } - - /* check TYPECEVT1IE/TYPECEVT1IE */ - if (UCPD_SR_TYPECEVT2 == (_interrupt & UCPD_SR_TYPECEVT2)) - { - Ports[PortNum].PIN_CC1 = hucpd->SR & UCPD_SR_TYPEC_VSTATE_CC1; - Ports[PortNum].PIN_CC2 = hucpd->SR & UCPD_SR_TYPEC_VSTATE_CC2; - LL_UCPD_ClearFlag_TypeCEventCC2(hucpd); - /* Wakeup CAD to check the detection event */ - Ports[PortNum].USBPD_CAD_WakeUp(); - return; - } - - /* check FRSEVTIE */ - if (_interrupt != UCPD_SR_FRSEVT) - { - /* not yet handled */ - } - } -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_phy.c b/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_phy.c deleted file mode 100644 index 8ec47de..0000000 --- a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_phy.c +++ /dev/null @@ -1,432 +0,0 @@ -/** - ****************************************************************************** - * @file usbpd_phy.c - * @author MCD Application Team - * @brief This file contains PHY layer functions. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbpd_def.h" -#include "usbpd_phy.h" -#include "usbpd_hw_if.h" -#include "usbpd_pwr_if.h" - -/** @addtogroup STM32_USBPD_LIBRARY - * @{ - */ - -/** @addtogroup USBPD_DEVICE - * @{ - */ - -/** @addtogroup USBPD_DEVICE_PHY - * @brief This file contains PHY layer functions. - * @details Receive from PRL a message and create a structured packet (according to the USBPD specifications): - * |SOP|DATA:[HEADER|DATAOBJECTS]|CRC|EOP| - * @{ - */ - -/* Private defines -----------------------------------------------------------*/ -/* Private typedef -----------------------------------------------------------*/ -/** @defgroup USBPD_DEVICE_PHY_Private_typedef USBPD DEVICE PHY Private typedef - * @brief Structures and enums internally used by the PHY layer - * @{ - */ - - -/** - * @brief Handle to support the data of the layer - */ -typedef struct -{ - const USBPD_PHY_Callbacks *cbs; - uint32_t SupportedSOP; /*!USBPD_PHY_ResetCompleted != NULL) - { - PHY_Ports[PortNum].cbs->USBPD_PHY_ResetCompleted(PortNum, Type); - } -} - -/** - * @brief Callback to notify the bist is completed - * @param PortNum Number of the port. - * @param bistmode Modality of the bist. - * @retval none. - */ -void PHY_BistCompleted(uint8_t PortNum, USBPD_BISTMsg_TypeDef bistmode) -{ - if (NULL != PHY_Ports[PortNum].cbs->USBPD_PHY_BistCompleted) - { - PHY_Ports[PortNum].cbs->USBPD_PHY_BistCompleted(PortNum, bistmode); - } -} - -/** - * @brief Callback to notify the a transmission is completed - * @param PortNum Number of the port. - * @retval none. - */ -void PHY_TxCompleted(uint8_t PortNum) -{ - if (NULL != PHY_Ports[PortNum].cbs->USBPD_PHY_TxCompleted) - { - PHY_Ports[PortNum].cbs->USBPD_PHY_TxCompleted(PortNum); - } -} - -/** - * @brief Callback to notify the start of reception - * @param PortNum Number of the port. - * @retval Status of current reception. - */ -USBPD_PHY_RX_Status_TypeDef PHY_Rx_Reset(uint8_t PortNum) -{ - (void)PortNum; - return USBPD_PHY_RX_STATUS_OK; -} - -/** - * @brief Callback to notify the start of reception - * @param PortNum Number of the port. - * @retval Status of current reception. - */ -void PHY_Rx_HardReset(uint8_t PortNum) -{ - /* nothing to do the message will be discarded and the port partner retry the send */ - if (NULL != PHY_Ports[PortNum].cbs->USBPD_PHY_ResetIndication) - { - PHY_Ports[PortNum].cbs->USBPD_PHY_ResetIndication(PortNum, USBPD_SOPTYPE_HARD_RESET); - } -} - -/** - * @brief Callback to notify the end of the current reception - * @param PortNum Number of the port. - * @param MsgType SOP Message Type - * @param RxPaySize Payload RX size - * @retval None. - */ -void PHY_Rx_Completed(uint8_t PortNum, uint32_t MsgType, uint16_t RxPaySize) -{ - USBPD_SOPType_TypeDef _msgtype; - uint8_t _callphy = 1u; - (void)RxPaySize; - - const USBPD_SOPType_TypeDef tab_sop_value[] = { USBPD_SOPTYPE_SOP, USBPD_SOPTYPE_SOP1, USBPD_SOPTYPE_SOP2, - USBPD_SOPTYPE_SOP1_DEBUG, USBPD_SOPTYPE_SOP2_DEBUG, USBPD_SOPTYPE_CABLE_RESET - }; - _msgtype = tab_sop_value[MsgType]; - - /* check if the message must be forwarded to usbpd stack */ - switch (_msgtype) - { - case USBPD_SOPTYPE_CABLE_RESET : - if (0x1Eu == (PHY_Ports[PortNum].SupportedSOP & 0x1Eu)) - { - /* nothing to do the message will be discarded and the port partner retry the send */ - if (PHY_Ports[PortNum].cbs->USBPD_PHY_ResetIndication != NULL) - { - PHY_Ports[PortNum].cbs->USBPD_PHY_ResetIndication(PortNum, USBPD_SOPTYPE_CABLE_RESET); - } - _callphy = 0u; - } - break; - case USBPD_SOPTYPE_SOP : - case USBPD_SOPTYPE_SOP1 : - case USBPD_SOPTYPE_SOP2 : - case USBPD_SOPTYPE_SOP1_DEBUG : - case USBPD_SOPTYPE_SOP2_DEBUG : - if ((uint8_t)(0x1u << _msgtype) != (PHY_Ports[PortNum].SupportedSOP & (uint8_t)(0x1u << _msgtype))) - { - _callphy = 0u; - } - break; - default : - _callphy = 0u; - break; - } - - if ((1u == _callphy) && (PHY_Ports[PortNum].cbs->USBPD_PHY_MessageReceived != NULL)) - { - PHY_Ports[PortNum].cbs->USBPD_PHY_MessageReceived(PortNum, _msgtype); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_phy_hw_if.c b/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_phy_hw_if.c deleted file mode 100644 index d2cb63c..0000000 --- a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_phy_hw_if.c +++ /dev/null @@ -1,334 +0,0 @@ -/** - ****************************************************************************** - * @file usbpd_phy_hw_if.c - * @author MCD Application Team - * @brief This file contains phy interface control functions. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#define USBPD_PHY_HW_IF_C - -#include "usbpd_devices_conf.h" -#include "usbpd_hw.h" -#include "usbpd_core.h" -#include "usbpd_hw_if.h" -#include "usbpd_timersserver.h" - -/* Private typedef -----------------------------------------------------------*/ - -/* Private function prototypes -----------------------------------------------*/ -USBPD_PORT_HandleTypeDef Ports[USBPD_PORT_COUNT]; - - -/* Private functions ---------------------------------------------------------*/ - - -void USBPD_HW_IF_GlobalHwInit(void) -{ - LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC); - LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); - LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPUART1); - /* Init timer to detect the reception of goodCRC */ - USBPD_TIM_Init(); - - /* Initialise VBUS power */ - (void)BSP_PWR_VBUSInit(0); - -} - -void USBPD_HW_IF_StopBISTMode2(uint8_t PortNum) -{ - uint32_t _cr = READ_REG(Ports[PortNum].husbpd->CR) & ~(UCPD_CR_TXMODE | UCPD_CR_TXSEND); - - LL_UCPD_Disable(Ports[PortNum].husbpd); - LL_UCPD_Enable(Ports[PortNum].husbpd); - - Ports[PortNum].husbpd->CR = _cr; -} - -USBPD_StatusTypeDef USBPD_HW_IF_SendBuffer(uint8_t PortNum, USBPD_SOPType_TypeDef Type, uint8_t *pBuffer, uint32_t Size) -{ - USBPD_StatusTypeDef _status = USBPD_OK; - - if (USBPD_SOPTYPE_HARD_RESET == Type) - { - LL_UCPD_SendHardReset(Ports[PortNum].husbpd); - } - else - { - switch (Type) - { - case USBPD_SOPTYPE_SOP : - { - LL_UCPD_WriteTxOrderSet(Ports[PortNum].husbpd, LL_UCPD_ORDERED_SET_SOP); - LL_UCPD_SetTxMode(Ports[PortNum].husbpd, LL_UCPD_TXMODE_NORMAL); - break; - } - case USBPD_SOPTYPE_SOP1 : - { - LL_UCPD_WriteTxOrderSet(Ports[PortNum].husbpd, LL_UCPD_ORDERED_SET_SOP1); - LL_UCPD_SetTxMode(Ports[PortNum].husbpd, LL_UCPD_TXMODE_NORMAL); - break; - } - case USBPD_SOPTYPE_SOP2 : - { - LL_UCPD_WriteTxOrderSet(Ports[PortNum].husbpd, LL_UCPD_ORDERED_SET_SOP2); - LL_UCPD_SetTxMode(Ports[PortNum].husbpd, LL_UCPD_TXMODE_NORMAL); - break; - } - case USBPD_SOPTYPE_CABLE_RESET : - { - LL_UCPD_SetTxMode(Ports[PortNum].husbpd, LL_UCPD_TXMODE_CABLE_RESET); - break; - } - case USBPD_SOPTYPE_BIST_MODE_2 : - { - LL_UCPD_SetTxMode(Ports[PortNum].husbpd, LL_UCPD_TXMODE_BIST_CARRIER2); - break; - } - default : - _status = USBPD_ERROR; - break; - } - - if (USBPD_OK == _status) - { - WRITE_REG(Ports[PortNum].hdmatx->CMAR, (uint32_t)pBuffer); - WRITE_REG(Ports[PortNum].hdmatx->CNDTR, Size); - Ports[PortNum].hdmatx->CCR |= DMA_CCR_EN; - - LL_UCPD_WriteTxPaySize(Ports[PortNum].husbpd, Size); - LL_UCPD_SendMessage(Ports[PortNum].husbpd); - } - } - return _status; -} - -void USBPD_HW_IF_Send_BIST_Pattern(uint8_t PortNum) -{ - LL_UCPD_SetTxMode(Ports[PortNum].husbpd, LL_UCPD_TXMODE_BIST_CARRIER2); - LL_UCPD_SendMessage(Ports[PortNum].husbpd); -} - -void USBPDM1_AssertRp(uint8_t PortNum) -{ - switch (Ports[PortNum].params->RpResistor) - { - case vRp_Default : - LL_UCPD_SetRpResistor(Ports[PortNum].husbpd, LL_UCPD_RESISTOR_DEFAULT); - break; - case vRp_1_5A: - LL_UCPD_SetRpResistor(Ports[PortNum].husbpd, LL_UCPD_RESISTOR_1_5A); - break; - case vRp_3_0A: - LL_UCPD_SetRpResistor(Ports[PortNum].husbpd, LL_UCPD_RESISTOR_3_0A); - break; - default: - break; - } - LL_UCPD_SetccEnable(Ports[PortNum].husbpd, LL_UCPD_CCENABLE_NONE); - LL_UCPD_SetSRCRole(Ports[PortNum].husbpd); - LL_UCPD_SetccEnable(Ports[PortNum].husbpd, LL_UCPD_CCENABLE_CC1CC2); -} - -void USBPDM1_DeAssertRp(uint8_t PortNum) -{ - /* not needed on G4, so nothing to do, keep only for compatibility */ - UNUSED(PortNum); -} - -void USBPDM1_AssertRd(uint8_t PortNum) -{ - LL_UCPD_TypeCDetectionCC2Disable(Ports[PortNum].husbpd); - LL_UCPD_TypeCDetectionCC1Disable(Ports[PortNum].husbpd); - - LL_UCPD_SetccEnable(Ports[PortNum].husbpd, LL_UCPD_CCENABLE_NONE); - LL_UCPD_SetSNKRole(Ports[PortNum].husbpd); - LL_UCPD_SetccEnable(Ports[PortNum].husbpd, LL_UCPD_CCENABLE_CC1CC2); - - HAL_Delay(1); - - LL_UCPD_TypeCDetectionCC2Enable(Ports[PortNum].husbpd); - LL_UCPD_TypeCDetectionCC1Enable(Ports[PortNum].husbpd); - -} - -void USBPDM1_EnterErrorRecovery(uint8_t PortNum) -{ - LL_UCPD_SetSRCRole(Ports[PortNum].husbpd); - LL_UCPD_SetRpResistor(Ports[PortNum].husbpd, LL_UCPD_RESISTOR_NONE); -} - -void USBPDM1_DeAssertRd(uint8_t PortNum) -{ - /* not needed on G4, so nothing to do, keep only for compatibility */ - UNUSED(PortNum); -} - -void USBPDM1_Set_CC(uint8_t PortNum, CCxPin_TypeDef cc) -{ - /* Set the correct pin on the comparator*/ - Ports[PortNum].CCx = cc; - LL_UCPD_SetCCPin(Ports[PortNum].husbpd , (cc == CC1) ? LL_UCPD_CCPIN_CC1 : LL_UCPD_CCPIN_CC2); -} - -void USBPDM1_RX_EnableInterrupt(uint8_t PortNum) -{ - /* Enable the RX interrupt process */ - MODIFY_REG(Ports[PortNum].husbpd->IMR, UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | UCPD_IMR_RXMSGENDIE, - UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | UCPD_IMR_RXMSGENDIE); - LL_UCPD_RxDMAEnable(Ports[PortNum].husbpd); -} - -void USBPD_HW_IF_EnableRX(uint8_t PortNum) -{ - LL_UCPD_RxEnable(Ports[PortNum].husbpd); - -} - -void USBPD_HW_IF_DisableRX(uint8_t PortNum) -{ - LL_UCPD_RxDisable(Ports[PortNum].husbpd); -} - -void HW_SignalAttachement(uint8_t PortNum, CCxPin_TypeDef cc) -{ - uint32_t _temp; - - /* Init timer to detect the reception of goodCRC */ - USBPD_TIM_Init(); - - /* Prepare ucpd to handle PD message - RX message start listen - TX prepare the DMA to be transfer ready - Detection listen only the line corresponding CC=Rd for SRC/SNK */ - Ports[PortNum].hdmatx = USBPD_HW_Init_DMATxInstance(PortNum); - Ports[PortNum].hdmarx = USBPD_HW_Init_DMARxInstance(PortNum); - - /* Set the RX dma to allow reception */ - _temp = (uint32_t)&Ports[PortNum].husbpd->RXDR; - WRITE_REG(Ports[PortNum].hdmarx->CPAR, _temp); - WRITE_REG(Ports[PortNum].hdmarx->CMAR, (uint32_t)Ports[PortNum].ptr_RxBuff); - Ports[PortNum].hdmarx->CNDTR = SIZE_MAX_PD_TRANSACTION_UNCHUNK; - Ports[PortNum].hdmarx->CCR |= DMA_CCR_EN; - - /* Set the TX dma only UCPD address */ - _temp = (uint32_t)&Ports[PortNum].husbpd->TXDR; - Ports[PortNum].hdmatx->CPAR = _temp; - - /* disabled non Rd line set CC line enable */ -#define INTERRUPT_MASK UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE | UCPD_IMR_TXMSGABTIE |\ - UCPD_IMR_TXUNDIE | UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | UCPD_IMR_RXMSGENDIE - - MODIFY_REG(Ports[PortNum].husbpd->IMR, INTERRUPT_MASK, INTERRUPT_MASK); - - /* Handle CC enable */ - Ports[PortNum].CCx = cc; - if (USBPD_PORTPOWERROLE_SRC == Ports[PortNum].params->PE_PowerRole) - { - LL_UCPD_SetccEnable(Ports[PortNum].husbpd, LL_UCPD_CCENABLE_CC1CC2); - } - else - { - /* disconnect is done by VBUS */ - LL_UCPD_SetccEnable(Ports[PortNum].husbpd, (Ports[PortNum].CCx == CC1) ? LL_UCPD_CCENABLE_CC1 : LL_UCPD_CCENABLE_CC2); - } - - /* Set CC pin for PD message */ - LL_UCPD_SetCCPin(Ports[PortNum].husbpd, (Ports[PortNum].CCx == CC1) ? LL_UCPD_CCPIN_CC1 : LL_UCPD_CCPIN_CC2); - -#if defined(USBPD_REV30_SUPPORT) - if (Ports[PortNum].settings->PE_PD3_Support.d.PE_FastRoleSwapSupport == USBPD_TRUE) - { - /* Set GPIO to allow the FRSTX handling */ - USBPD_HW_SetFRSSignalling(PortNum, (Ports[PortNum].CCx == CC1) ? 1u : 2u); - } -#endif /* USBPD_REV30_SUPPORT */ - -#if defined(_VCONN_SUPPORT) - /* Initialize Vconn managment */ - (void)BSP_PWR_VCONNInit(PortNum, (Ports[PortNum].CCx == CC1) ? 1u : 2u); -#endif /* _VCONN_SUPPORT */ - /* Disable the Resistor on Vconn PIN */ - (Ports[PortNum].CCx == CC1) ? LL_UCPD_SetccEnable(Ports[PortNum].husbpd, LL_UCPD_CCENABLE_CC1) : LL_UCPD_SetccEnable(Ports[PortNum].husbpd, LL_UCPD_CCENABLE_CC2); - - /* Prepare the rx processing */ - LL_UCPD_SetRxMode(Ports[PortNum].husbpd, LL_UCPD_RXMODE_NORMAL); - LL_UCPD_RxDMAEnable(Ports[PortNum].husbpd); - LL_UCPD_TxDMAEnable(Ports[PortNum].husbpd); - LL_UCPD_RxEnable(Ports[PortNum].husbpd); -} - - -void HW_SignalDetachment(uint8_t PortNum) -{ - LL_UCPD_RxDMADisable(Ports[PortNum].husbpd); - LL_UCPD_TxDMADisable(Ports[PortNum].husbpd); - LL_UCPD_RxDisable(Ports[PortNum].husbpd); - - /* Enable only detection interrupt */ - WRITE_REG(Ports[PortNum].husbpd->IMR, UCPD_IMR_TYPECEVT1IE | UCPD_IMR_TYPECEVT2IE); - - /* stop DMA RX/TX */ - LL_UCPD_RxDMADisable(Ports[PortNum].husbpd); - LL_UCPD_TxDMADisable(Ports[PortNum].husbpd); - - USBPD_HW_DeInit_DMATxInstance(PortNum); - USBPD_HW_DeInit_DMARxInstance(PortNum); - - LL_UCPD_SetccEnable(Ports[PortNum].husbpd, LL_UCPD_CCENABLE_CC1CC2); -} - -void USBPD_HW_IF_SetResistor_SinkTxNG(uint8_t PortNum) -{ - /* set the resistor SinkTxNG 1.5A5V */ - LL_UCPD_SetRpResistor(Ports[PortNum].husbpd, LL_UCPD_RESISTOR_1_5A); -} - -void USBPD_HW_IF_SetResistor_SinkTxOK(uint8_t PortNum) -{ - /* set the resistor SinkTxNG 3.0A5V */ - LL_UCPD_SetRpResistor(Ports[PortNum].husbpd, LL_UCPD_RESISTOR_3_0A); -} - -uint8_t USBPD_HW_IF_IsResistor_SinkTxOk(uint8_t PortNum) -{ - switch (Ports[PortNum].CCx) - { - case CC1 : - if (Ports[PortNum].PIN_CC1 == LL_UCPD_SNK_CC1_VRP30A) - { - return USBPD_TRUE; - } - break; - case CC2 : - if (Ports[PortNum].PIN_CC2 == LL_UCPD_SNK_CC2_VRP30A) - { - return USBPD_TRUE; - } - break; - default: - break; - } - - return USBPD_FALSE; -} - -void USBPD_HW_IF_FastRoleSwapSignalling(uint8_t PortNum) -{ - LL_UCPD_SignalFRSTX(Ports[PortNum].husbpd); -} -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_pwr_hw_if.c b/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_pwr_hw_if.c deleted file mode 100644 index 67105df..0000000 --- a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_pwr_hw_if.c +++ /dev/null @@ -1,115 +0,0 @@ -/** - ****************************************************************************** - * @file usbpd_pwr_hw_if.c - * @author MCD Application Team - * @brief This file contains power hardware interface functions. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbpd_hw_if.h" - - -#define _USBPD_POWER_DEBUG -#ifdef _USBPD_POWER_DEBUG -#include "usbpd_core.h" -#include "usbpd_trace.h" -#endif - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#if defined(_USBPD_POWER_DEBUG) && defined(_TRACE) -#define POWER_DEBUG(__MSG__,__SIZE__) USBPD_TRACE_Add(USBPD_TRACE_DEBUG, PortNum, 0,__MSG__,__SIZE__); -#else -#define POWER_DEBUG(__MSG__,__SIZE__) -#endif - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -USBPD_StatusTypeDef HW_IF_PWR_SetVoltage(uint8_t PortNum, uint16_t voltage) -{ - UNUSED(PortNum); - UNUSED(voltage); - /* Section below has been commented for the P-Nucleo Demo */ - /* - uint32_t off = (PortNum == 0) ? 0 : 2; - switch (voltage) - { - case 12000: - HAL_GPIO_WritePin(USBPDM1_POWSELs[0+off].GPIOx, USBPDM1_POWSELs[0+off].GPIO_Pin, GPIO_PIN_SET); - break; - case 5000: - default: - HAL_GPIO_WritePin(USBPDM1_POWSELs[0+off].GPIOx, USBPDM1_POWSELs[0+off].GPIO_Pin, GPIO_PIN_RESET); - break; - } - */ - return USBPD_OK; -} - -uint16_t HW_IF_PWR_GetVoltage(uint8_t PortNum) -{ - return (uint16_t)BSP_PWR_VBUSGetVoltage(PortNum);; -} - -int16_t HW_IF_PWR_GetCurrent(uint8_t PortNum) -{ - return (int16_t)BSP_PWR_VBUSGetCurrent(PortNum);; -} - -#if defined(_SRC) || defined(_DRP) -USBPD_StatusTypeDef HW_IF_PWR_Enable(uint8_t PortNum, USBPD_FunctionalState state, CCxPin_TypeDef Cc, uint32_t VconnState, USBPD_PortPowerRole_TypeDef role) -{ - UNUSED(role); - PWR_StatusTypeDef status; - if (USBPD_ENABLE == state) - { -#if defined(_VCONN_SUPPORT) - if (USBPD_TRUE == VconnState) - { - POWER_DEBUG((uint8_t *)"VCONN ON", 8); - (void)BSP_PWR_VCONNOn(PortNum, Cc); - } -#endif /* _VCONN_SUPPORT */ - POWER_DEBUG((uint8_t *)"VBUS ON", 7); - status = BSP_PWR_VBUSOn(PortNum); - } - else - { -#if defined(_VCONN_SUPPORT) - if (VconnState == USBPD_TRUE) - { - POWER_DEBUG((uint8_t *)"VCONN OFF", 9); - (void)BSP_PWR_VCONNOff(PortNum, Cc); - } -#endif /* _VCONN_SUPPORT */ - POWER_DEBUG((uint8_t *)"VBUS OFF", 8); - status = BSP_PWR_VBUSOff(PortNum); - } - return (status == PWR_OK) ? USBPD_OK : USBPD_FAIL; -} -#endif /* _SRC || _DRP */ - -USBPD_FunctionalState HW_IF_PWR_VBUSIsEnabled(uint8_t PortNum) -{ -#if defined(_SRC)||defined(_DRP) - return (BSP_PWR_VBUSIsOn(PortNum) == 0) ? USBPD_DISABLE : USBPD_ENABLE; -#else - return USBPD_DISABLE; -#endif /* _SRC || _DRP */ -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_timersserver.c b/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_timersserver.c deleted file mode 100644 index 5193579..0000000 --- a/Software/VNA_embedded/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_timersserver.c +++ /dev/null @@ -1,170 +0,0 @@ -/** - ****************************************************************************** - * @file usbpd_timersserver.c - * @author MCD Application Team - * @brief This file contains timer server functions. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbpd_devices_conf.h" -#include "usbpd_timersserver.h" - -/** @addtogroup STM32_USBPD_LIBRARY - * @{ - */ - -/** @addtogroup USBPD_DEVICE - * @{ - */ - -/** @addtogroup USBPD_DEVICE_TIMESERVER - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -int8_t timer_initcounter = 0; -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief Initialize a timer to manage timing in us - * @retval None - */ -void USBPD_TIM_Init(void) -{ - if (0 == timer_initcounter) - { - TIMX_CLK_ENABLE; - /***************************/ - /* Time base configuration */ - /***************************/ - /* Counter mode: select up-counting mode */ - LL_TIM_SetCounterMode(TIMX, LL_TIM_COUNTERMODE_UP); - - /* Set the pre-scaler value to have TIMx counter clock equal to 1 MHz */ - LL_TIM_SetPrescaler(TIMX, __LL_TIM_CALC_PSC(SystemCoreClock, 1000000u)); - - /* Set the auto-reload value to have a counter frequency of 100Hz */ - LL_TIM_SetAutoReload(TIMX, __LL_TIM_CALC_ARR(SystemCoreClock, LL_TIM_GetPrescaler(TIMX), 100u)); - - /*********************************/ - /* Output waveform configuration */ - /*********************************/ - /* Set output compare mode: TOGGLE */ - LL_TIM_OC_SetMode(TIMX, TIMX_CHANNEL_CH1, LL_TIM_OCMODE_TOGGLE); - LL_TIM_OC_SetMode(TIMX, TIMX_CHANNEL_CH2, LL_TIM_OCMODE_TOGGLE); - LL_TIM_OC_SetMode(TIMX, TIMX_CHANNEL_CH3, LL_TIM_OCMODE_TOGGLE); - LL_TIM_OC_SetMode(TIMX, TIMX_CHANNEL_CH4, LL_TIM_OCMODE_TOGGLE); - - /* Set output channel polarity: OC is active high */ - LL_TIM_OC_SetPolarity(TIMX, TIMX_CHANNEL_CH1, LL_TIM_OCPOLARITY_HIGH); - LL_TIM_OC_SetPolarity(TIMX, TIMX_CHANNEL_CH2, LL_TIM_OCPOLARITY_HIGH); - LL_TIM_OC_SetPolarity(TIMX, TIMX_CHANNEL_CH3, LL_TIM_OCPOLARITY_HIGH); - LL_TIM_OC_SetPolarity(TIMX, TIMX_CHANNEL_CH4, LL_TIM_OCPOLARITY_HIGH); - - /* Enable counter */ - LL_TIM_EnableCounter(TIMX); - } - - /* Enable the timer counter */ - timer_initcounter++; -} - -/** - * @brief UnInitialize a timer to manage timing in us - * @retval None - */ -void USBPD_TIM_DeInit(void) -{ - timer_initcounter--; - if(0 == timer_initcounter) - { - TIMX_CLK_DISABLE; - } -} - -/** - * @brief start the timer counting - * @param timer id @TIM_identifier - * @param time in us - * @retval None - */ -void USBPD_TIM_Start(TIM_identifier Id, uint32_t TimeUs) -{ - /* Positionne l'evenement pour sa detection */ - switch (Id) - { - case TIM_PORT0_CRC: - TIMX_CHANNEL1_SETEVENT; - break; - case TIM_PORT0_RETRY: - TIMX_CHANNEL2_SETEVENT; - break; - case TIM_PORT1_CRC: - TIMX_CHANNEL3_SETEVENT; - break; - case TIM_PORT1_RETRY: - TIMX_CHANNEL4_SETEVENT; - break; - default: - break; - } -} - -/** - * @brief check timer expiration - * @param timer id @TIM_identifier - * @retval None - */ -uint32_t USBPD_TIM_IsExpired(TIM_identifier Id) -{ - uint32_t _expired = 1u; - switch (Id) - { - case TIM_PORT0_CRC: - _expired = TIMX_CHANNEL1_GETFLAG(TIMX); - break; - case TIM_PORT0_RETRY: - _expired = TIMX_CHANNEL2_GETFLAG(TIMX); - break; - case TIM_PORT1_CRC: - _expired = TIMX_CHANNEL3_GETFLAG(TIMX); - break; - case TIM_PORT1_RETRY: - _expired = TIMX_CHANNEL4_GETFLAG(TIMX); - break; - default: - break; - } - return _expired; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c index f8f065f..0900213 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c @@ -53,49 +53,6 @@ * POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ - /** - ****************************************************************************** - * @file cmsis_os.c - * @author MCD Application Team - * @date 13-July-2017 - * @brief CMSIS-RTOS API implementation for FreeRTOS V10.0.1 - ****************************************************************************** - * @attention - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - #include #include "cmsis_os.h" @@ -407,7 +364,7 @@ osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void 1, // period should be filled when starting the Timer using osTimerStart (type == osTimerPeriodic) ? pdTRUE : pdFALSE, (void *) argument, - (TaskFunction_t)timer_def->ptimer, + (TimerCallbackFunction_t)timer_def->ptimer, (StaticTimer_t *)timer_def->controlblock); } else { @@ -415,21 +372,21 @@ osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void 1, // period should be filled when starting the Timer using osTimerStart (type == osTimerPeriodic) ? pdTRUE : pdFALSE, (void *) argument, - (TaskFunction_t)timer_def->ptimer); + (TimerCallbackFunction_t)timer_def->ptimer); } #elif( configSUPPORT_STATIC_ALLOCATION == 1 ) return xTimerCreateStatic((const char *)"", 1, // period should be filled when starting the Timer using osTimerStart (type == osTimerPeriodic) ? pdTRUE : pdFALSE, (void *) argument, - (TaskFunction_t)timer_def->ptimer, + (TimerCallbackFunction_t)timer_def->ptimer, (StaticTimer_t *)timer_def->controlblock); #else return xTimerCreate((const char *)"", 1, // period should be filled when starting the Timer using osTimerStart (type == osTimerPeriodic) ? pdTRUE : pdFALSE, (void *) argument, - (TaskFunction_t)timer_def->ptimer); + (TimerCallbackFunction_t)timer_def->ptimer); #endif #else @@ -991,10 +948,7 @@ void *osPoolAlloc (osPoolId pool_id) } for (i = 0; i < pool_id->pool_sz; i++) { - index = pool_id->currentIndex + i; - if (index >= pool_id->pool_sz) { - index = 0; - } + index = (pool_id->currentIndex + i) % pool_id->pool_sz; if (pool_id->markers[index] == 0) { pool_id->markers[index] = 1; diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h index 1fd0581..1fb4186 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h @@ -53,51 +53,6 @@ * POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ - /** - ****************************************************************************** - * @file cmsis_os.h - * @author MCD Application Team - * @date 13-July-2017 - * @brief Header of cmsis_os.c - * A new set of APIs are added in addition to existing ones, these APIs - * are specific to FreeRTOS. - ****************************************************************************** - * @attention - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - #include "FreeRTOS.h" #include "task.h" #include "timers.h" diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/LICENSE b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/LICENSE new file mode 100644 index 0000000..d479d8b --- /dev/null +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/LICENSE @@ -0,0 +1,18 @@ +Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/croutine.c b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/croutine.c index b995073..507e217 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/croutine.c +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/croutine.c @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -260,7 +260,7 @@ CRCB_t *pxCRCB; ( void ) uxListRemove( &( pxCRCB->xGenericListItem ) ); /* Is the co-routine waiting on an event also? */ - if( pxCRCB->xEventListItem.pvContainer ) + if( pxCRCB->xEventListItem.pxContainer ) { ( void ) uxListRemove( &( pxCRCB->xEventListItem ) ); } diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c index 4257950..0bf3b96 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -39,11 +39,11 @@ task.h is included from an application file. */ #include "timers.h" #include "event_groups.h" -/* Lint e961 and e750 are suppressed as a MISRA exception justified because the -MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the -header files above, but not in this file, in order to generate the correct -privileged Vs unprivileged linkage and placement. */ -#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */ +/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified +because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined +for the header files above, but not in this file, in order to generate the +correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */ /* The following bit fields convey control information in a task's event list item value. It is important they don't clash with the @@ -60,7 +60,7 @@ taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */ #define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL #endif -typedef struct xEventGroupDefinition +typedef struct EventGroupDef_t { EventBits_t uxEventBits; List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */ @@ -104,11 +104,11 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, co event group structure. */ volatile size_t xSize = sizeof( StaticEventGroup_t ); configASSERT( xSize == sizeof( EventGroup_t ) ); - } + } /*lint !e529 xSize is referenced if configASSERT() is defined. */ #endif /* configASSERT_DEFINED */ /* The user has provided a statically allocated event group - use it. */ - pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 EventGroup_t and StaticEventGroup_t are guaranteed to have the same size and alignment requirement - checked by configASSERT(). */ + pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */ if( pxEventBits != NULL ) { @@ -128,10 +128,13 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, co } else { + /* xEventGroupCreateStatic should only ever be called with + pxEventGroupBuffer pointing to a pre-allocated (compile time + allocated) StaticEventGroup_t variable. */ traceEVENT_GROUP_CREATE_FAILED(); } - return ( EventGroupHandle_t ) pxEventBits; + return pxEventBits; } #endif /* configSUPPORT_STATIC_ALLOCATION */ @@ -143,8 +146,20 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, co { EventGroup_t *pxEventBits; - /* Allocate the event group. */ - pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); + /* Allocate the event group. Justification for MISRA deviation as + follows: pvPortMalloc() always ensures returned memory blocks are + aligned per the requirements of the MCU stack. In this case + pvPortMalloc() must return a pointer that is guaranteed to meet the + alignment requirements of the EventGroup_t structure - which (if you + follow it through) is the alignment requirements of the TickType_t type + (EventBits_t being of TickType_t itself). Therefore, whenever the + stack alignment requirements are greater than or equal to the + TickType_t alignment requirements the cast is safe. In other cases, + where the natural word size of the architecture is less than + sizeof( TickType_t ), the TickType_t variables will be accessed in two + or more reads operations, and the alignment requirements is only that + of each individual read. */ + pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */ if( pxEventBits != NULL ) { @@ -164,10 +179,10 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, co } else { - traceEVENT_GROUP_CREATE_FAILED(); + traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */ } - return ( EventGroupHandle_t ) pxEventBits; + return pxEventBits; } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ @@ -176,7 +191,7 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, co EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) { EventBits_t uxOriginalBitValue, uxReturn; -EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventGroup_t *pxEventBits = xEventGroup; BaseType_t xAlreadyYielded; BaseType_t xTimeoutOccurred = pdFALSE; @@ -295,7 +310,7 @@ BaseType_t xTimeoutOccurred = pdFALSE; EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) { -EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventGroup_t *pxEventBits = xEventGroup; EventBits_t uxReturn, uxControlBits = 0; BaseType_t xWaitConditionMet, xAlreadyYielded; BaseType_t xTimeoutOccurred = pdFALSE; @@ -445,7 +460,7 @@ BaseType_t xTimeoutOccurred = pdFALSE; EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) { -EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventGroup_t *pxEventBits = xEventGroup; EventBits_t uxReturn; /* Check the user is not attempting to clear the bits used by the kernel @@ -477,7 +492,7 @@ EventBits_t uxReturn; BaseType_t xReturn; traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ); - xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ return xReturn; } @@ -488,7 +503,7 @@ EventBits_t uxReturn; EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) { UBaseType_t uxSavedInterruptStatus; -EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventGroup_t const * const pxEventBits = xEventGroup; EventBits_t uxReturn; uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); @@ -498,16 +513,16 @@ EventBits_t uxReturn; portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return uxReturn; -} +} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */ /*-----------------------------------------------------------*/ EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) { ListItem_t *pxListItem, *pxNext; ListItem_t const *pxListEnd; -List_t *pxList; +List_t const * pxList; EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits; -EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventGroup_t *pxEventBits = xEventGroup; BaseType_t xMatchFound = pdFALSE; /* Check the user is not attempting to set the bits used by the kernel @@ -516,7 +531,7 @@ BaseType_t xMatchFound = pdFALSE; configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); pxList = &( pxEventBits->xTasksWaitingForBits ); - pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ vTaskSuspendAll(); { traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ); @@ -597,7 +612,7 @@ BaseType_t xMatchFound = pdFALSE; void vEventGroupDelete( EventGroupHandle_t xEventGroup ) { -EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventGroup_t *pxEventBits = xEventGroup; const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits ); vTaskSuspendAll(); @@ -641,7 +656,7 @@ const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits ); an interrupt. */ void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) { - ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); + ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ } /*-----------------------------------------------------------*/ @@ -649,7 +664,7 @@ void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet an interrupt. */ void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) { - ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); + ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ } /*-----------------------------------------------------------*/ @@ -695,7 +710,7 @@ BaseType_t xWaitConditionMet = pdFALSE; BaseType_t xReturn; traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ); - xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ return xReturn; } @@ -708,7 +723,7 @@ BaseType_t xWaitConditionMet = pdFALSE; UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) { UBaseType_t xReturn; - EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; + EventGroup_t const *pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ if( xEventGroup == NULL ) { @@ -729,7 +744,7 @@ BaseType_t xWaitConditionMet = pdFALSE; void vEventGroupSetNumber( void * xEventGroup, UBaseType_t uxEventGroupNumber ) { - ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; + ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ } #endif /* configUSE_TRACE_FACILITY */ diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h index f974c73..5a1a497 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -156,6 +156,10 @@ extern "C" { #define INCLUDE_uxTaskGetStackHighWaterMark 0 #endif +#ifndef INCLUDE_uxTaskGetStackHighWaterMark2 + #define INCLUDE_uxTaskGetStackHighWaterMark2 0 +#endif + #ifndef INCLUDE_eTaskGetState #define INCLUDE_eTaskGetState 0 #endif @@ -237,6 +241,26 @@ extern "C" { #define configASSERT_DEFINED 1 #endif +/* configPRECONDITION should be defined as configASSERT. +The CBMC proofs need a way to track assumptions and assertions. +A configPRECONDITION statement should express an implicit invariant or +assumption made. A configASSERT statement should express an invariant that must +hold explicit before calling the code. */ +#ifndef configPRECONDITION + #define configPRECONDITION( X ) configASSERT(X) + #define configPRECONDITION_DEFINED 0 +#else + #define configPRECONDITION_DEFINED 1 +#endif + +#ifndef portMEMORY_BARRIER + #define portMEMORY_BARRIER() +#endif + +#ifndef portSOFTWARE_BARRIER + #define portSOFTWARE_BARRIER() +#endif + /* The timers module relies on xTaskGetSchedulerState(). */ #if configUSE_TIMERS == 1 @@ -758,8 +782,12 @@ extern "C" { #define portTASK_USES_FLOATING_POINT() #endif -#ifndef portTASK_CALLS_SECURE_FUNCTIONS - #define portTASK_CALLS_SECURE_FUNCTIONS() +#ifndef portALLOCATE_SECURE_CONTEXT + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) +#endif + +#ifndef portDONT_DISCARD + #define portDONT_DISCARD #endif #ifndef configUSE_TIME_SLICING @@ -806,6 +834,10 @@ extern "C" { #define configUSE_TASK_NOTIFICATIONS 1 #endif +#ifndef configUSE_POSIX_ERRNO + #define configUSE_POSIX_ERRNO 0 +#endif + #ifndef portTICK_TYPE_IS_ATOMIC #define portTICK_TYPE_IS_ATOMIC 0 #endif @@ -826,6 +858,13 @@ extern "C" { #define configSTACK_DEPTH_TYPE uint16_t #endif +#ifndef configMESSAGE_BUFFER_LENGTH_TYPE + /* Defaults to size_t for backward compatibility, but can be overridden + in FreeRTOSConfig.h if lengths will always be less than the number of bytes + in a size_t. */ + #define configMESSAGE_BUFFER_LENGTH_TYPE size_t +#endif + /* Sanity check the configuration. */ #if( configUSE_TICKLESS_IDLE != 0 ) #if( INCLUDE_vTaskSuspend != 1 ) @@ -914,6 +953,7 @@ V8 if desired. */ #define pcTimerGetTimerName pcTimerGetName #define pcQueueGetQueueName pcQueueGetName #define vTaskGetTaskInfo vTaskGetInfo + #define xTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter /* Backward compatibility within the scheduler code only - these definitions are not really required but are included for completeness. */ @@ -921,6 +961,10 @@ V8 if desired. */ #define pdTASK_CODE TaskFunction_t #define xListItem ListItem_t #define xList List_t + + /* For libraries that break the list data hiding, and access list structure + members directly (which is not supposed to be done). */ + #define pxContainer pvContainer #endif /* configENABLE_BACKWARD_COMPATIBILITY */ #if( configUSE_ALTERNATIVE_API != 0 ) @@ -935,6 +979,75 @@ point support. */ #define configUSE_TASK_FPU_SUPPORT 1 #endif +/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is +currently used in ARMv8M ports. */ +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif + +/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is +currently used in ARMv8M ports. */ +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif + +/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it. +This is currently used in ARMv8M ports. */ +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 1 +#endif + +/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on +the Secure Side only. */ +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 0 +#endif + +/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using + * dynamically allocated RAM, in which case when any task is deleted it is known + * that both the task's stack and TCB need to be freed. Sometimes the + * FreeRTOSConfig.h settings only allow a task to be created using statically + * allocated RAM, in which case when any task is deleted it is known that neither + * the task's stack or TCB should be freed. Sometimes the FreeRTOSConfig.h + * settings allow a task to be created using either statically or dynamically + * allocated RAM, in which case a member of the TCB is used to record whether the + * stack and/or TCB were allocated statically or dynamically, so when a task is + * deleted the RAM that was allocated dynamically is freed again and no attempt is + * made to free the RAM that was allocated statically. + * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a + * task to be created using either statically or dynamically allocated RAM. Note + * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with + * a statically allocated stack and a dynamically allocated TCB. + * + * The following table lists various combinations of portUSING_MPU_WRAPPERS, + * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and + * when it is possible to have both static and dynamic allocation: + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | MPU | Dynamic | Static | Available Functions | Possible Allocations | Both Dynamic and | Need Free | + * | | | | | | Static Possible | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | 0 | 0 | 1 | xTaskCreateStatic | TCB - Static, Stack - Static | No | No | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 0 | xTaskCreate | TCB - Dynamic, Stack - Dynamic | No | Yes | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic | 2. TCB - Static, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 0 | 1 | xTaskCreateStatic, | TCB - Static, Stack - Static | No | No | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 0 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateRestricted | 2. TCB - Dynamic, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic, | 2. TCB - Dynamic, Stack - Static | | | + * | | | | xTaskCreateRestricted, | 3. TCB - Static, Stack - Static | | | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + */ +#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \ + ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) ) + /* * In line with software engineering best practice, FreeRTOS implements a strict * data hiding policy, so the real structures used by FreeRTOS to maintain the @@ -947,25 +1060,40 @@ point support. */ */ struct xSTATIC_LIST_ITEM { - TickType_t xDummy1; - void *pvDummy2[ 4 ]; + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void *pvDummy3[ 4 ]; + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy4; + #endif }; typedef struct xSTATIC_LIST_ITEM StaticListItem_t; /* See the comments above the struct xSTATIC_LIST_ITEM definition. */ struct xSTATIC_MINI_LIST_ITEM { - TickType_t xDummy1; - void *pvDummy2[ 2 ]; + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void *pvDummy3[ 2 ]; }; typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t; /* See the comments above the struct xSTATIC_LIST_ITEM definition. */ typedef struct xSTATIC_LIST { - UBaseType_t uxDummy1; - void *pvDummy2; - StaticMiniListItem_t xDummy3; + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + UBaseType_t uxDummy2; + void *pvDummy3; + StaticMiniListItem_t xDummy4; + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy5; + #endif } StaticList_t; /* @@ -1019,14 +1147,16 @@ typedef struct xSTATIC_TCB uint32_t ulDummy18; uint8_t ucDummy19; #endif - #if( ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) || ( portUSING_MPU_WRAPPERS == 1 ) ) + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) uint8_t uxDummy20; #endif #if( INCLUDE_xTaskAbortDelay == 1 ) uint8_t ucDummy21; #endif - + #if ( configUSE_POSIX_ERRNO == 1 ) + int iDummy22; + #endif } StaticTask_t; /* @@ -1121,15 +1251,12 @@ typedef struct xSTATIC_TIMER void *pvDummy1; StaticListItem_t xDummy2; TickType_t xDummy3; - UBaseType_t uxDummy4; - void *pvDummy5[ 2 ]; + void *pvDummy5; + TaskFunction_t pvDummy6; #if( configUSE_TRACE_FACILITY == 1 ) - UBaseType_t uxDummy6; - #endif - - #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) - uint8_t ucDummy7; + UBaseType_t uxDummy7; #endif + uint8_t ucDummy8; } StaticTimer_t; diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h index fd6b340..ac94611 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/atomic.h b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/atomic.h new file mode 100644 index 0000000..795d801 --- /dev/null +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/atomic.h @@ -0,0 +1,414 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/** + * @file atomic.h + * @brief FreeRTOS atomic operation support. + * + * This file implements atomic functions by disabling interrupts globally. + * Implementations with architecture specific atomic instructions can be + * provided under each compiler directory. + */ + +#ifndef ATOMIC_H +#define ATOMIC_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include atomic.h" +#endif + +/* Standard includes. */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Port specific definitions -- entering/exiting critical section. + * Refer template -- ./lib/FreeRTOS/portable/Compiler/Arch/portmacro.h + * + * Every call to ATOMIC_EXIT_CRITICAL() must be closely paired with + * ATOMIC_ENTER_CRITICAL(). + * + */ +#if defined( portSET_INTERRUPT_MASK_FROM_ISR ) + + /* Nested interrupt scheme is supported in this port. */ + #define ATOMIC_ENTER_CRITICAL() \ + UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR() + + #define ATOMIC_EXIT_CRITICAL() \ + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType ) + +#else + + /* Nested interrupt scheme is NOT supported in this port. */ + #define ATOMIC_ENTER_CRITICAL() portENTER_CRITICAL() + #define ATOMIC_EXIT_CRITICAL() portEXIT_CRITICAL() + +#endif /* portSET_INTERRUPT_MASK_FROM_ISR() */ + +/* + * Port specific definition -- "always inline". + * Inline is compiler specific, and may not always get inlined depending on your + * optimization level. Also, inline is considered as performance optimization + * for atomic. Thus, if portFORCE_INLINE is not provided by portmacro.h, + * instead of resulting error, simply define it away. + */ +#ifndef portFORCE_INLINE + #define portFORCE_INLINE +#endif + +#define ATOMIC_COMPARE_AND_SWAP_SUCCESS 0x1U /**< Compare and swap succeeded, swapped. */ +#define ATOMIC_COMPARE_AND_SWAP_FAILURE 0x0U /**< Compare and swap failed, did not swap. */ + +/*----------------------------- Swap && CAS ------------------------------*/ + +/** + * Atomic compare-and-swap + * + * @brief Performs an atomic compare-and-swap operation on the specified values. + * + * @param[in, out] pulDestination Pointer to memory location from where value is + * to be loaded and checked. + * @param[in] ulExchange If condition meets, write this value to memory. + * @param[in] ulComparand Swap condition. + * + * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. + * + * @note This function only swaps *pulDestination with ulExchange, if previous + * *pulDestination value equals ulComparand. + */ +static portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32( uint32_t volatile * pulDestination, + uint32_t ulExchange, + uint32_t ulComparand ) +{ +uint32_t ulReturnValue; + + ATOMIC_ENTER_CRITICAL(); + { + if( *pulDestination == ulComparand ) + { + *pulDestination = ulExchange; + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; + } + else + { + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; + } + } + ATOMIC_EXIT_CRITICAL(); + + return ulReturnValue; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic swap (pointers) + * + * @brief Atomically sets the address pointed to by *ppvDestination to the value + * of *pvExchange. + * + * @param[in, out] ppvDestination Pointer to memory location from where a pointer + * value is to be loaded and written back to. + * @param[in] pvExchange Pointer value to be written to *ppvDestination. + * + * @return The initial value of *ppvDestination. + */ +static portFORCE_INLINE void * Atomic_SwapPointers_p32( void * volatile * ppvDestination, + void * pvExchange ) +{ +void * pReturnValue; + + ATOMIC_ENTER_CRITICAL(); + { + pReturnValue = *ppvDestination; + *ppvDestination = pvExchange; + } + ATOMIC_EXIT_CRITICAL(); + + return pReturnValue; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic compare-and-swap (pointers) + * + * @brief Performs an atomic compare-and-swap operation on the specified pointer + * values. + * + * @param[in, out] ppvDestination Pointer to memory location from where a pointer + * value is to be loaded and checked. + * @param[in] pvExchange If condition meets, write this value to memory. + * @param[in] pvComparand Swap condition. + * + * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. + * + * @note This function only swaps *ppvDestination with pvExchange, if previous + * *ppvDestination value equals pvComparand. + */ +static portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32( void * volatile * ppvDestination, + void * pvExchange, + void * pvComparand ) +{ +uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; + + ATOMIC_ENTER_CRITICAL(); + { + if( *ppvDestination == pvComparand ) + { + *ppvDestination = pvExchange; + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; + } + } + ATOMIC_EXIT_CRITICAL(); + + return ulReturnValue; +} + + +/*----------------------------- Arithmetic ------------------------------*/ + +/** + * Atomic add + * + * @brief Atomically adds count to the value of the specified pointer points to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * @param[in] ulCount Value to be added to *pulAddend. + * + * @return previous *pulAddend value. + */ +static portFORCE_INLINE uint32_t Atomic_Add_u32( uint32_t volatile * pulAddend, + uint32_t ulCount ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend += ulCount; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic subtract + * + * @brief Atomically subtracts count from the value of the specified pointer + * pointers to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * @param[in] ulCount Value to be subtract from *pulAddend. + * + * @return previous *pulAddend value. + */ +static portFORCE_INLINE uint32_t Atomic_Subtract_u32( uint32_t volatile * pulAddend, + uint32_t ulCount ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend -= ulCount; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic increment + * + * @brief Atomically increments the value of the specified pointer points to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * + * @return *pulAddend value before increment. + */ +static portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pulAddend ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend += 1; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic decrement + * + * @brief Atomically decrements the value of the specified pointer points to + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * + * @return *pulAddend value before decrement. + */ +static portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pulAddend ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend -= 1; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} + +/*----------------------------- Bitwise Logical ------------------------------*/ + +/** + * Atomic OR + * + * @brief Performs an atomic OR operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be ORed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_OR_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination |= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic AND + * + * @brief Performs an atomic AND operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be ANDed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_AND_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination &= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic NAND + * + * @brief Performs an atomic NAND operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be NANDed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_NAND_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination = ~( ulCurrent & ulValue ); + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic XOR + * + * @brief Performs an atomic XOR operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be XORed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_XOR_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination ^= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} + +#ifdef __cplusplus +} +#endif + +#endif /* ATOMIC_H */ diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h index aa132bb..ed2c161 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -157,7 +157,7 @@ BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPri } // Alternatively, if you do not require any other part of the idle task to - // execute, the idle task hook can call vCoRoutineScheduler() within an + // execute, the idle task hook can call vCoRoutineSchedule() within an // infinite loop. void vApplicationIdleHook( void ) { diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h index 9dfdf21..e048e6c 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h index 5064404..bf8a985 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -78,7 +78,8 @@ extern "C" { * \defgroup EventGroupHandle_t EventGroupHandle_t * \ingroup EventGroup */ -typedef void * EventGroupHandle_t; +struct EventGroupDef_t; +typedef struct EventGroupDef_t * EventGroupHandle_t; /* * The type that holds event bits always matches TickType_t - therefore the @@ -404,7 +405,7 @@ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBit * \ingroup EventGroup */ #if( configUSE_TRACE_FACILITY == 1 ) - BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION; + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; #else #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ) #endif diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/list.h b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/list.h index 431443f..0598a93 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/list.h +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/list.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -136,6 +136,7 @@ use of FreeRTOS.*/ /* * Definition of the only type of object that a list can contain. */ +struct xLIST; struct xLIST_ITEM { listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ @@ -143,7 +144,7 @@ struct xLIST_ITEM struct xLIST_ITEM * configLIST_VOLATILE pxNext; /*< Pointer to the next ListItem_t in the list. */ struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */ void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ - void * configLIST_VOLATILE pvContainer; /*< Pointer to the list in which this list item is placed (if any). */ + struct xLIST * configLIST_VOLATILE pxContainer; /*< Pointer to the list in which this list item is placed (if any). */ listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ }; typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */ @@ -182,7 +183,7 @@ typedef struct xLIST * Access macro to get the owner of a list item. The owner of a list item * is the object (usually a TCB) that contains the list item. * - * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \page listGET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER * \ingroup LinkedList */ #define listGET_LIST_ITEM_OWNER( pxListItem ) ( ( pxListItem )->pvOwner ) @@ -224,7 +225,7 @@ typedef struct xLIST #define listGET_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext ) /* - * Return the list item at the head of the list. + * Return the next list item. * * \page listGET_NEXT listGET_NEXT * \ingroup LinkedList @@ -246,7 +247,7 @@ typedef struct xLIST * \page listLIST_IS_EMPTY listLIST_IS_EMPTY * \ingroup LinkedList */ -#define listLIST_IS_EMPTY( pxList ) ( ( BaseType_t ) ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ) +#define listLIST_IS_EMPTY( pxList ) ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE ) /* * Access macro to return the number of items in the list. @@ -314,7 +315,7 @@ List_t * const pxConstList = ( pxList ); \ * @param pxListItem The list item we want to know if is in the list. * @return pdTRUE if the list item is in the list, otherwise pdFALSE. */ -#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( BaseType_t ) ( ( pxListItem )->pvContainer == ( void * ) ( pxList ) ) ) +#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) ) /* * Return the list a list item is contained within (referenced from). @@ -322,7 +323,7 @@ List_t * const pxConstList = ( pxList ); \ * @param pxListItem The list item being queried. * @return A pointer to the List_t object that references the pxListItem */ -#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pvContainer ) +#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer ) /* * This provides a crude means of knowing if a list has been initialised, as diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h index 8be9740..b20c09e 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -62,6 +62,10 @@ #ifndef FREERTOS_MESSAGE_BUFFER_H #define FREERTOS_MESSAGE_BUFFER_H +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include message_buffer.h" +#endif + /* Message buffers are built onto of stream buffers. */ #include "stream_buffer.h" @@ -395,10 +399,10 @@ BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE. // priority of the currently executing task was unblocked and a context // switch should be performed to ensure the ISR returns to the unblocked // task. In most FreeRTOS ports this is done by simply passing - // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the + // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the // variables value, and perform the context switch if necessary. Check the // documentation for the port in use for port specific instructions. - taskYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); } * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR @@ -584,10 +588,10 @@ BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE. // priority of the currently executing task was unblocked and a context // switch should be performed to ensure the ISR returns to the unblocked // task. In most FreeRTOS ports this is done by simply passing - // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the + // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the // variables value, and perform the context switch if necessary. Check the // documentation for the port in use for port specific instructions. - taskYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); } * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR @@ -692,6 +696,26 @@ size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) ); * \ingroup MessageBufferManagement */ #define xMessageBufferSpaceAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) +#define xMessageBufferSpacesAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */ + +/** + * message_buffer.h +
+ size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ) );
+ 
+ * Returns the length (in bytes) of the next message in a message buffer. + * Useful if xMessageBufferReceive() returned 0 because the size of the buffer + * passed into xMessageBufferReceive() was too small to hold the next message. + * + * @param xMessageBuffer The handle of the message buffer being queried. + * + * @return The length (in bytes) of the next message in the message buffer, or 0 + * if the message buffer is empty. + * + * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes + * \ingroup MessageBufferManagement + */ +#define xMessageBufferNextLengthBytes( xMessageBuffer ) xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION; /** * message_buffer.h diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h index a08d748..79a185b 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -38,116 +38,121 @@ #define MPU_PROTOTYPES_H /* MPU versions of tasks.h API functions. */ -BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ); -TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ); -BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ); -BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ); -void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ); -void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ); -void MPU_vTaskDelay( const TickType_t xTicksToDelay ); -void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ); -BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ); -UBaseType_t MPU_uxTaskPriorityGet( TaskHandle_t xTask ); -eTaskState MPU_eTaskGetState( TaskHandle_t xTask ); -void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ); -void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ); -void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ); -void MPU_vTaskResume( TaskHandle_t xTaskToResume ); -void MPU_vTaskStartScheduler( void ); -void MPU_vTaskSuspendAll( void ); -BaseType_t MPU_xTaskResumeAll( void ); -TickType_t MPU_xTaskGetTickCount( void ); -UBaseType_t MPU_uxTaskGetNumberOfTasks( void ); -char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ); -TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ); -UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ); -void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ); -TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ); -void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ); -void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ); -BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ); -TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ); -UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ); -void MPU_vTaskList( char * pcWriteBuffer ); -void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ); -BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ); -BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ); -uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ); -BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ); -BaseType_t MPU_xTaskIncrementTick( void ); -TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ); -void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ); -BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ); -void MPU_vTaskMissedYield( void ); -BaseType_t MPU_xTaskGetSchedulerState( void ); +BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL; +char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL; +TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) FREERTOS_SYSTEM_CALL; +void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL; +uint32_t MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +uint32_t MPU_ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) FREERTOS_SYSTEM_CALL; /* MPU versions of queue.h API functions. */ -BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ); -BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ); -BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ); -BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ); -UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ); -UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ); -void MPU_vQueueDelete( QueueHandle_t xQueue ); -QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ); -QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ); -QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ); -QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ); -void* MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ); -BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ); -BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ); -void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ); -void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ); -const char * MPU_pcQueueGetName( QueueHandle_t xQueue ); -QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ); -QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ); -QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ); -BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ); -BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ); -QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ); -BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ); -void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ); -UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ); -uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ); +BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; +QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL; +QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; /* MPU versions of timers.h API functions. */ -TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ); -TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ); -void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ); -void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ); -BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ); -TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ); -BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ); -const char * MPU_pcTimerGetName( TimerHandle_t xTimer ); -TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ); -TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ); -BaseType_t MPU_xTimerCreateTimerTask( void ); -BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ); +TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL; +TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) FREERTOS_SYSTEM_CALL; +void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; /* MPU versions of event_group.h API functions. */ -EventGroupHandle_t MPU_xEventGroupCreate( void ); -EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ); -EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ); -EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ); -EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ); -EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ); -void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ); -UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup ); +EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL; +EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup ) FREERTOS_SYSTEM_CALL; /* MPU versions of message/stream_buffer.h API functions. */ -size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ); -size_t MPU_xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, BaseType_t * const pxHigherPriorityTaskWoken ); -size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ); -size_t MPU_xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, BaseType_t * const pxHigherPriorityTaskWoken ); -void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ); -BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ); -BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ); -BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ); -size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ); -size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ); -BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ); -StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ); -StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ); +size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL; +StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL; +StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL; diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h index 1e97ae4..87a2f2c 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -67,6 +67,7 @@ only for ports that are using the MPU. */ #define pcTaskGetName MPU_pcTaskGetName #define xTaskGetHandle MPU_xTaskGetHandle #define uxTaskGetStackHighWaterMark MPU_uxTaskGetStackHighWaterMark + #define uxTaskGetStackHighWaterMark2 MPU_uxTaskGetStackHighWaterMark2 #define vTaskSetApplicationTaskTag MPU_vTaskSetApplicationTaskTag #define xTaskGetApplicationTaskTag MPU_xTaskGetApplicationTaskTag #define vTaskSetThreadLocalStoragePointer MPU_vTaskSetThreadLocalStoragePointer @@ -76,10 +77,13 @@ only for ports that are using the MPU. */ #define uxTaskGetSystemState MPU_uxTaskGetSystemState #define vTaskList MPU_vTaskList #define vTaskGetRunTimeStats MPU_vTaskGetRunTimeStats + #define ulTaskGetIdleRunTimeCounter MPU_ulTaskGetIdleRunTimeCounter #define xTaskGenericNotify MPU_xTaskGenericNotify #define xTaskNotifyWait MPU_xTaskNotifyWait #define ulTaskNotifyTake MPU_ulTaskNotifyTake #define xTaskNotifyStateClear MPU_xTaskNotifyStateClear + #define ulTaskNotifyValueClear MPU_ulTaskNotifyValueClear + #define xTaskCatchUpTicks MPU_xTaskCatchUpTicks #define xTaskGetCurrentTaskHandle MPU_xTaskGetCurrentTaskHandle #define vTaskSetTimeOutState MPU_vTaskSetTimeOutState @@ -124,6 +128,8 @@ only for ports that are using the MPU. */ #define xTimerGetTimerDaemonTaskHandle MPU_xTimerGetTimerDaemonTaskHandle #define xTimerPendFunctionCall MPU_xTimerPendFunctionCall #define pcTimerGetName MPU_pcTimerGetName + #define vTimerSetReloadMode MPU_vTimerSetReloadMode + #define uxTimerGetReloadMode MPU_uxTimerGetReloadMode #define xTimerGetPeriod MPU_xTimerGetPeriod #define xTimerGetExpiryTime MPU_xTimerGetExpiryTime #define xTimerGenericCommand MPU_xTimerGenericCommand @@ -140,9 +146,8 @@ only for ports that are using the MPU. */ /* Map standard message/stream_buffer.h API functions to the MPU equivalents. */ #define xStreamBufferSend MPU_xStreamBufferSend - #define xStreamBufferSendFromISR MPU_xStreamBufferSendFromISR #define xStreamBufferReceive MPU_xStreamBufferReceive - #define xStreamBufferReceiveFromISR MPU_xStreamBufferReceiveFromISR + #define xStreamBufferNextMessageLengthBytes MPU_xStreamBufferNextMessageLengthBytes #define vStreamBufferDelete MPU_vStreamBufferDelete #define xStreamBufferIsFull MPU_xStreamBufferIsFull #define xStreamBufferIsEmpty MPU_xStreamBufferIsEmpty @@ -159,12 +164,14 @@ only for ports that are using the MPU. */ (useful when using statically allocated objects). */ #define PRIVILEGED_FUNCTION #define PRIVILEGED_DATA __attribute__((section("privileged_data"))) + #define FREERTOS_SYSTEM_CALL #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */ /* Ensure API functions go in the privileged execution section. */ #define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions"))) #define PRIVILEGED_DATA __attribute__((section("privileged_data"))) + #define FREERTOS_SYSTEM_CALL __attribute__((section( "freertos_system_calls"))) #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */ @@ -172,6 +179,7 @@ only for ports that are using the MPU. */ #define PRIVILEGED_FUNCTION #define PRIVILEGED_DATA + #define FREERTOS_SYSTEM_CALL #define portUSING_MPU_WRAPPERS 0 #endif /* portUSING_MPU_WRAPPERS */ diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h index 8aac353..47ceab9 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -84,6 +84,14 @@ must be set in the compiler's include path. */ #define portNUM_CONFIGURABLE_REGIONS 1 #endif +#ifndef portHAS_STACK_OVERFLOW_CHECKING + #define portHAS_STACK_OVERFLOW_CHECKING 0 +#endif + +#ifndef portARCH_NAME + #define portARCH_NAME NULL +#endif + #ifdef __cplusplus extern "C" { #endif @@ -97,18 +105,39 @@ extern "C" { * */ #if( portUSING_MPU_WRAPPERS == 1 ) - StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION; + #if( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION; + #else + StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION; + #endif #else - StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION; + #if( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION; + #else + StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION; + #endif #endif -/* Used by heap_5.c. */ +/* Used by heap_5.c to define the start address and size of each memory region +that together comprise the total FreeRTOS heap space. */ typedef struct HeapRegion { uint8_t *pucStartAddress; size_t xSizeInBytes; } HeapRegion_t; +/* Used to pass information about the heap out of vPortGetHeapStats(). */ +typedef struct xHeapStats +{ + size_t xAvailableHeapSpaceInBytes; /* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */ + size_t xSizeOfLargestFreeBlockInBytes; /* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xSizeOfSmallestFreeBlockInBytes; /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xNumberOfFreeBlocks; /* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xMinimumEverFreeBytesRemaining; /* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */ + size_t xNumberOfSuccessfulAllocations; /* The number of calls to pvPortMalloc() that have returned a valid memory block. */ + size_t xNumberOfSuccessfulFrees; /* The number of calls to vPortFree() that has successfully freed a block of memory. */ +} HeapStats_t; + /* * Used to define multiple heap regions for use by heap_5.c. This function * must be called before any calls to pvPortMalloc() - not creating a task, @@ -122,6 +151,11 @@ typedef struct HeapRegion */ void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION; +/* + * Returns a HeapStats_t structure filled with information about the current + * heap state. + */ +void vPortGetHeapStats( HeapStats_t *pxHeapStats ); /* * Map to the memory management routines required for the port. diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h index d4aa198..75d4155 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h index 2895205..fb82315 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -37,27 +37,29 @@ extern "C" { #endif +#include "task.h" /** * Type by which queues are referenced. For example, a call to xQueueCreate() * returns an QueueHandle_t variable that can then be used as a parameter to * xQueueSend(), xQueueReceive(), etc. */ -typedef void * QueueHandle_t; +struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */ +typedef struct QueueDefinition * QueueHandle_t; /** * Type by which queue sets are referenced. For example, a call to * xQueueCreateSet() returns an xQueueSet variable that can then be used as a * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc. */ -typedef void * QueueSetHandle_t; +typedef struct QueueDefinition * QueueSetHandle_t; /** * Queue sets can contain both queues and semaphores, so the * QueueSetMemberHandle_t is defined as a type to be used where a parameter or * return value can be either an QueueHandle_t or an SemaphoreHandle_t. */ -typedef void * QueueSetMemberHandle_t; +typedef struct QueueDefinition * QueueSetMemberHandle_t; /* For internal use only. */ #define queueSEND_TO_BACK ( ( BaseType_t ) 0 ) @@ -1282,7 +1284,7 @@ uint32_t ulVarToSend, ulValReceived; // name of the yield function required is port specific. if( xHigherPriorityTaskWokenByPost ) { - taskYIELD_YIELD_FROM_ISR(); + portYIELD_FROM_ISR(); } } @@ -1414,15 +1416,15 @@ QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION; QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION; BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; -void* xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; -void* xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; +TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; +TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; /* * For internal use only. Use xSemaphoreTakeMutexRecursive() or * xSemaphoreGiveMutexRecursive() instead of calling these functions directly. */ BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; -BaseType_t xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) PRIVILEGED_FUNCTION; +BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION; /* * Reset a queue back to its original empty state. The return value is now @@ -1453,7 +1455,7 @@ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) PRIVILEGED_FUNCTION * preferably in ROM/Flash), not on the stack. */ #if( configQUEUE_REGISTRY_SIZE > 0 ) - void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ #endif /* diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h index 0f58285..ff21a39 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h index e8515b3..c505574 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -82,10 +82,10 @@ const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \ const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5; \ \ - if( ( pulStack[ 0 ] != ulCheckValue ) || \ - ( pulStack[ 1 ] != ulCheckValue ) || \ - ( pulStack[ 2 ] != ulCheckValue ) || \ - ( pulStack[ 3 ] != ulCheckValue ) ) \ + if( ( pulStack[ 0 ] != ulCheckValue ) || \ + ( pulStack[ 1 ] != ulCheckValue ) || \ + ( pulStack[ 2 ] != ulCheckValue ) || \ + ( pulStack[ 3 ] != ulCheckValue ) ) \ { \ vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ } \ diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h index f967dd2..3605703 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -43,7 +43,7 @@ * (such as xStreamBufferSend()) inside a critical section and set the send * block time to 0. Likewise, if there are to be multiple different readers * then the application writer must place each call to a reading API function - * (such as xStreamBufferRead()) inside a critical section section and set the + * (such as xStreamBufferReceive()) inside a critical section section and set the * receive block time to 0. * */ @@ -51,6 +51,10 @@ #ifndef STREAM_BUFFER_H #define STREAM_BUFFER_H +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include stream_buffer.h" +#endif + #if defined( __cplusplus ) extern "C" { #endif @@ -61,7 +65,8 @@ extern "C" { * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(), * etc. */ -typedef void * StreamBufferHandle_t; +struct StreamBufferDef_t; +typedef struct StreamBufferDef_t * StreamBufferHandle_t; /** @@ -220,7 +225,7 @@ size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ); -
+
* * Sends bytes to a stream buffer. The bytes are copied into the stream buffer. * @@ -236,7 +241,7 @@ size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, * (such as xStreamBufferSend()) inside a critical section and set the send * block time to 0. Likewise, if there are to be multiple different readers * then the application writer must place each call to a reading API function - * (such as xStreamBufferRead()) inside a critical section and set the receive + * (such as xStreamBufferReceive()) inside a critical section and set the receive * block time to 0. * * Use xStreamBufferSend() to write to a stream buffer from a task. Use @@ -317,7 +322,7 @@ size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, BaseType_t *pxHigherPriorityTaskWoken ); -
+
* * Interrupt safe version of the API function that sends a stream of bytes to * the stream buffer. @@ -334,7 +339,7 @@ size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, * (such as xStreamBufferSend()) inside a critical section and set the send * block time to 0. Likewise, if there are to be multiple different readers * then the application writer must place each call to a reading API function - * (such as xStreamBufferRead()) inside a critical section and set the receive + * (such as xStreamBufferReceive()) inside a critical section and set the receive * block time to 0. * * Use xStreamBufferSend() to write to a stream buffer from a task. Use @@ -434,7 +439,7 @@ size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, * (such as xStreamBufferSend()) inside a critical section and set the send * block time to 0. Likewise, if there are to be multiple different readers * then the application writer must place each call to a reading API function - * (such as xStreamBufferRead()) inside a critical section and set the receive + * (such as xStreamBufferReceive()) inside a critical section and set the receive * block time to 0. * * Use xStreamBufferReceive() to read from a stream buffer from a task. Use @@ -839,6 +844,8 @@ StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION; +size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + #if( configUSE_TRACE_FACILITY == 1 ) void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION; UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/task.h b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/task.h index df7ce95..4b8639c 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/task.h +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/task.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -43,11 +43,19 @@ extern "C" { * MACROS AND DEFINITIONS *----------------------------------------------------------*/ -#define tskKERNEL_VERSION_NUMBER "V10.0.1" +#define tskKERNEL_VERSION_NUMBER "V10.3.1" #define tskKERNEL_VERSION_MAJOR 10 -#define tskKERNEL_VERSION_MINOR 0 +#define tskKERNEL_VERSION_MINOR 3 #define tskKERNEL_VERSION_BUILD 1 +/* MPU region parameters passed in ulParameters + * of MemoryRegion_t struct. */ +#define tskMPU_REGION_READ_ONLY ( 1UL << 0UL ) +#define tskMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define tskMPU_REGION_EXECUTE_NEVER ( 1UL << 2UL ) +#define tskMPU_REGION_NORMAL_MEMORY ( 1UL << 3UL ) +#define tskMPU_REGION_DEVICE_MEMORY ( 1UL << 4UL ) + /** * task. h * @@ -58,7 +66,8 @@ extern "C" { * \defgroup TaskHandle_t TaskHandle_t * \ingroup Tasks */ -typedef void * TaskHandle_t; +struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */ +typedef struct tskTaskControlBlock* TaskHandle_t; /* * Defines the prototype to which the application task hook function must @@ -74,7 +83,7 @@ typedef enum eBlocked, /* The task being queried is in the Blocked state. */ eSuspended, /* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */ eDeleted, /* The task being queried has been deleted, but its TCB has not yet been freed. */ - eInvalid /* Used as an 'invalid state' value. */ + eInvalid /* Used as an 'invalid state' value. */ } eTaskState; /* Actions that can be performed when vTaskNotify() is called. */ @@ -113,7 +122,7 @@ typedef struct xTASK_PARAMETERS { TaskFunction_t pvTaskCode; const char * const pcName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ - uint16_t usStackDepth; + configSTACK_DEPTH_TYPE usStackDepth; void *pvParameters; UBaseType_t uxPriority; StackType_t *puxStackBuffer; @@ -135,7 +144,7 @@ typedef struct xTASK_STATUS UBaseType_t uxBasePriority; /* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex. Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */ uint32_t ulRunTimeCounter; /* The total run time allocated to the task so far, as defined by the run time stats clock. See http://www.freertos.org/rtos-run-time-stats.html. Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */ StackType_t *pxStackBase; /* Points to the lowest address of the task's stack area. */ - uint16_t usStackHighWaterMark; /* The minimum amount of stack space that has remained for the task since the task was created. The closer this value is to zero the closer the task has come to overflowing its stack. */ + configSTACK_DEPTH_TYPE usStackHighWaterMark; /* The minimum amount of stack space that has remained for the task since the task was created. The closer this value is to zero the closer the task has come to overflowing its stack. */ } TaskStatus_t; /* Possible return values for eTaskConfirmSleepModeStatus(). */ @@ -305,13 +314,13 @@ is used in assert() statements. */ // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time // the new task attempts to access it. xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle ); - configASSERT( xHandle ); + configASSERT( xHandle ); // Use the handle to delete the task. - if( xHandle != NULL ) - { - vTaskDelete( xHandle ); - } + if( xHandle != NULL ) + { + vTaskDelete( xHandle ); + } } * \defgroup xTaskCreate xTaskCreate @@ -375,9 +384,9 @@ is used in assert() statements. */ * memory to be allocated dynamically. * * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will - * be created and pdPASS is returned. If either pxStackBuffer or pxTaskBuffer - * are NULL then the task will not be created and - * errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY is returned. + * be created and a handle to the created task is returned. If either + * pxStackBuffer or pxTaskBuffer are NULL then the task will not be created and + * NULL is returned. * * Example usage:
@@ -489,9 +498,9 @@ static const TaskParameters_t xCheckTaskParameters =
 	// for full information.
 	{
 		// Base address					Length	Parameters
-        { cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
-        { cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
-        { cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+		{ cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+		{ cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+		{ cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
 	}
 };
 
@@ -575,9 +584,9 @@ static const TaskParameters_t xCheckTaskParameters =
 	// for full information.
 	{
 		// Base address					Length	Parameters
-        { cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
-        { cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
-        { cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+		{ cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+		{ cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+		{ cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
 	}
 
 	&xTaskBuffer; // Holds the task's data structure.
@@ -822,6 +831,11 @@ void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xT
  * task will leave the Blocked state, and return from whichever function call
  * placed the task into the Blocked state.
  *
+ * There is no 'FromISR' version of this function as an interrupt would need to
+ * know which object a task was blocked on in order to know which actions to
+ * take.  For example, if the task was blocked on a queue the interrupt handler
+ * would then need to know if the queue was locked.
+ *
  * @param xTask The handle of the task to remove from the Blocked state.
  *
  * @return If the task referenced by xTask was not in the Blocked state then
@@ -834,7 +848,7 @@ BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
 
 /**
  * task. h
- * 
UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask );
+ *
UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );
* * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available. * See the configuration section for more information. @@ -877,15 +891,15 @@ BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; * \defgroup uxTaskPriorityGet uxTaskPriorityGet * \ingroup TaskCtrl */ -UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; /** * task. h - *
UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask );
+ *
UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );
* * A version of uxTaskPriorityGet() that can be used from an ISR. */ -UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; /** * task. h @@ -1412,6 +1426,12 @@ TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /* * a value of 1 means 4 bytes) since the task started. The smaller the returned * number the closer the task has come to overflowing its stack. * + * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the + * same except for their return type. Using configSTACK_DEPTH_TYPE allows the + * user to determine the return type. It gets around the problem of the value + * overflowing on 8-bit types without breaking backward compatibility for + * applications that expect an 8-bit return type. + * * @param xTask Handle of the task associated with the stack to be checked. * Set xTask to NULL to check the stack of the calling task. * @@ -1421,6 +1441,33 @@ TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /* */ UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +/** + * task.h + *
configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );
+ * + * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for + * this function to be available. + * + * Returns the high water mark of the stack associated with xTask. That is, + * the minimum free stack space there has been (in words, so on a 32 bit machine + * a value of 1 means 4 bytes) since the task started. The smaller the returned + * number the closer the task has come to overflowing its stack. + * + * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the + * same except for their return type. Using configSTACK_DEPTH_TYPE allows the + * user to determine the return type. It gets around the problem of the value + * overflowing on 8-bit types without breaking backward compatibility for + * applications that expect an 8-bit return type. + * + * @param xTask Handle of the task associated with the stack to be checked. + * Set xTask to NULL to check the stack of the calling task. + * + * @return The smallest amount of free stack space there has been (in words, so + * actual spaces on the stack rather than bytes) since the task referenced by + * xTask was created. + */ +configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + /* When using trace macros it is sometimes necessary to include task.h before FreeRTOS.h. When this is done TaskHookFunction_t will not yet have been defined, so the following two prototypes will cause a compilation error. This can be @@ -1443,9 +1490,20 @@ constant. */ * task.h *
void xTaskGetApplicationTaskTag( TaskHandle_t xTask );
* - * Returns the pxHookFunction value assigned to the task xTask. + * Returns the pxHookFunction value assigned to the task xTask. Do not + * call from an interrupt service routine - call + * xTaskGetApplicationTaskTagFromISR() instead. */ TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + + /** + * task.h + *
void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );
+ * + * Returns the pxHookFunction value assigned to the task xTask. Can + * be called from an interrupt service routine. + */ + TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; #endif /* configUSE_APPLICATION_TASK_TAG ==1 */ #endif /* ifdef configUSE_APPLICATION_TASK_TAG */ @@ -1683,6 +1741,36 @@ void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unquali */ void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +/** +* task. h +*
uint32_t ulTaskGetIdleRunTimeCounter( void );
+* +* configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS +* must both be defined as 1 for this function to be available. The application +* must also then provide definitions for +* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE() +* to configure a peripheral timer/counter and return the timers current count +* value respectively. The counter should be at least 10 times the frequency of +* the tick count. +* +* Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total +* accumulated execution time being stored for each task. The resolution +* of the accumulated time value depends on the frequency of the timer +* configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro. +* While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total +* execution time of each task into a buffer, ulTaskGetIdleRunTimeCounter() +* returns the total execution time of just the idle task. +* +* @return The total run time of the idle task. This is the amount of time the +* idle task has actually been executing. The unit of time is dependent on the +* frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and +* portGET_RUN_TIME_COUNTER_VALUE() macros. +* +* \defgroup ulTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter +* \ingroup TaskUtils +*/ +uint32_t ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION; + /** * task. h *
BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );
@@ -2118,6 +2206,121 @@ uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait */ BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask ); +/** +* task. h +*
uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear );
+* +* Clears the bits specified by the ulBitsToClear bit mask in the notification +* value of the task referenced by xTask. +* +* Set ulBitsToClear to 0xffffffff (UINT_MAX on 32-bit architectures) to clear +* the notification value to 0. Set ulBitsToClear to 0 to query the task's +* notification value without clearing any bits. +* +* @return The value of the target task's notification value before the bits +* specified by ulBitsToClear were cleared. +* \defgroup ulTaskNotifyValueClear ulTaskNotifyValueClear +* \ingroup TaskNotifications +*/ +uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; + +/** + * task.h + *
void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
+ * + * Capture the current time for future use with xTaskCheckForTimeOut(). + * + * @param pxTimeOut Pointer to a timeout object into which the current time + * is to be captured. The captured time includes the tick count and the number + * of times the tick count has overflowed since the system first booted. + * \defgroup vTaskSetTimeOutState vTaskSetTimeOutState + * \ingroup TaskCtrl + */ +void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION; + +/** + * task.h + *
BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait );
+ * + * Determines if pxTicksToWait ticks has passed since a time was captured + * using a call to vTaskSetTimeOutState(). The captured time includes the tick + * count and the number of times the tick count has overflowed. + * + * @param pxTimeOut The time status as captured previously using + * vTaskSetTimeOutState. If the timeout has not yet occurred, it is updated + * to reflect the current time status. + * @param pxTicksToWait The number of ticks to check for timeout i.e. if + * pxTicksToWait ticks have passed since pxTimeOut was last updated (either by + * vTaskSetTimeOutState() or xTaskCheckForTimeOut()), the timeout has occurred. + * If the timeout has not occurred, pxTIcksToWait is updated to reflect the + * number of remaining ticks. + * + * @return If timeout has occurred, pdTRUE is returned. Otherwise pdFALSE is + * returned and pxTicksToWait is updated to reflect the number of remaining + * ticks. + * + * @see https://www.freertos.org/xTaskCheckForTimeOut.html + * + * Example Usage: + *
+	// Driver library function used to receive uxWantedBytes from an Rx buffer
+	// that is filled by a UART interrupt. If there are not enough bytes in the
+	// Rx buffer then the task enters the Blocked state until it is notified that
+	// more data has been placed into the buffer. If there is still not enough
+	// data then the task re-enters the Blocked state, and xTaskCheckForTimeOut()
+	// is used to re-calculate the Block time to ensure the total amount of time
+	// spent in the Blocked state does not exceed MAX_TIME_TO_WAIT. This
+	// continues until either the buffer contains at least uxWantedBytes bytes,
+	// or the total amount of time spent in the Blocked state reaches
+	// MAX_TIME_TO_WAIT – at which point the task reads however many bytes are
+	// available up to a maximum of uxWantedBytes.
+
+	size_t xUART_Receive( uint8_t *pucBuffer, size_t uxWantedBytes )
+	{
+	size_t uxReceived = 0;
+	TickType_t xTicksToWait = MAX_TIME_TO_WAIT;
+	TimeOut_t xTimeOut;
+
+		// Initialize xTimeOut.  This records the time at which this function
+		// was entered.
+		vTaskSetTimeOutState( &xTimeOut );
+
+		// Loop until the buffer contains the wanted number of bytes, or a
+		// timeout occurs.
+		while( UART_bytes_in_rx_buffer( pxUARTInstance ) < uxWantedBytes )
+		{
+			// The buffer didn't contain enough data so this task is going to
+			// enter the Blocked state. Adjusting xTicksToWait to account for
+			// any time that has been spent in the Blocked state within this
+			// function so far to ensure the total amount of time spent in the
+			// Blocked state does not exceed MAX_TIME_TO_WAIT.
+			if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) != pdFALSE )
+			{
+				//Timed out before the wanted number of bytes were available,
+				// exit the loop.
+				break;
+			}
+
+			// Wait for a maximum of xTicksToWait ticks to be notified that the
+			// receive interrupt has placed more data into the buffer.
+			ulTaskNotifyTake( pdTRUE, xTicksToWait );
+		}
+
+		// Attempt to read uxWantedBytes from the receive buffer into pucBuffer.
+		// The actual number of bytes read (which might be less than
+		// uxWantedBytes) is returned.
+		uxReceived = UART_read_from_receive_buffer( pxUARTInstance,
+													pucBuffer,
+													uxWantedBytes );
+
+		return uxReceived;
+	}
+ 
+ * \defgroup xTaskCheckForTimeOut xTaskCheckForTimeOut + * \ingroup TaskCtrl + */ +BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION; + /*----------------------------------------------------------- * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES *----------------------------------------------------------*/ @@ -2221,7 +2424,7 @@ void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const Tick * Sets the pointer to the current TCB to the TCB of the highest priority task * that is ready to run. */ -void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION; +portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION; /* * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE. THEY ARE USED BY @@ -2234,17 +2437,6 @@ TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION; */ TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION; -/* - * Capture the current time status for future reference. - */ -void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION; - -/* - * Compare the time status now with that previously captured to see if the - * timeout has expired. - */ -BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION; - /* * Shortcut used by the queue implementation to prevent unnecessary call to * taskYIELD(); @@ -2300,8 +2492,21 @@ void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVIL */ void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION; +/* Correct the tick count value after the application code has held +interrupts disabled for an extended period. xTicksToCatchUp is the number +of tick interrupts that have been missed due to interrupts being disabled. +Its value is not computed automatically, so must be computed by the +application writer. + +This function is similar to vTaskStepTick(), however, unlike +vTaskStepTick(), xTaskCatchUpTicks() may move the tick count forward past a +time at which a task should be removed from the blocked state. That means +tasks may have to be removed from the blocked state as the tick count is +moved. */ +BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) PRIVILEGED_FUNCTION; + /* - * Only avilable when configUSE_TICKLESS_IDLE is set to 1. + * Only available when configUSE_TICKLESS_IDLE is set to 1. * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port * specific sleep function to determine if it is ok to proceed with the sleep, * and if it is ok to proceed, if it is ok to sleep indefinitely. @@ -2320,7 +2525,7 @@ eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION; * For internal use only. Increment the mutex held count when a mutex is * taken and return the handle of the task that has taken the mutex. */ -void *pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION; +TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION; /* * For internal use only. Same as vTaskSetTimeOutState(), but without a critial diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h index 7e2eceb..9ee2a0c 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -73,7 +73,8 @@ or interrupt version of the queue send function should be used. */ * reference the subject timer in calls to other software timer API functions * (for example, xTimerStart(), xTimerReset(), etc.). */ -typedef void * TimerHandle_t; +struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */ +typedef struct tmrTimerControl * TimerHandle_t; /* * Defines the prototype to which timer callback functions must conform. @@ -120,7 +121,7 @@ typedef void (*PendedFunction_t)( void *, uint32_t ); * after 100 ticks, then xTimerPeriodInTicks should be set to 100. * Alternatively, if the timer must expire after 500ms, then xPeriod can be set * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or - * equal to 1000. + * equal to 1000. Time timer period must be greater than 0. * * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter. @@ -137,9 +138,9 @@ typedef void (*PendedFunction_t)( void *, uint32_t ); * which is "void vCallbackFunction( TimerHandle_t xTimer );". * * @return If the timer is successfully created then a handle to the newly - * created timer is returned. If the timer cannot be created (because either - * there is insufficient FreeRTOS heap remaining to allocate the timer - * structures, or the timer period was set to 0) then NULL is returned. + * created timer is returned. If the timer cannot be created because there is + * insufficient FreeRTOS heap remaining to allocate the timer + * structures then NULL is returned. * * Example usage: * @verbatim @@ -266,7 +267,7 @@ typedef void (*PendedFunction_t)( void *, uint32_t ); * after 100 ticks, then xTimerPeriodInTicks should be set to 100. * Alternatively, if the timer must expire after 500ms, then xPeriod can be set * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or - * equal to 1000. + * equal to 1000. The timer period must be greater than 0. * * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter. @@ -1230,6 +1231,37 @@ BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvPar */ const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +/** + * void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ); + * + * Updates a timer to be either an auto-reload timer, in which case the timer + * automatically resets itself each time it expires, or a one-shot timer, in + * which case the timer will only expire once unless it is manually restarted. + * + * @param xTimer The handle of the timer being updated. + * + * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will + * expire repeatedly with a frequency set by the timer's period (see the + * xTimerPeriodInTicks parameter of the xTimerCreate() API function). If + * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and + * enter the dormant state after it expires. + */ +void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION; + +/** +* UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ); +* +* Queries a timer to determine if it is an auto-reload timer, in which case the timer +* automatically resets itself each time it expires, or a one-shot timer, in +* which case the timer will only expire once unless it is manually restarted. +* +* @param xTimer The handle of the timer being queried. +* +* @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise +* pdFALSE is returned. +*/ +UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + /** * TickType_t xTimerGetPeriod( TimerHandle_t xTimer ); * diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/list.c b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/list.c index e3a54e3..0e0e72d 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/list.c +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/list.c @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -39,7 +39,7 @@ void vListInitialise( List_t * const pxList ) /* The list structure contains a list item which is used to mark the end of the list. To initialise the list the list end is inserted as the only list entry. */ - pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ /* The list end value is the highest possible value in the list to ensure it remains at the end of the list. */ @@ -47,8 +47,8 @@ void vListInitialise( List_t * const pxList ) /* The list end next and previous pointers point to itself so we know when the list is empty. */ - pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */ - pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ pxList->uxNumberOfItems = ( UBaseType_t ) 0U; @@ -62,7 +62,7 @@ void vListInitialise( List_t * const pxList ) void vListInitialiseItem( ListItem_t * const pxItem ) { /* Make sure the list item is not recorded as being on a list. */ - pxItem->pvContainer = NULL; + pxItem->pxContainer = NULL; /* Write known values into the list item if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ @@ -94,7 +94,7 @@ ListItem_t * const pxIndex = pxList->pxIndex; pxIndex->pxPrevious = pxNewListItem; /* Remember which list the item is in. */ - pxNewListItem->pvContainer = ( void * ) pxList; + pxNewListItem->pxContainer = pxList; ( pxList->uxNumberOfItems )++; } @@ -114,7 +114,7 @@ const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; /* Insert the new list item into the list, sorted in xItemValue order. If the list already contains a list item with the same item value then the - new list item should be placed after it. This ensures that TCB's which are + new list item should be placed after it. This ensures that TCBs which are stored in ready lists (all of which have the same xItemValue value) get a share of the CPU. However, if the xItemValue is the same as the back marker the iteration loop below will not end. Therefore the value is checked @@ -127,18 +127,18 @@ const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; { /* *** NOTE *********************************************************** If you find your application is crashing here then likely causes are - listed below. In addition see http://www.freertos.org/FAQHelp.html for + listed below. In addition see https://www.freertos.org/FAQHelp.html for more tips, and ensure configASSERT() is defined! - http://www.freertos.org/a00110.html#configASSERT + https://www.freertos.org/a00110.html#configASSERT 1) Stack overflow - - see http://www.freertos.org/Stacks-and-stack-overflow-checking.html + see https://www.freertos.org/Stacks-and-stack-overflow-checking.html 2) Incorrect interrupt priority assignment, especially on Cortex-M parts where numerically high priority values denote low actual interrupt priorities, which can seem counter intuitive. See - http://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition + https://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition of configMAX_SYSCALL_INTERRUPT_PRIORITY on - http://www.freertos.org/a00110.html + https://www.freertos.org/a00110.html 3) Calling an API function from within a critical section or when the scheduler is suspended, or calling an API function that does not end in "FromISR" from an interrupt. @@ -147,7 +147,7 @@ const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; before vTaskStartScheduler() has been called?). **********************************************************************/ - for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ { /* There is nothing to do here, just iterating to the wanted insertion position. */ @@ -161,7 +161,7 @@ const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; /* Remember which list the item is in. This allows fast removal of the item later. */ - pxNewListItem->pvContainer = ( void * ) pxList; + pxNewListItem->pxContainer = pxList; ( pxList->uxNumberOfItems )++; } @@ -171,7 +171,7 @@ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) { /* The list item knows which list it is in. Obtain the list from the list item. */ -List_t * const pxList = ( List_t * ) pxItemToRemove->pvContainer; +List_t * const pxList = pxItemToRemove->pxContainer; pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; @@ -189,7 +189,7 @@ List_t * const pxList = ( List_t * ) pxItemToRemove->pvContainer; mtCOVERAGE_TEST_MARKER(); } - pxItemToRemove->pvContainer = NULL; + pxItemToRemove->pxContainer = NULL; ( pxList->uxNumberOfItems )--; return pxList->uxNumberOfItems; diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c index e18d94e..9e1d1a8 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -576,14 +576,14 @@ void xPortSysTickHandler( void ) should not be executed again. However, the original expected idle time variable must remain unmodified, so a copy is taken. */ xModifiableIdleTime = xExpectedIdleTime; - configPRE_SLEEP_PROCESSING( &xModifiableIdleTime ); + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); if( xModifiableIdleTime > 0 ) { __asm volatile( "dsb" ::: "memory" ); __asm volatile( "wfi" ); __asm volatile( "isb" ); } - configPOST_SLEEP_PROCESSING( &xExpectedIdleTime ); + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); /* Re-enable interrupts to allow the interrupt that brought the MCU out of sleep mode to execute immediately. see comments above @@ -664,7 +664,7 @@ void xPortSysTickHandler( void ) vTaskStepTick( ulCompleteTickPeriods ); portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; - /* Exit with interrpts enabled. */ + /* Exit with interrupts enabled. */ __asm volatile( "cpsie i" ::: "memory" ); } } diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h index 335732f..e1e7fad 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -233,6 +233,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) } /*-----------------------------------------------------------*/ +#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) #ifdef __cplusplus } diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/queue.c b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/queue.c index f6d1450..e35055f 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/queue.c +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/queue.c @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -41,11 +41,11 @@ task.h is included from an application file. */ #include "croutine.h" #endif -/* Lint e961 and e750 are suppressed as a MISRA exception justified because the -MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the -header files above, but not in this file, in order to generate the correct -privileged Vs unprivileged linkage and placement. */ -#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */ +/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified +because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined +for the header files above, but not in this file, in order to generate the +correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ /* Constants used with the cRxLock and cTxLock structure members. */ @@ -56,17 +56,26 @@ privileged Vs unprivileged linkage and placement. */ pcTail members are used as pointers into the queue storage area. When the Queue_t structure is used to represent a mutex pcHead and pcTail pointers are not necessary, and the pcHead pointer is set to NULL to indicate that the -pcTail pointer actually points to the mutex holder (if any). Map alternative -names to the pcHead and pcTail structure members to ensure the readability of -the code is maintained despite this dual use of two structure members. An -alternative implementation would be to use a union, but use of a union is -against the coding standard (although an exception to the standard has been -permitted where the dual use also significantly changes the type of the -structure member). */ -#define pxMutexHolder pcTail +structure instead holds a pointer to the mutex holder (if any). Map alternative +names to the pcHead and structure member to ensure the readability of the code +is maintained. The QueuePointers_t and SemaphoreData_t types are used to form +a union as their usage is mutually exclusive dependent on what the queue is +being used for. */ #define uxQueueType pcHead #define queueQUEUE_IS_MUTEX NULL +typedef struct QueuePointers +{ + int8_t *pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */ + int8_t *pcReadFrom; /*< Points to the last place that a queued item was read from when the structure is used as a queue. */ +} QueuePointers_t; + +typedef struct SemaphoreData +{ + TaskHandle_t xMutexHolder; /*< The handle of the task that holds the mutex. */ + UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */ +} SemaphoreData_t; + /* Semaphores do not actually store or copy data, so have an item size of zero. */ #define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 ) @@ -83,18 +92,17 @@ zero. */ /* * Definition of the queue used by the scheduler. * Items are queued by copy, not reference. See the following link for the - * rationale: http://www.freertos.org/Embedded-RTOS-Queues.html + * rationale: https://www.freertos.org/Embedded-RTOS-Queues.html */ -typedef struct QueueDefinition +typedef struct QueueDefinition /* The old naming convention is used to prevent breaking kernel aware debuggers. */ { int8_t *pcHead; /*< Points to the beginning of the queue storage area. */ - int8_t *pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */ int8_t *pcWriteTo; /*< Points to the free next place in the storage area. */ - union /* Use of a union is an exception to the coding standard to ensure two mutually exclusive structure members don't appear simultaneously (wasting RAM). */ + union { - int8_t *pcReadFrom; /*< Points to the last place that a queued item was read from when the structure is used as a queue. */ - UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */ + QueuePointers_t xQueue; /*< Data required exclusively when this structure is used as a queue. */ + SemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */ } u; List_t xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */ @@ -195,7 +203,7 @@ static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer * Checks to see if a queue is a member of a queue set, and if so, notifies * the queue set that the queue contains data. */ - static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION; + static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION; #endif /* @@ -246,16 +254,16 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) { -Queue_t * const pxQueue = ( Queue_t * ) xQueue; +Queue_t * const pxQueue = xQueue; configASSERT( pxQueue ); taskENTER_CRITICAL(); { - pxQueue->pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); + pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; pxQueue->pcWriteTo = pxQueue->pcHead; - pxQueue->u.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - ( UBaseType_t ) 1U ) * pxQueue->uxItemSize ); + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ pxQueue->cRxLock = queueUNLOCKED; pxQueue->cTxLock = queueUNLOCKED; @@ -321,13 +329,14 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; the real queue and semaphore structures. */ volatile size_t xSize = sizeof( StaticQueue_t ); configASSERT( xSize == sizeof( Queue_t ) ); + ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ } #endif /* configASSERT_DEFINED */ /* The address of a statically allocated queue was passed in, use it. The address of a statically allocated storage area was also passed in but is already set. */ - pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ + pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ if( pxNewQueue != NULL ) { @@ -345,6 +354,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; else { traceQUEUE_CREATE_FAILED( ucQueueType ); + mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; @@ -363,25 +373,28 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); - if( uxItemSize == ( UBaseType_t ) 0 ) - { - /* There is not going to be a queue storage area. */ - xQueueSizeInBytes = ( size_t ) 0; - } - else - { - /* Allocate enough space to hold the maximum number of items that - can be in the queue at any time. */ - xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ - } + /* Allocate enough space to hold the maximum number of items that + can be in the queue at any time. It is valid for uxItemSize to be + zero in the case the queue is used as a semaphore. */ + xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ - pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); + /* Allocate the queue and storage area. Justification for MISRA + deviation as follows: pvPortMalloc() always ensures returned memory + blocks are aligned per the requirements of the MCU stack. In this case + pvPortMalloc() must return a pointer that is guaranteed to meet the + alignment requirements of the Queue_t structure - which in this case + is an int8_t *. Therefore, whenever the stack alignment requirements + are greater than or equal to the pointer to char requirements the cast + is safe. In other cases alignment requirements are not strict (one or + two bytes). */ + pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */ if( pxNewQueue != NULL ) { /* Jump past the queue structure to find the location of the queue storage area. */ - pucQueueStorage = ( ( uint8_t * ) pxNewQueue ) + sizeof( Queue_t ); + pucQueueStorage = ( uint8_t * ) pxNewQueue; + pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { @@ -397,6 +410,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; else { traceQUEUE_CREATE_FAILED( ucQueueType ); + mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; @@ -457,11 +471,11 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT correctly for a generic queue, but this function is creating a mutex. Overwrite those members that need to be set differently - in particular the information required for priority inheritance. */ - pxNewQueue->pxMutexHolder = NULL; + pxNewQueue->u.xSemaphore.xMutexHolder = NULL; pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; /* In case this is a recursive mutex. */ - pxNewQueue->u.uxRecursiveCallCount = 0; + pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0; traceCREATE_MUTEX( pxNewQueue ); @@ -481,13 +495,13 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) { - Queue_t *pxNewQueue; + QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; - pxNewQueue = ( Queue_t * ) xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType ); - prvInitialiseMutex( pxNewQueue ); + xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType ); + prvInitialiseMutex( ( Queue_t * ) xNewQueue ); - return pxNewQueue; + return xNewQueue; } #endif /* configUSE_MUTEXES */ @@ -497,17 +511,17 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) { - Queue_t *pxNewQueue; + QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; /* Prevent compiler warnings about unused parameters if configUSE_TRACE_FACILITY does not equal 1. */ ( void ) ucQueueType; - pxNewQueue = ( Queue_t * ) xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType ); - prvInitialiseMutex( pxNewQueue ); + xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType ); + prvInitialiseMutex( ( Queue_t * ) xNewQueue ); - return pxNewQueue; + return xNewQueue; } #endif /* configUSE_MUTEXES */ @@ -515,9 +529,10 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) - void* xQueueGetMutexHolder( QueueHandle_t xSemaphore ) + TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) { - void *pxReturn; + TaskHandle_t pxReturn; + Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore; /* This function is called by xSemaphoreGetMutexHolder(), and should not be called directly. Note: This is a good way of determining if the @@ -526,9 +541,9 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT following critical section exiting and the function returning. */ taskENTER_CRITICAL(); { - if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX ) + if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX ) { - pxReturn = ( void * ) ( ( Queue_t * ) xSemaphore )->pxMutexHolder; + pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder; } else { @@ -545,9 +560,9 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) - void* xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) + TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) { - void *pxReturn; + TaskHandle_t pxReturn; configASSERT( xSemaphore ); @@ -556,7 +571,7 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT not required here. */ if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX ) { - pxReturn = ( void * ) ( ( Queue_t * ) xSemaphore )->pxMutexHolder; + pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder; } else { @@ -578,25 +593,25 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT configASSERT( pxMutex ); - /* If this is the task that holds the mutex then pxMutexHolder will not + /* If this is the task that holds the mutex then xMutexHolder will not change outside of this task. If this task does not hold the mutex then pxMutexHolder can never coincidentally equal the tasks handle, and as this is the only condition we are interested in it does not matter if pxMutexHolder is accessed simultaneously by another task. Therefore no mutual exclusion is required to test the pxMutexHolder variable. */ - if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Not a redundant cast as TaskHandle_t is a typedef. */ + if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) { traceGIVE_MUTEX_RECURSIVE( pxMutex ); - /* uxRecursiveCallCount cannot be zero if pxMutexHolder is equal to + /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to the task handle, therefore no underflow check is required. Also, uxRecursiveCallCount is only modified by the mutex holder, and as there can only be one, no mutual exclusion is required to modify the uxRecursiveCallCount member. */ - ( pxMutex->u.uxRecursiveCallCount )--; + ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--; /* Has the recursive call count unwound to 0? */ - if( pxMutex->u.uxRecursiveCallCount == ( UBaseType_t ) 0 ) + if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 ) { /* Return the mutex. This will automatically unblock any other task that might be waiting to access the mutex. */ @@ -638,9 +653,9 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT traceTAKE_MUTEX_RECURSIVE( pxMutex ); - if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */ + if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) { - ( pxMutex->u.uxRecursiveCallCount )++; + ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; xReturn = pdPASS; } else @@ -652,7 +667,7 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT before reaching here. */ if( xReturn != pdFAIL ) { - ( pxMutex->u.uxRecursiveCallCount )++; + ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; } else { @@ -726,7 +741,7 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQ { BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; TimeOut_t xTimeOut; -Queue_t * const pxQueue = ( Queue_t * ) xQueue; +Queue_t * const pxQueue = xQueue; configASSERT( pxQueue ); configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); @@ -738,9 +753,9 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; #endif - /* This function relaxes the coding standard somewhat to allow return - statements within the function itself. This is done in the interest - of execution time efficiency. */ + /*lint -save -e904 This function relaxes the coding standard somewhat to + allow return statements within the function itself. This is done in the + interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); @@ -752,13 +767,23 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) { traceQUEUE_SEND( pxQueue ); - xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); #if ( configUSE_QUEUE_SETS == 1 ) { + const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; + + xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + if( pxQueue->pxQueueSetContainer != NULL ) { - if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE ) + if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) ) + { + /* Do not notify the queue set as an existing item + was overwritten in the queue so the number of items + in the queue has not changed. */ + mtCOVERAGE_TEST_MARKER(); + } + else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) { /* The queue is a member of a queue set, and posting to the queue set caused a higher priority task to @@ -805,6 +830,8 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; } #else /* configUSE_QUEUE_SETS */ { + xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + /* If there was a task waiting for data to arrive on the queue then unblock it now. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) @@ -916,7 +943,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; } - } + } /*lint -restore */ } /*-----------------------------------------------------------*/ @@ -924,7 +951,7 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pv { BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; -Queue_t * const pxQueue = ( Queue_t * ) xQueue; +Queue_t * const pxQueue = xQueue; configASSERT( pxQueue ); configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); @@ -956,6 +983,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) { const int8_t cTxLock = pxQueue->cTxLock; + const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; traceQUEUE_SEND_FROM_ISR( pxQueue ); @@ -974,7 +1002,14 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; { if( pxQueue->pxQueueSetContainer != NULL ) { - if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE ) + if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) ) + { + /* Do not notify the queue set as an existing item + was overwritten in the queue so the number of items + in the queue has not changed. */ + mtCOVERAGE_TEST_MARKER(); + } + else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) { /* The queue is a member of a queue set, and posting to the queue set caused a higher priority task to @@ -1047,6 +1082,9 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; { mtCOVERAGE_TEST_MARKER(); } + + /* Not used in this path. */ + ( void ) uxPreviousMessagesWaiting; } #endif /* configUSE_QUEUE_SETS */ } @@ -1075,7 +1113,7 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherP { BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; -Queue_t * const pxQueue = ( Queue_t * ) xQueue; +Queue_t * const pxQueue = xQueue; /* Similar to xQueueGenericSendFromISR() but used with semaphores where the item size is 0. Don't directly wake a task that was blocked on a queue @@ -1092,7 +1130,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; /* Normally a mutex would not be given from an interrupt, especially if there is a mutex holder, as priority inheritance makes no sense for an interrupts, only tasks. */ - configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->pxMutexHolder != NULL ) ) ); + configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) ); /* RTOS ports that support interrupt nesting have the concept of a maximum system call (or maximum API call) interrupt priority. Interrupts that are @@ -1139,7 +1177,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; { if( pxQueue->pxQueueSetContainer != NULL ) { - if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) != pdFALSE ) + if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) { /* The semaphore is a member of a queue set, and posting to the queue set caused a higher priority @@ -1240,7 +1278,7 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_ { BaseType_t xEntryTimeSet = pdFALSE; TimeOut_t xTimeOut; -Queue_t * const pxQueue = ( Queue_t * ) xQueue; +Queue_t * const pxQueue = xQueue; /* Check the pointer is not NULL. */ configASSERT( ( pxQueue ) ); @@ -1256,10 +1294,10 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; } #endif - /* This function relaxes the coding standard somewhat to allow return - statements within the function itself. This is done in the interest - of execution time efficiency. */ + /*lint -save -e904 This function relaxes the coding standard somewhat to + allow return statements within the function itself. This is done in the + interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); @@ -1373,7 +1411,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; mtCOVERAGE_TEST_MARKER(); } } - } + } /*lint -restore */ } /*-----------------------------------------------------------*/ @@ -1381,7 +1419,7 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) { BaseType_t xEntryTimeSet = pdFALSE; TimeOut_t xTimeOut; -Queue_t * const pxQueue = ( Queue_t * ) xQueue; +Queue_t * const pxQueue = xQueue; #if( configUSE_MUTEXES == 1 ) BaseType_t xInheritanceOccurred = pdFALSE; @@ -1402,10 +1440,9 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; #endif - /* This function relaxes the coding standard somewhat to allow return + /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ - for( ;; ) { taskENTER_CRITICAL(); @@ -1430,7 +1467,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; { /* Record the information required to implement priority inheritance should it become necessary. */ - pxQueue->pxMutexHolder = ( int8_t * ) pvTaskIncrementMutexHeldCount(); /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */ + pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount(); } else { @@ -1518,7 +1555,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; { taskENTER_CRITICAL(); { - xInheritanceOccurred = xTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder ); + xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder ); } taskEXIT_CRITICAL(); } @@ -1577,7 +1614,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; again, but only as low as the next highest priority task that is waiting for the same mutex. */ uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue ); - vTaskPriorityDisinheritAfterTimeout( ( void * ) pxQueue->pxMutexHolder, uxHighestWaitingPriority ); + vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority ); } taskEXIT_CRITICAL(); } @@ -1592,7 +1629,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; mtCOVERAGE_TEST_MARKER(); } } - } + } /*lint -restore */ } /*-----------------------------------------------------------*/ @@ -1601,7 +1638,7 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t x BaseType_t xEntryTimeSet = pdFALSE; TimeOut_t xTimeOut; int8_t *pcOriginalReadPosition; -Queue_t * const pxQueue = ( Queue_t * ) xQueue; +Queue_t * const pxQueue = xQueue; /* Check the pointer is not NULL. */ configASSERT( ( pxQueue ) ); @@ -1618,10 +1655,9 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; #endif - /* This function relaxes the coding standard somewhat to allow return - statements within the function itself. This is done in the interest - of execution time efficiency. */ - + /*lint -save -e904 This function relaxes the coding standard somewhat to + allow return statements within the function itself. This is done in the + interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); @@ -1635,13 +1671,13 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; /* Remember the read position so it can be reset after the data is read from the queue as this function is only peeking the data, not removing it. */ - pcOriginalReadPosition = pxQueue->u.pcReadFrom; + pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom; prvCopyDataFromQueue( pxQueue, pvBuffer ); traceQUEUE_PEEK( pxQueue ); /* The data is not being removed, so reset the read pointer. */ - pxQueue->u.pcReadFrom = pcOriginalReadPosition; + pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition; /* The data is being left in the queue, so see if there are any other tasks waiting for the data. */ @@ -1742,7 +1778,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; mtCOVERAGE_TEST_MARKER(); } } - } + } /*lint -restore */ } /*-----------------------------------------------------------*/ @@ -1750,7 +1786,7 @@ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, Ba { BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; -Queue_t * const pxQueue = ( Queue_t * ) xQueue; +Queue_t * const pxQueue = xQueue; configASSERT( pxQueue ); configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); @@ -1842,7 +1878,7 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; int8_t *pcOriginalReadPosition; -Queue_t * const pxQueue = ( Queue_t * ) xQueue; +Queue_t * const pxQueue = xQueue; configASSERT( pxQueue ); configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); @@ -1873,9 +1909,9 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; /* Remember the read position so it can be reset as nothing is actually being removed from the queue. */ - pcOriginalReadPosition = pxQueue->u.pcReadFrom; + pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom; prvCopyDataFromQueue( pxQueue, pvBuffer ); - pxQueue->u.pcReadFrom = pcOriginalReadPosition; + pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition; xReturn = pdPASS; } @@ -1910,9 +1946,8 @@ UBaseType_t uxReturn; UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) { UBaseType_t uxReturn; -Queue_t *pxQueue; +Queue_t * const pxQueue = xQueue; - pxQueue = ( Queue_t * ) xQueue; configASSERT( pxQueue ); taskENTER_CRITICAL(); @@ -1928,10 +1963,10 @@ Queue_t *pxQueue; UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) { UBaseType_t uxReturn; +Queue_t * const pxQueue = xQueue; - configASSERT( xQueue ); - - uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting; + configASSERT( pxQueue ); + uxReturn = pxQueue->uxMessagesWaiting; return uxReturn; } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ @@ -1939,7 +1974,7 @@ UBaseType_t uxReturn; void vQueueDelete( QueueHandle_t xQueue ) { -Queue_t * const pxQueue = ( Queue_t * ) xQueue; +Queue_t * const pxQueue = xQueue; configASSERT( pxQueue ); traceQUEUE_DELETE( pxQueue ); @@ -2021,9 +2056,9 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue; other tasks that are waiting for the same mutex. For this purpose, return the priority of the highest priority task that is waiting for the mutex. */ - if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0 ) + if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U ) { - uxHighestPriorityOfWaitingTasks = configMAX_PRIORITIES - listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ); + uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ); } else { @@ -2052,8 +2087,8 @@ UBaseType_t uxMessagesWaiting; if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) { /* The mutex is no longer being held. */ - xReturn = xTaskPriorityDisinherit( ( void * ) pxQueue->pxMutexHolder ); - pxQueue->pxMutexHolder = NULL; + xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); + pxQueue->u.xSemaphore.xMutexHolder = NULL; } else { @@ -2064,9 +2099,9 @@ UBaseType_t uxMessagesWaiting; } else if( xPosition == queueSEND_TO_BACK ) { - ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. */ - pxQueue->pcWriteTo += pxQueue->uxItemSize; - if( pxQueue->pcWriteTo >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ + ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ + pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ + if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ { pxQueue->pcWriteTo = pxQueue->pcHead; } @@ -2077,11 +2112,11 @@ UBaseType_t uxMessagesWaiting; } else { - ( void ) memcpy( ( void * ) pxQueue->u.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ - pxQueue->u.pcReadFrom -= pxQueue->uxItemSize; - if( pxQueue->u.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ + ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ + pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; + if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ { - pxQueue->u.pcReadFrom = ( pxQueue->pcTail - pxQueue->uxItemSize ); + pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); } else { @@ -2119,16 +2154,16 @@ static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer { if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) { - pxQueue->u.pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->u.pcReadFrom >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ + pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ + if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ { - pxQueue->u.pcReadFrom = pxQueue->pcHead; + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; } else { mtCOVERAGE_TEST_MARKER(); } - ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. */ + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ } } /*-----------------------------------------------------------*/ @@ -2154,7 +2189,7 @@ static void prvUnlockQueue( Queue_t * const pxQueue ) { if( pxQueue->pxQueueSetContainer != NULL ) { - if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) != pdFALSE ) + if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) { /* The queue is a member of a queue set, and posting to the queue set caused a higher priority task to unblock. @@ -2277,9 +2312,10 @@ BaseType_t xReturn; BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) { BaseType_t xReturn; +Queue_t * const pxQueue = xQueue; - configASSERT( xQueue ); - if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( UBaseType_t ) 0 ) + configASSERT( pxQueue ); + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) { xReturn = pdTRUE; } @@ -2316,9 +2352,10 @@ BaseType_t xReturn; BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) { BaseType_t xReturn; +Queue_t * const pxQueue = xQueue; - configASSERT( xQueue ); - if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( ( Queue_t * ) xQueue )->uxLength ) + configASSERT( pxQueue ); + if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) { xReturn = pdTRUE; } @@ -2336,7 +2373,7 @@ BaseType_t xReturn; BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait ) { BaseType_t xReturn; - Queue_t * const pxQueue = ( Queue_t * ) xQueue; + Queue_t * const pxQueue = xQueue; /* If the queue is already full we may have to block. A critical section is required to prevent an interrupt removing something from the queue @@ -2413,7 +2450,7 @@ BaseType_t xReturn; BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait ) { BaseType_t xReturn; - Queue_t * const pxQueue = ( Queue_t * ) xQueue; + Queue_t * const pxQueue = xQueue; /* If the queue is already empty we may have to block. A critical section is required to prevent an interrupt adding something to the queue @@ -2450,17 +2487,17 @@ BaseType_t xReturn; if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 ) { /* Data is available from the queue. */ - pxQueue->u.pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->u.pcReadFrom >= pxQueue->pcTail ) + pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; + if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) { - pxQueue->u.pcReadFrom = pxQueue->pcHead; + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; } else { mtCOVERAGE_TEST_MARKER(); } --( pxQueue->uxMessagesWaiting ); - ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); xReturn = pdPASS; @@ -2502,7 +2539,7 @@ BaseType_t xReturn; BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken ) { - Queue_t * const pxQueue = ( Queue_t * ) xQueue; + Queue_t * const pxQueue = xQueue; /* Cannot block within an ISR so if there is no space on the queue then exit without doing anything. */ @@ -2551,24 +2588,24 @@ BaseType_t xReturn; BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken ) { BaseType_t xReturn; - Queue_t * const pxQueue = ( Queue_t * ) xQueue; + Queue_t * const pxQueue = xQueue; /* We cannot block from an ISR, so check there is data available. If not then just leave without doing anything. */ if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 ) { /* Copy the data from the queue. */ - pxQueue->u.pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->u.pcReadFrom >= pxQueue->pcTail ) + pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; + if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) { - pxQueue->u.pcReadFrom = pxQueue->pcHead; + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; } else { mtCOVERAGE_TEST_MARKER(); } --( pxQueue->uxMessagesWaiting ); - ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); if( ( *pxCoRoutineWoken ) == pdFALSE ) { @@ -2699,7 +2736,7 @@ BaseType_t xReturn; void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { - Queue_t * const pxQueue = ( Queue_t * ) xQueue; + Queue_t * const pxQueue = xQueue; /* This function should not be called by application code hence the 'Restricted' in its name. It is not part of the public API. It is @@ -2842,7 +2879,7 @@ BaseType_t xReturn; #if ( configUSE_QUEUE_SETS == 1 ) - static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition ) + static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) { Queue_t *pxQueueSetContainer = pxQueue->pxQueueSetContainer; BaseType_t xReturn = pdFALSE; @@ -2859,7 +2896,7 @@ BaseType_t xReturn; traceQUEUE_SEND( pxQueueSetContainer ); /* The data copied is the handle of the queue that contains data. */ - xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, xCopyPosition ); + xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, queueSEND_TO_BACK ); if( cTxLock == queueUNLOCKED ) { diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c index c0ef727..c88e4ea 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -43,11 +43,11 @@ task.h is included from an application file. */ #error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c #endif -/* Lint e961 and e750 are suppressed as a MISRA exception justified because the -MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the -header files above, but not in this file, in order to generate the correct -privileged Vs unprivileged linkage and placement. */ -#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */ +/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified +because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined +for the header files above, but not in this file, in order to generate the +correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ /* If the user has not provided application specific Rx notification macros, or #defined the notification macros away, them provide default implementations @@ -129,7 +129,7 @@ that uses task notifications. */ /*lint -restore (9026) */ /* The number of bytes used to hold the length of a message in the buffer. */ -#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( size_t ) ) +#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) ) /* Bits stored in the ucFlags field of the stream buffer. */ #define sbFLAGS_IS_MESSAGE_BUFFER ( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */ @@ -138,7 +138,7 @@ that uses task notifications. */ /*-----------------------------------------------------------*/ /* Structure that hold state information on the buffer. */ -typedef struct xSTREAM_BUFFER /*lint !e9058 Style convention uses tag. */ +typedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */ { volatile size_t xTail; /* Index to the next item to read within the buffer. */ volatile size_t xHead; /* Index to the next item to write within the buffer. */ @@ -200,7 +200,7 @@ static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer, static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer, uint8_t *pucData, size_t xMaxCount, - size_t xBytesAvailable ); PRIVILEGED_FUNCTION + size_t xBytesAvailable ) PRIVILEGED_FUNCTION; /* * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to @@ -210,7 +210,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, uint8_t * const pucBuffer, size_t xBufferSizeBytes, size_t xTriggerLevelBytes, - BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION; + uint8_t ucFlags ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ @@ -219,19 +219,31 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) { uint8_t *pucAllocatedMemory; + uint8_t ucFlags; /* In case the stream buffer is going to be used as a message buffer (that is, it will hold discrete messages with a little meta data that says how big the next message is) check the buffer will be large enough to hold at least one message. */ - configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH ); + if( xIsMessageBuffer == pdTRUE ) + { + /* Is a message buffer but not statically allocated. */ + ucFlags = sbFLAGS_IS_MESSAGE_BUFFER; + configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH ); + } + else + { + /* Not a message buffer and not statically allocated. */ + ucFlags = 0; + configASSERT( xBufferSizeBytes > 0 ); + } configASSERT( xTriggerLevelBytes <= xBufferSizeBytes ); /* A trigger level of 0 would cause a waiting task to unblock even when the buffer was empty. */ if( xTriggerLevelBytes == ( size_t ) 0 ) { - xTriggerLevelBytes = ( size_t ) 1; /*lint !e9044 Parameter modified to ensure it doesn't have a dangerous value. */ + xTriggerLevelBytes = ( size_t ) 1; } /* A stream buffer requires a StreamBuffer_t structure and a buffer. @@ -251,7 +263,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, pucAllocatedMemory + sizeof( StreamBuffer_t ), /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */ xBufferSizeBytes, xTriggerLevelBytes, - xIsMessageBuffer ); + ucFlags ); traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer ); } @@ -260,7 +272,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ); } - return ( StreamBufferHandle_t * ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */ + return ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */ } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ @@ -276,6 +288,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, { StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */ StreamBufferHandle_t xReturn; + uint8_t ucFlags; configASSERT( pucStreamBufferStorageArea ); configASSERT( pxStaticStreamBuffer ); @@ -285,7 +298,18 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, the buffer was empty. */ if( xTriggerLevelBytes == ( size_t ) 0 ) { - xTriggerLevelBytes = ( size_t ) 1; /*lint !e9044 Function parameter deliberately modified to ensure it is in range. */ + xTriggerLevelBytes = ( size_t ) 1; + } + + if( xIsMessageBuffer != pdFALSE ) + { + /* Statically allocated message buffer. */ + ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED; + } + else + { + /* Statically allocated stream buffer. */ + ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED; } /* In case the stream buffer is going to be used as a message buffer @@ -301,7 +325,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, message buffer structure. */ volatile size_t xSize = sizeof( StaticStreamBuffer_t ); configASSERT( xSize == sizeof( StreamBuffer_t ) ); - } + } /*lint !e529 xSize is referenced is configASSERT() is defined. */ #endif /* configASSERT_DEFINED */ if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) ) @@ -310,7 +334,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, pucStreamBufferStorageArea, xBufferSizeBytes, xTriggerLevelBytes, - xIsMessageBuffer ); + ucFlags ); /* Remember this was statically allocated in case it is ever deleted again. */ @@ -334,7 +358,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) { -StreamBuffer_t * pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */ +StreamBuffer_t * pxStreamBuffer = xStreamBuffer; configASSERT( pxStreamBuffer ); @@ -360,15 +384,15 @@ StreamBuffer_t * pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9 { /* The structure and buffer were not allocated dynamically and cannot be freed - just scrub the structure so future use will assert. */ - memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); + ( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); } } /*-----------------------------------------------------------*/ BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) { -StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */ -BaseType_t xReturn = pdFAIL, xIsMessageBuffer; +StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; +BaseType_t xReturn = pdFAIL; #if( configUSE_TRACE_FACILITY == 1 ) UBaseType_t uxStreamBufferNumber; @@ -385,35 +409,30 @@ BaseType_t xReturn = pdFAIL, xIsMessageBuffer; #endif /* Can only reset a message buffer if there are no tasks blocked on it. */ - if( pxStreamBuffer->xTaskWaitingToReceive == NULL ) + taskENTER_CRITICAL(); { - if( pxStreamBuffer->xTaskWaitingToSend == NULL ) + if( pxStreamBuffer->xTaskWaitingToReceive == NULL ) { - if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + if( pxStreamBuffer->xTaskWaitingToSend == NULL ) { - xIsMessageBuffer = pdTRUE; - } - else - { - xIsMessageBuffer = pdFALSE; - } + prvInitialiseNewStreamBuffer( pxStreamBuffer, + pxStreamBuffer->pucBuffer, + pxStreamBuffer->xLength, + pxStreamBuffer->xTriggerLevelBytes, + pxStreamBuffer->ucFlags ); + xReturn = pdPASS; - prvInitialiseNewStreamBuffer( pxStreamBuffer, - pxStreamBuffer->pucBuffer, - pxStreamBuffer->xLength, - pxStreamBuffer->xTriggerLevelBytes, - xIsMessageBuffer ); - xReturn = pdPASS; + #if( configUSE_TRACE_FACILITY == 1 ) + { + pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber; + } + #endif - #if( configUSE_TRACE_FACILITY == 1 ) - { - pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber; + traceSTREAM_BUFFER_RESET( xStreamBuffer ); } - #endif - - traceSTREAM_BUFFER_RESET( xStreamBuffer ); } } + taskEXIT_CRITICAL(); return xReturn; } @@ -421,7 +440,7 @@ BaseType_t xReturn = pdFAIL, xIsMessageBuffer; BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) { -StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */ +StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; BaseType_t xReturn; configASSERT( pxStreamBuffer ); @@ -429,7 +448,7 @@ BaseType_t xReturn; /* It is not valid for the trigger level to be 0. */ if( xTriggerLevel == ( size_t ) 0 ) { - xTriggerLevel = ( size_t ) 1; /*lint !e9044 Parameter modified to ensure it doesn't have a dangerous value. */ + xTriggerLevel = ( size_t ) 1; } /* The trigger level is the number of bytes that must be in the stream @@ -450,7 +469,7 @@ BaseType_t xReturn; size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) { -const StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */ +const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; size_t xSpace; configASSERT( pxStreamBuffer ); @@ -474,7 +493,7 @@ size_t xSpace; size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) { -const StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */ +const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; size_t xReturn; configASSERT( pxStreamBuffer ); @@ -489,7 +508,7 @@ size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, size_t xDataLengthBytes, TickType_t xTicksToWait ) { -StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */ +StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; size_t xReturn, xSpace = 0; size_t xRequiredSpace = xDataLengthBytes; TimeOut_t xTimeOut; @@ -504,6 +523,9 @@ TimeOut_t xTimeOut; if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) { xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH; + + /* Overflow? */ + configASSERT( xRequiredSpace > xDataLengthBytes ); } else { @@ -540,7 +562,7 @@ TimeOut_t xTimeOut; taskEXIT_CRITICAL(); traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ); - ( void ) xTaskNotifyWait( ( uint32_t ) 0, UINT32_MAX, NULL, xTicksToWait ); + ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); pxStreamBuffer->xTaskWaitingToSend = NULL; } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ); @@ -590,7 +612,7 @@ size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, size_t xDataLengthBytes, BaseType_t * const pxHigherPriorityTaskWoken ) { -StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */ +StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; size_t xReturn, xSpace; size_t xRequiredSpace = xDataLengthBytes; @@ -657,7 +679,7 @@ static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer, stream of bytes rather than discrete messages. Write as many bytes as possible. */ xShouldWrite = pdTRUE; - xDataLengthBytes = configMIN( xDataLengthBytes, xSpace ); /*lint !e9044 Function parameter modified to ensure it is capped to available space. */ + xDataLengthBytes = configMIN( xDataLengthBytes, xSpace ); } else if( xSpace >= xRequiredSpace ) { @@ -693,7 +715,7 @@ size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, size_t xBufferLengthBytes, TickType_t xTicksToWait ) { -StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */ +StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength; configASSERT( pvRxData ); @@ -746,7 +768,7 @@ size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength; { /* Wait for data to be available. */ traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ); - ( void ) xTaskNotifyWait( ( uint32_t ) 0, UINT32_MAX, NULL, xTicksToWait ); + ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); pxStreamBuffer->xTaskWaitingToReceive = NULL; /* Recheck the data available after blocking. */ @@ -792,12 +814,56 @@ size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength; } /*-----------------------------------------------------------*/ +size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) +{ +StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; +size_t xReturn, xBytesAvailable, xOriginalTail; +configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn; + + configASSERT( pxStreamBuffer ); + + /* Ensure the stream buffer is being used as a message buffer. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH ) + { + /* The number of bytes available is greater than the number of bytes + required to hold the length of the next message, so another message + is available. Return its length without removing the length bytes + from the buffer. A copy of the tail is stored so the buffer can be + returned to its prior state as the message is not actually being + removed from the buffer. */ + xOriginalTail = pxStreamBuffer->xTail; + ( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, xBytesAvailable ); + xReturn = ( size_t ) xTempReturn; + pxStreamBuffer->xTail = xOriginalTail; + } + else + { + /* The minimum amount of bytes in a message buffer is + ( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is + less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid + value is 0. */ + configASSERT( xBytesAvailable == 0 ); + xReturn = 0; + } + } + else + { + xReturn = 0; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, BaseType_t * const pxHigherPriorityTaskWoken ) { -StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */ +StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength; configASSERT( pvRxData ); @@ -856,6 +922,7 @@ static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer, size_t xBytesToStoreMessageLength ) { size_t xOriginalTail, xReceivedLength, xNextMessageLength; +configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength; if( xBytesToStoreMessageLength != ( size_t ) 0 ) { @@ -864,7 +931,8 @@ size_t xOriginalTail, xReceivedLength, xNextMessageLength; returned to its prior state if the length of the message is too large for the provided buffer. */ xOriginalTail = pxStreamBuffer->xTail; - ( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable ); + ( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable ); + xNextMessageLength = ( size_t ) xTempNextMessageLength; /* Reduce the number of bytes available by the number of bytes just read out. */ @@ -901,7 +969,7 @@ size_t xOriginalTail, xReceivedLength, xNextMessageLength; BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) { -const StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */ +const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; BaseType_t xReturn; size_t xTail; @@ -926,7 +994,7 @@ BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) { BaseType_t xReturn; size_t xBytesToStoreMessageLength; -const StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */ +const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; configASSERT( pxStreamBuffer ); @@ -959,7 +1027,7 @@ const StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) { -StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */ +StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; @@ -989,7 +1057,7 @@ UBaseType_t uxSavedInterruptStatus; BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) { -StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */ +StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; @@ -1032,7 +1100,7 @@ size_t xNextHead, xFirstLength; /* Write as many bytes as can be written in the first write. */ configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength ); - memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + ( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */ /* If the number of bytes written was less than the number that could be written in the first write... */ @@ -1040,7 +1108,7 @@ size_t xNextHead, xFirstLength; { /* ...then write the remaining bytes to the start of the buffer. */ configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength ); - memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ } else { @@ -1083,7 +1151,7 @@ size_t xCount, xFirstLength, xNextTail; read. Asserts check bounds of read and write. */ configASSERT( xFirstLength <= xMaxCount ); configASSERT( ( xNextTail + xFirstLength ) <= pxStreamBuffer->xLength ); - memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + ( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */ /* If the total number of wanted bytes is greater than the number that could be read in the first read... */ @@ -1091,7 +1159,7 @@ size_t xCount, xFirstLength, xNextTail; { /*...then read the remaining bytes from the start of the buffer. */ configASSERT( xCount <= xMaxCount ); - memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + ( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ } else { @@ -1142,7 +1210,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, uint8_t * const pucBuffer, size_t xBufferSizeBytes, size_t xTriggerLevelBytes, - BaseType_t xIsMessageBuffer ) + uint8_t ucFlags ) { /* Assert here is deliberately writing to the entire buffer to ensure it can be written to without generating exceptions, and is setting the buffer to a @@ -1154,25 +1222,21 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, result in confusion as to what is actually being observed. */ const BaseType_t xWriteValue = 0x55; configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer ); - } + } /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */ #endif - memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */ + ( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */ pxStreamBuffer->pucBuffer = pucBuffer; pxStreamBuffer->xLength = xBufferSizeBytes; pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes; - - if( xIsMessageBuffer != pdFALSE ) - { - pxStreamBuffer->ucFlags |= sbFLAGS_IS_MESSAGE_BUFFER; - } + pxStreamBuffer->ucFlags = ucFlags; } #if ( configUSE_TRACE_FACILITY == 1 ) UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) { - return ( ( StreamBuffer_t * ) xStreamBuffer )->uxStreamBufferNumber; + return xStreamBuffer->uxStreamBufferNumber; } #endif /* configUSE_TRACE_FACILITY */ @@ -1182,7 +1246,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber ) { - ( ( StreamBuffer_t * ) xStreamBuffer )->uxStreamBufferNumber = uxStreamBufferNumber; + xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber; } #endif /* configUSE_TRACE_FACILITY */ @@ -1192,7 +1256,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) { - return ( ( StreamBuffer_t * )xStreamBuffer )->ucFlags | sbFLAGS_IS_MESSAGE_BUFFER; + return ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ); } #endif /* configUSE_TRACE_FACILITY */ diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/tasks.c b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/tasks.c index 9e1cb9b..f93fca0 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/tasks.c +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/tasks.c @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -40,11 +40,11 @@ task.h is included from an application file. */ #include "timers.h" #include "stack_macros.h" -/* Lint e961 and e750 are suppressed as a MISRA exception justified because the -MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the -header files above, but not in this file, in order to generate the correct -privileged Vs unprivileged linkage and placement. */ -#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */ +/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified +because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined +for the header files above, but not in this file, in order to generate the +correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ /* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting functions but without including stdio.h here. */ @@ -75,24 +75,7 @@ functions but without including stdio.h here. */ */ #define tskSTACK_FILL_BYTE ( 0xa5U ) -/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using -dynamically allocated RAM, in which case when any task is deleted it is known -that both the task's stack and TCB need to be freed. Sometimes the -FreeRTOSConfig.h settings only allow a task to be created using statically -allocated RAM, in which case when any task is deleted it is known that neither -the task's stack or TCB should be freed. Sometimes the FreeRTOSConfig.h -settings allow a task to be created using either statically or dynamically -allocated RAM, in which case a member of the TCB is used to record whether the -stack and/or TCB were allocated statically or dynamically, so when a task is -deleted the RAM that was allocated dynamically is freed again and no attempt is -made to free the RAM that was allocated statically. -tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a -task to be created using either statically or dynamically allocated RAM. Note -that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with -a statically allocated stack and a dynamically allocated TCB. -!!!NOTE!!! If the definition of tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is -changed then the definition of StaticTask_t must also be updated. */ -#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) +/* Bits used to recored how a task's stack and TCB were allocated. */ #define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ( ( uint8_t ) 0 ) #define tskSTATICALLY_ALLOCATED_STACK_ONLY ( ( uint8_t ) 1 ) #define tskSTATICALLY_ALLOCATED_STACK_AND_TCB ( ( uint8_t ) 2 ) @@ -100,7 +83,7 @@ changed then the definition of StaticTask_t must also be updated. */ /* If any of the following are set then task stacks are filled with a known value so the high water mark can be determined. If none of the following are set then don't fill the stack so there is no unnecessary dependency on memset. */ -#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) +#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) #define tskSET_NEW_STACKS_TO_KNOWN_VALUE 1 #else #define tskSET_NEW_STACKS_TO_KNOWN_VALUE 0 @@ -245,7 +228,7 @@ count overflows. */ * task should be used in place of the parameter. This macro simply checks to * see if the parameter is NULL and returns a pointer to the appropriate TCB. */ -#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? ( TCB_t * ) pxCurrentTCB : ( TCB_t * ) ( pxHandle ) ) +#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) ) /* The item value of the event list item is normally used to hold the priority of the task to which it belongs (coded to allow it to be held in reverse @@ -266,7 +249,7 @@ to its original value when it is released. */ * and stores task state information, including a pointer to the task's context * (the task's run time environment, including register values) */ -typedef struct tskTaskControlBlock +typedef struct tskTaskControlBlock /* The old naming convention is used to prevent breaking kernel aware debuggers. */ { volatile StackType_t *pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */ @@ -317,7 +300,10 @@ typedef struct tskTaskControlBlock responsible for resulting newlib operation. User must be familiar with newlib and must provide system-wide implementations of the necessary stubs. Be warned that (at the time of writing) the current newlib design - implements a system-wide malloc() that must be provided with locks. */ + implements a system-wide malloc() that must be provided with locks. + + See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + for additional information. */ struct _reent xNewLib_reent; #endif @@ -326,9 +312,9 @@ typedef struct tskTaskControlBlock volatile uint8_t ucNotifyState; #endif - /* See the comments above the definition of + /* See the comments in FreeRTOS.h with the definition of tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */ - #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 Macro has been consolidated for readability reasons. */ + #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */ #endif @@ -336,6 +322,10 @@ typedef struct tskTaskControlBlock uint8_t ucDelayAborted; #endif + #if( configUSE_POSIX_ERRNO == 1 ) + int iTaskErrno; + #endif + } tskTCB; /* The old tskTCB name is maintained above then typedefed to the new TCB_t name @@ -344,36 +334,44 @@ typedef tskTCB TCB_t; /*lint -save -e956 A manual analysis and inspection has been used to determine which static variables must be declared volatile. */ - PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL; -/* Lists for ready and blocked tasks. --------------------*/ -PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ] = {0}; /*< Prioritised ready tasks. */ -PRIVILEGED_DATA static List_t xDelayedTaskList1 = {0}; /*< Delayed tasks. */ -PRIVILEGED_DATA static List_t xDelayedTaskList2 = {0}; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */ -PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList = NULL; /*< Points to the delayed task list currently being used. */ -PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList = NULL; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */ -PRIVILEGED_DATA static List_t xPendingReadyList = {0}; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready list when the scheduler is resumed. */ +/* Lists for ready and blocked tasks. -------------------- +xDelayedTaskList1 and xDelayedTaskList2 could be move to function scople but +doing so breaks some kernel aware debuggers and debuggers that rely on removing +the static qualifier. */ +PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ];/*< Prioritised ready tasks. */ +PRIVILEGED_DATA static List_t xDelayedTaskList1; /*< Delayed tasks. */ +PRIVILEGED_DATA static List_t xDelayedTaskList2; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */ +PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList; /*< Points to the delayed task list currently being used. */ +PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */ +PRIVILEGED_DATA static List_t xPendingReadyList; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready list when the scheduler is resumed. */ #if( INCLUDE_vTaskDelete == 1 ) - PRIVILEGED_DATA static List_t xTasksWaitingTermination = {0}; /*< Tasks that have been deleted - but their memory not yet freed. */ + PRIVILEGED_DATA static List_t xTasksWaitingTermination; /*< Tasks that have been deleted - but their memory not yet freed. */ PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U; #endif #if ( INCLUDE_vTaskSuspend == 1 ) - PRIVILEGED_DATA static List_t xSuspendedTaskList = {0}; /*< Tasks that are currently suspended. */ + PRIVILEGED_DATA static List_t xSuspendedTaskList; /*< Tasks that are currently suspended. */ #endif +/* Global POSIX errno. Its value is changed upon context switching to match +the errno of the currently running task. */ +#if ( configUSE_POSIX_ERRNO == 1 ) + int FreeRTOS_errno = 0; +#endif + /* Other file private variables. --------------------------------*/ PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks = ( UBaseType_t ) 0U; PRIVILEGED_DATA static volatile TickType_t xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority = tskIDLE_PRIORITY; PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning = pdFALSE; -PRIVILEGED_DATA static volatile UBaseType_t uxPendedTicks = ( UBaseType_t ) 0U; +PRIVILEGED_DATA static volatile TickType_t xPendedTicks = ( TickType_t ) 0U; PRIVILEGED_DATA static volatile BaseType_t xYieldPending = pdFALSE; PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows = ( BaseType_t ) 0; PRIVILEGED_DATA static UBaseType_t uxTaskNumber = ( UBaseType_t ) 0U; @@ -392,6 +390,8 @@ PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended = ( UBaseType_t #if ( configGENERATE_RUN_TIME_STATS == 1 ) + /* Do not move these variables to function scope as doing so prevents the + code working with debuggers that need to remove the static qualifier. */ PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL; /*< Holds the value of a timer/counter the last time a task was switched in. */ PRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL; /*< Holds the total amount of execution time as defined by the run time counter clock. */ @@ -403,15 +403,21 @@ PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended = ( UBaseType_t /* Callback function prototypes. --------------------------*/ #if( configCHECK_FOR_STACK_OVERFLOW > 0 ) + extern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName ); + #endif #if( configUSE_TICK_HOOK > 0 ) - extern void vApplicationTickHook( void ); + + extern void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */ + #endif #if( configSUPPORT_STATIC_ALLOCATION == 1 ) - extern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ); + + extern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */ + #endif /* File private functions. --------------------------------*/ @@ -501,9 +507,9 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseT * This function determines the 'high water mark' of the task stack by * determining how much of the stack remains at the original preset value. */ -#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) +#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) - static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION; + static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION; #endif @@ -593,6 +599,7 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION; structure. */ volatile size_t xSize = sizeof( StaticTask_t ); configASSERT( xSize == sizeof( TCB_t ) ); + ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ } #endif /* configASSERT_DEFINED */ @@ -601,16 +608,16 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION; { /* The memory used for the task's TCB and stack are passed into this function - use them. */ - pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ + pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; - #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 Macro has been consolidated for readability reasons. */ + #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created statically in case the task is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; } - #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); prvAddNewTaskToReadyList( pxNewTCB ); @@ -652,7 +659,7 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION; task was created statically in case the task is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; } - #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskDefinition->pvTaskCode, pxTaskDefinition->pcName, @@ -693,14 +700,14 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION; /* Store the stack location in the TCB. */ pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer; - #if( configSUPPORT_STATIC_ALLOCATION == 1 ) + #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) { /* Tasks can be created statically or dynamically, so note this task had a statically allocated stack in case it is later deleted. The TCB was allocated dynamically. */ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY; } - #endif + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskDefinition->pvTaskCode, pxTaskDefinition->pcName, @@ -763,12 +770,12 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION; StackType_t *pxStack; /* Allocate space for the stack used by the task being created. */ - pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ if( pxStack != NULL ) { /* Allocate space for the TCB. */ - pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e961 MISRA exception as the casts are only redundant for some paths. */ + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ if( pxNewTCB != NULL ) { @@ -791,13 +798,13 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION; if( pxNewTCB != NULL ) { - #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 Macro has been consolidated for readability reasons. */ + #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; } - #endif /* configSUPPORT_STATIC_ALLOCATION */ + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); prvAddNewTaskToReadyList( pxNewTCB ); @@ -854,8 +861,8 @@ UBaseType_t x; by the port. */ #if( portSTACK_GROWTH < 0 ) { - pxTopOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); - pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. */ + pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); + pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ /* Check the alignment of the calculated top of stack is correct. */ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); @@ -882,26 +889,35 @@ UBaseType_t x; #endif /* portSTACK_GROWTH */ /* Store the task name in the TCB. */ - for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) + if( pcName != NULL ) { - pxNewTCB->pcTaskName[ x ] = pcName[ x ]; + for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) + { + pxNewTCB->pcTaskName[ x ] = pcName[ x ]; - /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than - configMAX_TASK_NAME_LEN characters just in case the memory after the - string is not accessible (extremely unlikely). */ - if( pcName[ x ] == 0x00 ) - { - break; - } - else - { - mtCOVERAGE_TEST_MARKER(); + /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than + configMAX_TASK_NAME_LEN characters just in case the memory after the + string is not accessible (extremely unlikely). */ + if( pcName[ x ] == ( char ) 0x00 ) + { + break; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } } + + /* Ensure the name string is terminated in the case that the string length + was greater or equal to configMAX_TASK_NAME_LEN. */ + pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; + } + else + { + /* The task has not been given a name, so just ensure there is a NULL + terminator when it is read out. */ + pxNewTCB->pcTaskName[ 0 ] = 0x00; } - - /* Ensure the name string is terminated in the case that the string length - was greater or equal to configMAX_TASK_NAME_LEN. */ - pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; /* This is used as an array index so must ensure it's not too large. First remove the privilege bit if one is present. */ @@ -980,7 +996,9 @@ UBaseType_t x; #if ( configUSE_NEWLIB_REENTRANT == 1 ) { - /* Initialise this task's Newlib reent structure. */ + /* Initialise this task's Newlib reent structure. + See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + for additional information. */ _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) ); } #endif @@ -997,15 +1015,53 @@ UBaseType_t x; the top of stack variable is updated. */ #if( portUSING_MPU_WRAPPERS == 1 ) { - pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged ); + /* If the port has capability to detect stack overflow, + pass the stack end address to the stack initialization + function as well. */ + #if( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + { + #if( portSTACK_GROWTH < 0 ) + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged ); + } + #else /* portSTACK_GROWTH */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged ); + } + #endif /* portSTACK_GROWTH */ + } + #else /* portHAS_STACK_OVERFLOW_CHECKING */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged ); + } + #endif /* portHAS_STACK_OVERFLOW_CHECKING */ } #else /* portUSING_MPU_WRAPPERS */ { - pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); + /* If the port has capability to detect stack overflow, + pass the stack end address to the stack initialization + function as well. */ + #if( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + { + #if( portSTACK_GROWTH < 0 ) + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters ); + } + #else /* portSTACK_GROWTH */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters ); + } + #endif /* portSTACK_GROWTH */ + } + #else /* portHAS_STACK_OVERFLOW_CHECKING */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); + } + #endif /* portHAS_STACK_OVERFLOW_CHECKING */ } #endif /* portUSING_MPU_WRAPPERS */ - if( ( void * ) pxCreatedTask != NULL ) + if( pxCreatedTask != NULL ) { /* Pass the handle out in an anonymous way. The handle can be used to change the created task's priority, delete the created task, etc.*/ @@ -1113,7 +1169,7 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) being deleted. */ pxTCB = prvGetTCBFromHandle( xTaskToDelete ); - /* Remove task from the ready list. */ + /* Remove task from the ready/delayed list. */ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) { taskRESET_READY_PRIORITY( pxTCB->uxPriority ); @@ -1153,6 +1209,10 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) check the xTasksWaitingTermination list. */ ++uxDeletedTasksWaitingCleanUp; + /* Call the delete hook before portPRE_TASK_DELETE_HOOK() as + portPRE_TASK_DELETE_HOOK() does not return in the Win32 port. */ + traceTASK_DELETE( pxTCB ); + /* The pre-delete hook is primarily for the Windows simulator, in which Windows specific clean up operations are performed, after which it is not possible to yield away from this task - @@ -1163,14 +1223,13 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) else { --uxCurrentNumberOfTasks; + traceTASK_DELETE( pxTCB ); prvDeleteTCB( pxTCB ); /* Reset the next expected unblock time in case it referred to the task that has just been deleted. */ prvResetNextTaskUnblockTime(); } - - traceTASK_DELETE( pxTCB ); } taskEXIT_CRITICAL(); @@ -1322,13 +1381,13 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) #endif /* INCLUDE_vTaskDelay */ /*-----------------------------------------------------------*/ -#if( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) ) +#if( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) ) eTaskState eTaskGetState( TaskHandle_t xTask ) { eTaskState eReturn; - List_t *pxStateList; - const TCB_t * const pxTCB = ( TCB_t * ) xTask; + List_t const * pxStateList, *pxDelayedList, *pxOverflowedDelayedList; + const TCB_t * const pxTCB = xTask; configASSERT( pxTCB ); @@ -1341,11 +1400,13 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) { taskENTER_CRITICAL(); { - pxStateList = ( List_t * ) listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) ); + pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) ); + pxDelayedList = pxDelayedTaskList; + pxOverflowedDelayedList = pxOverflowDelayedTaskList; } taskEXIT_CRITICAL(); - if( ( pxStateList == pxDelayedTaskList ) || ( pxStateList == pxOverflowDelayedTaskList ) ) + if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) ) { /* The task being queried is referenced from one of the Blocked lists. */ @@ -1356,11 +1417,30 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) else if( pxStateList == &xSuspendedTaskList ) { /* The task being queried is referenced from the suspended - list. Is it genuinely suspended or is it block + list. Is it genuinely suspended or is it blocked indefinitely? */ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ) { - eReturn = eSuspended; + #if( configUSE_TASK_NOTIFICATIONS == 1 ) + { + /* The task does not appear on the event list item of + and of the RTOS objects, but could still be in the + blocked state if it is waiting on its notification + rather than waiting on an object. */ + if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION ) + { + eReturn = eBlocked; + } + else + { + eReturn = eSuspended; + } + } + #else + { + eReturn = eSuspended; + } + #endif } else { @@ -1395,15 +1475,15 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) #if ( INCLUDE_uxTaskPriorityGet == 1 ) - UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask ) + UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) { - TCB_t *pxTCB; + TCB_t const *pxTCB; UBaseType_t uxReturn; taskENTER_CRITICAL(); { - /* If null is passed in here then it is the priority of the that - called uxTaskPriorityGet() that is being queried. */ + /* If null is passed in here then it is the priority of the task + that called uxTaskPriorityGet() that is being queried. */ pxTCB = prvGetTCBFromHandle( xTask ); uxReturn = pxTCB->uxPriority; } @@ -1417,9 +1497,9 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) #if ( INCLUDE_uxTaskPriorityGet == 1 ) - UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask ) + UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) { - TCB_t *pxTCB; + TCB_t const *pxTCB; UBaseType_t uxReturn, uxSavedInterruptState; /* RTOS ports that support interrupt nesting have the concept of a @@ -1437,7 +1517,7 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: - http://www.freertos.org/RTOS-Cortex-M3-M4.html */ + https://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR(); @@ -1697,7 +1777,7 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) /* The scheduler is not running, but the task that was pointed to by pxCurrentTCB has just been suspended and pxCurrentTCB must be adjusted to point to a different task. */ - if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) + if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */ { /* No other tasks are ready, so set pxCurrentTCB back to NULL so when the next task is created pxCurrentTCB will @@ -1725,7 +1805,7 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) { BaseType_t xReturn = pdFALSE; - const TCB_t * const pxTCB = ( TCB_t * ) xTask; + const TCB_t * const pxTCB = xTask; /* Accesses xPendingReadyList so must be called from a critical section. */ @@ -1770,14 +1850,14 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) void vTaskResume( TaskHandle_t xTaskToResume ) { - TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume; + TCB_t * const pxTCB = xTaskToResume; /* It does not make sense to resume the calling task. */ configASSERT( xTaskToResume ); /* The parameter cannot be NULL as it is impossible to resume the currently executing task. */ - if( ( pxTCB != NULL ) && ( pxTCB != pxCurrentTCB ) ) + if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) ) { taskENTER_CRITICAL(); { @@ -1825,7 +1905,7 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) { BaseType_t xYieldRequired = pdFALSE; - TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume; + TCB_t * const pxTCB = xTaskToResume; UBaseType_t uxSavedInterruptStatus; configASSERT( xTaskToResume ); @@ -1845,7 +1925,7 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: - http://www.freertos.org/RTOS-Cortex-M3-M4.html */ + https://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); @@ -1910,7 +1990,7 @@ BaseType_t xReturn; configIDLE_TASK_NAME, ulIdleTaskStackSize, ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */ - ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), + portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ pxIdleTaskStackBuffer, pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ @@ -1930,7 +2010,7 @@ BaseType_t xReturn; configIDLE_TASK_NAME, configMINIMAL_STACK_SIZE, ( void * ) NULL, - ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), + portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ &xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ } #endif /* configSUPPORT_STATIC_ALLOCATION */ @@ -1969,14 +2049,16 @@ BaseType_t xReturn; #if ( configUSE_NEWLIB_REENTRANT == 1 ) { /* Switch Newlib's _impure_ptr variable to point to the _reent - structure specific to the task that will run first. */ + structure specific to the task that will run first. + See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); } #endif /* configUSE_NEWLIB_REENTRANT */ xNextTaskUnblockTime = portMAX_DELAY; xSchedulerRunning = pdTRUE; - xTickCount = ( TickType_t ) 0U; + xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; /* If configGENERATE_RUN_TIME_STATS is defined then the following macro must be defined to configure the timer/counter used to generate @@ -1986,6 +2068,8 @@ BaseType_t xReturn; FreeRTOSConfig.h file. */ portCONFIGURE_TIMER_FOR_RUN_TIME_STATS(); + traceTASK_SWITCHED_IN(); + /* Setting up the timer tick is hardware specific and thus in the portable interface. */ if( xPortStartScheduler() != pdFALSE ) @@ -2029,7 +2113,18 @@ void vTaskSuspendAll( void ) BaseType_t. Please read Richard Barry's reply in the following link to a post in the FreeRTOS support forum before reporting this as a bug! - http://goo.gl/wu4acr */ + + /* portSOFRWARE_BARRIER() is only implemented for emulated/simulated ports that + do not otherwise exhibit real time behaviour. */ + portSOFTWARE_BARRIER(); + + /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment + is used to allow calls to vTaskSuspendAll() to nest. */ ++uxSchedulerSuspended; + + /* Enforces ordering for ports and optimised compilers that may otherwise place + the above increment elsewhere. */ + portMEMORY_BARRIER(); } /*----------------------------------------------------------*/ @@ -2122,7 +2217,7 @@ BaseType_t xAlreadyYielded = pdFALSE; appropriate ready list. */ while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) { - pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); prvAddTaskToReadyList( pxTCB ); @@ -2155,9 +2250,9 @@ BaseType_t xAlreadyYielded = pdFALSE; not slip, and that any delayed tasks are resumed at the correct time. */ { - UBaseType_t uxPendedCounts = uxPendedTicks; /* Non-volatile copy. */ + TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ - if( uxPendedCounts > ( UBaseType_t ) 0U ) + if( xPendedCounts > ( TickType_t ) 0U ) { do { @@ -2169,10 +2264,10 @@ BaseType_t xAlreadyYielded = pdFALSE; { mtCOVERAGE_TEST_MARKER(); } - --uxPendedCounts; - } while( uxPendedCounts > ( UBaseType_t ) 0U ); + --xPendedCounts; + } while( xPendedCounts > ( TickType_t ) 0U ); - uxPendedTicks = 0; + xPendedTicks = 0; } else { @@ -2239,7 +2334,7 @@ UBaseType_t uxSavedInterruptStatus; system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following - link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ + link: https://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR(); @@ -2279,19 +2374,21 @@ TCB_t *pxTCB; TCB_t *pxNextTCB, *pxFirstTCB, *pxReturn = NULL; UBaseType_t x; char cNextChar; + BaseType_t xBreakLoop; /* This function is called with the scheduler suspended. */ if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 ) { - listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); + listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ do { - listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); + listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ /* Check each character in the name looking for a match or mismatch. */ + xBreakLoop = pdFALSE; for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) { cNextChar = pxNextTCB->pcTaskName[ x ]; @@ -2299,19 +2396,24 @@ TCB_t *pxTCB; if( cNextChar != pcNameToQuery[ x ] ) { /* Characters didn't match. */ - break; + xBreakLoop = pdTRUE; } - else if( cNextChar == 0x00 ) + else if( cNextChar == ( char ) 0x00 ) { /* Both strings terminated, a match must have been found. */ pxReturn = pxNextTCB; - break; + xBreakLoop = pdTRUE; } else { mtCOVERAGE_TEST_MARKER(); } + + if( xBreakLoop != pdFALSE ) + { + break; + } } if( pxReturn != NULL ) @@ -2392,7 +2494,7 @@ TCB_t *pxTCB; } ( void ) xTaskResumeAll(); - return ( TaskHandle_t ) pxTCB; + return pxTCB; } #endif /* INCLUDE_xTaskGetHandle */ @@ -2504,11 +2606,29 @@ implementations require configUSE_TICKLESS_IDLE to be set to a value other than #endif /* configUSE_TICKLESS_IDLE */ /*----------------------------------------------------------*/ +BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) +{ +BaseType_t xYieldRequired = pdFALSE; + + /* Must not be called with the scheduler suspended as the implementation + relies on xPendedTicks being wound down to 0 in xTaskResumeAll(). */ + configASSERT( uxSchedulerSuspended == 0 ); + + /* Use xPendedTicks to mimic xTicksToCatchUp number of ticks occurring when + the scheduler is suspended so the ticks are executed in xTaskResumeAll(). */ + vTaskSuspendAll(); + xPendedTicks += xTicksToCatchUp; + xYieldRequired = xTaskResumeAll(); + + return xYieldRequired; +} +/*----------------------------------------------------------*/ + #if ( INCLUDE_xTaskAbortDelay == 1 ) BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) { - TCB_t *pxTCB = ( TCB_t * ) xTask; + TCB_t *pxTCB = xTask; BaseType_t xReturn; configASSERT( pxTCB ); @@ -2535,6 +2655,10 @@ implementations require configUSE_TICKLESS_IDLE to be set to a value other than if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) { ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + + /* This lets the task know it was forcibly removed from the + blocked state so it should not re-evaluate its block time and + then block again. */ pxTCB->ucDelayAborted = pdTRUE; } else @@ -2633,7 +2757,7 @@ BaseType_t xSwitchRequired = pdFALSE; item at the head of the delayed list. This is the time at which the task at the head of the delayed list must be removed from the Blocked state. */ - pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); if( xConstTickCount < xItemValue ) @@ -2644,7 +2768,7 @@ BaseType_t xSwitchRequired = pdFALSE; state - so record the item value in xNextTaskUnblockTime. */ xNextTaskUnblockTime = xItemValue; - break; + break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ } else { @@ -2711,7 +2835,7 @@ BaseType_t xSwitchRequired = pdFALSE; { /* Guard against the tick hook being called when the pended tick count is being unwound (when the scheduler is being unlocked). */ - if( uxPendedTicks == ( UBaseType_t ) 0U ) + if( xPendedTicks == ( TickType_t ) 0 ) { vApplicationTickHook(); } @@ -2721,10 +2845,23 @@ BaseType_t xSwitchRequired = pdFALSE; } } #endif /* configUSE_TICK_HOOK */ + + #if ( configUSE_PREEMPTION == 1 ) + { + if( xYieldPending != pdFALSE ) + { + xSwitchRequired = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_PREEMPTION */ } else { - ++uxPendedTicks; + ++xPendedTicks; /* The tick hook gets called at regular intervals, even if the scheduler is locked. */ @@ -2735,19 +2872,6 @@ BaseType_t xSwitchRequired = pdFALSE; #endif } - #if ( configUSE_PREEMPTION == 1 ) - { - if( xYieldPending != pdFALSE ) - { - xSwitchRequired = pdTRUE; - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - } - #endif /* configUSE_PREEMPTION */ - return xSwitchRequired; } /*-----------------------------------------------------------*/ @@ -2766,13 +2890,15 @@ BaseType_t xSwitchRequired = pdFALSE; } else { - xTCB = ( TCB_t * ) xTask; + xTCB = xTask; } /* Save the hook function in the TCB. A critical section is required as the value can be accessed from an interrupt. */ taskENTER_CRITICAL(); + { xTCB->pxTaskTag = pxHookFunction; + } taskEXIT_CRITICAL(); } @@ -2783,24 +2909,17 @@ BaseType_t xSwitchRequired = pdFALSE; TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) { - TCB_t *xTCB; + TCB_t *pxTCB; TaskHookFunction_t xReturn; - /* If xTask is NULL then we are setting our own task hook. */ - if( xTask == NULL ) - { - xTCB = ( TCB_t * ) pxCurrentTCB; - } - else - { - xTCB = ( TCB_t * ) xTask; - } + /* If xTask is NULL then set the calling task's hook. */ + pxTCB = prvGetTCBFromHandle( xTask ); /* Save the hook function in the TCB. A critical section is required as the value can be accessed from an interrupt. */ taskENTER_CRITICAL(); { - xReturn = xTCB->pxTaskTag; + xReturn = pxTCB->pxTaskTag; } taskEXIT_CRITICAL(); @@ -2810,6 +2929,31 @@ BaseType_t xSwitchRequired = pdFALSE; #endif /* configUSE_APPLICATION_TASK_TAG */ /*-----------------------------------------------------------*/ +#if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) + { + TCB_t *pxTCB; + TaskHookFunction_t xReturn; + UBaseType_t uxSavedInterruptStatus; + + /* If xTask is NULL then set the calling task's hook. */ + pxTCB = prvGetTCBFromHandle( xTask ); + + /* Save the hook function in the TCB. A critical section is required as + the value can be accessed from an interrupt. */ + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + xReturn = pxTCB->pxTaskTag; + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; + } + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) @@ -2820,11 +2964,11 @@ BaseType_t xSwitchRequired = pdFALSE; /* If xTask is NULL then we are calling our own task hook. */ if( xTask == NULL ) { - xTCB = ( TCB_t * ) pxCurrentTCB; + xTCB = pxCurrentTCB; } else { - xTCB = ( TCB_t * ) xTask; + xTCB = xTask; } if( xTCB->pxTaskTag != NULL ) @@ -2857,43 +3001,59 @@ void vTaskSwitchContext( void ) #if ( configGENERATE_RUN_TIME_STATS == 1 ) { - #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE - portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime ); - #else - ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE(); - #endif + #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE + portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime ); + #else + ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE(); + #endif - /* Add the amount of time the task has been running to the - accumulated time so far. The time the task started running was - stored in ulTaskSwitchedInTime. Note that there is no overflow - protection here so count values are only valid until the timer - overflows. The guard against negative values is to protect - against suspect run time stat counter implementations - which - are provided by the application, not the kernel. */ - if( ulTotalRunTime > ulTaskSwitchedInTime ) - { - pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime ); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - ulTaskSwitchedInTime = ulTotalRunTime; + /* Add the amount of time the task has been running to the + accumulated time so far. The time the task started running was + stored in ulTaskSwitchedInTime. Note that there is no overflow + protection here so count values are only valid until the timer + overflows. The guard against negative values is to protect + against suspect run time stat counter implementations - which + are provided by the application, not the kernel. */ + if( ulTotalRunTime > ulTaskSwitchedInTime ) + { + pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + ulTaskSwitchedInTime = ulTotalRunTime; } #endif /* configGENERATE_RUN_TIME_STATS */ /* Check for stack overflow, if configured. */ taskCHECK_FOR_STACK_OVERFLOW(); + /* Before the currently running task is switched out, save its errno. */ + #if( configUSE_POSIX_ERRNO == 1 ) + { + pxCurrentTCB->iTaskErrno = FreeRTOS_errno; + } + #endif + /* Select a new task to run using either the generic C or port optimised asm code. */ - taskSELECT_HIGHEST_PRIORITY_TASK(); + taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ traceTASK_SWITCHED_IN(); + /* After the new task is switched in, update the global errno. */ + #if( configUSE_POSIX_ERRNO == 1 ) + { + FreeRTOS_errno = pxCurrentTCB->iTaskErrno; + } + #endif + #if ( configUSE_NEWLIB_REENTRANT == 1 ) { /* Switch Newlib's _impure_ptr variable to point to the _reent - structure specific to this task. */ + structure specific to this task. + See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); } #endif /* configUSE_NEWLIB_REENTRANT */ @@ -2993,7 +3153,7 @@ BaseType_t xReturn; This function assumes that a check has already been made to ensure that pxEventList is not empty. */ - pxUnblockedTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); + pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ configASSERT( pxUnblockedTCB ); ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); @@ -3001,6 +3161,20 @@ BaseType_t xReturn; { ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); prvAddTaskToReadyList( pxUnblockedTCB ); + + #if( configUSE_TICKLESS_IDLE != 0 ) + { + /* If a task is blocked on a kernel object then xNextTaskUnblockTime + might be set to the blocked task's time out time. If the task is + unblocked for a reason other than a timeout xNextTaskUnblockTime is + normally left unchanged, because it is automatically reset to a new + value when the tick count equals xNextTaskUnblockTime. However if + tickless idling is used it might be more important to enter sleep mode + at the earliest possible time - so reset xNextTaskUnblockTime here to + ensure it is updated at the earliest possible time. */ + prvResetNextTaskUnblockTime(); + } + #endif } else { @@ -3025,20 +3199,6 @@ BaseType_t xReturn; xReturn = pdFALSE; } - #if( configUSE_TICKLESS_IDLE != 0 ) - { - /* If a task is blocked on a kernel object then xNextTaskUnblockTime - might be set to the blocked task's time out time. If the task is - unblocked for a reason other than a timeout xNextTaskUnblockTime is - normally left unchanged, because it is automatically reset to a new - value when the tick count equals xNextTaskUnblockTime. However if - tickless idling is used it might be more important to enter sleep mode - at the earliest possible time - so reset xNextTaskUnblockTime here to - ensure it is updated at the earliest possible time. */ - prvResetNextTaskUnblockTime(); - } - #endif - return xReturn; } /*-----------------------------------------------------------*/ @@ -3056,10 +3216,24 @@ TCB_t *pxUnblockedTCB; /* Remove the event list form the event flag. Interrupts do not access event flags. */ - pxUnblockedTCB = ( TCB_t * ) listGET_LIST_ITEM_OWNER( pxEventListItem ); + pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ configASSERT( pxUnblockedTCB ); ( void ) uxListRemove( pxEventListItem ); + #if( configUSE_TICKLESS_IDLE != 0 ) + { + /* If a task is blocked on a kernel object then xNextTaskUnblockTime + might be set to the blocked task's time out time. If the task is + unblocked for a reason other than a timeout xNextTaskUnblockTime is + normally left unchanged, because it is automatically reset to a new + value when the tick count equals xNextTaskUnblockTime. However if + tickless idling is used it might be more important to enter sleep mode + at the earliest possible time - so reset xNextTaskUnblockTime here to + ensure it is updated at the earliest possible time. */ + prvResetNextTaskUnblockTime(); + } + #endif + /* Remove the task from the delayed list and add it to the ready list. The scheduler is suspended so interrupts will not be accessing the ready lists. */ @@ -3111,7 +3285,7 @@ BaseType_t xReturn; const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; #if( INCLUDE_xTaskAbortDelay == 1 ) - if( pxCurrentTCB->ucDelayAborted != pdFALSE ) + if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE ) { /* The delay was aborted, which is not the same as a time out, but has the same result. */ @@ -3171,11 +3345,11 @@ void vTaskMissedYield( void ) UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) { UBaseType_t uxReturn; - TCB_t *pxTCB; + TCB_t const *pxTCB; if( xTask != NULL ) { - pxTCB = ( TCB_t * ) xTask; + pxTCB = xTask; uxReturn = pxTCB->uxTaskNumber; } else @@ -3193,11 +3367,11 @@ void vTaskMissedYield( void ) void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) { - TCB_t *pxTCB; + TCB_t * pxTCB; if( xTask != NULL ) { - pxTCB = ( TCB_t * ) xTask; + pxTCB = xTask; pxTCB->uxTaskNumber = uxHandle; } } @@ -3226,7 +3400,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters ) /* In case a task that has a secure context deletes itself, in which case the idle task is responsible for deleting the task's secure context, if any. */ - portTASK_CALLS_SECURE_FUNCTIONS(); + portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE ); for( ;; ) { @@ -3340,6 +3514,8 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters ) const UBaseType_t uxNonApplicationTasks = 1; eSleepModeStatus eReturn = eStandardSleep; + /* This function must be called from a critical section. */ + if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 ) { /* A task was made ready while the scheduler was suspended. */ @@ -3381,6 +3557,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters ) if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS ) { pxTCB = prvGetTCBFromHandle( xTaskToSet ); + configASSERT( pxTCB != NULL ); pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue; } } @@ -3468,13 +3645,13 @@ static void prvCheckTasksWaitingTermination( void ) { TCB_t *pxTCB; - /* uxDeletedTasksWaitingCleanUp is used to prevent vTaskSuspendAll() + /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() being called too often in the idle task. */ while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) { taskENTER_CRITICAL(); { - pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); --uxCurrentNumberOfTasks; --uxDeletedTasksWaitingCleanUp; @@ -3593,7 +3770,7 @@ static void prvCheckTasksWaitingTermination( void ) if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 ) { - listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); + listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ /* Populate an TaskStatus_t structure within the pxTaskStatusArray array for each task that is referenced from @@ -3601,7 +3778,7 @@ static void prvCheckTasksWaitingTermination( void ) meaning of each TaskStatus_t structure member. */ do { - listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); + listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState ); uxTask++; } while( pxNextTCB != pxFirstTCB ); @@ -3617,9 +3794,9 @@ static void prvCheckTasksWaitingTermination( void ) #endif /* configUSE_TRACE_FACILITY */ /*-----------------------------------------------------------*/ -#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) +#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) - static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) + static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) { uint32_t ulCount = 0U; @@ -3631,10 +3808,50 @@ static void prvCheckTasksWaitingTermination( void ) ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */ - return ( uint16_t ) ulCount; + return ( configSTACK_DEPTH_TYPE ) ulCount; } -#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) */ +#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + /* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the + same except for their return type. Using configSTACK_DEPTH_TYPE allows the + user to determine the return type. It gets around the problem of the value + overflowing on 8-bit types without breaking backward compatibility for + applications that expect an 8-bit return type. */ + configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) + { + TCB_t *pxTCB; + uint8_t *pucEndOfStack; + configSTACK_DEPTH_TYPE uxReturn; + + /* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are + the same except for their return type. Using configSTACK_DEPTH_TYPE + allows the user to determine the return type. It gets around the + problem of the value overflowing on 8-bit types without breaking + backward compatibility for applications that expect an 8-bit return + type. */ + + pxTCB = prvGetTCBFromHandle( xTask ); + + #if portSTACK_GROWTH < 0 + { + pucEndOfStack = ( uint8_t * ) pxTCB->pxStack; + } + #else + { + pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack; + } + #endif + + uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack ); + + return uxReturn; + } + +#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */ /*-----------------------------------------------------------*/ #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) @@ -3675,7 +3892,9 @@ static void prvCheckTasksWaitingTermination( void ) portCLEAN_UP_TCB( pxTCB ); /* Free up the memory allocated by the scheduler for the task. It is up - to the task to free any memory allocated at the application level. */ + to the task to free any memory allocated at the application level. + See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + for additional information. */ #if ( configUSE_NEWLIB_REENTRANT == 1 ) { _reclaim_reent( &( pxTCB->xNewLib_reent ) ); @@ -3689,7 +3908,7 @@ static void prvCheckTasksWaitingTermination( void ) vPortFree( pxTCB->pxStack ); vPortFree( pxTCB ); } - #elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 Macro has been consolidated for readability reasons. */ + #elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* The task could have been allocated statically or dynamically, so check what was statically allocated before trying to free the @@ -3739,7 +3958,7 @@ TCB_t *pxTCB; the item at the head of the delayed list. This is the time at which the task at the head of the delayed list should be removed from the Blocked state. */ - ( pxTCB ) = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); + ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); } } @@ -3794,7 +4013,7 @@ TCB_t *pxTCB; BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) { - TCB_t * const pxMutexHolderTCB = ( TCB_t * ) pxMutexHolder; + TCB_t * const pxMutexHolderTCB = pxMutexHolder; BaseType_t xReturn = pdFALSE; /* If the mutex was given back by an interrupt while the queue was @@ -3825,7 +4044,10 @@ TCB_t *pxTCB; { if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) { - taskRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority ); + /* It is known that the task is in its ready list so + there is no need to check again and the port level + reset macro can be called directly. */ + portRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority, uxTopReadyPriority ); } else { @@ -3881,7 +4103,7 @@ TCB_t *pxTCB; BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) { - TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder; + TCB_t * const pxTCB = pxMutexHolder; BaseType_t xReturn = pdFALSE; if( pxMutexHolder != NULL ) @@ -3905,7 +4127,7 @@ TCB_t *pxTCB; the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. Remove - the holding task from the ready list. */ + the holding task from the ready/delayed list. */ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) { taskRESET_READY_PRIORITY( pxTCB->uxPriority ); @@ -3961,7 +4183,7 @@ TCB_t *pxTCB; void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) { - TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder; + TCB_t * const pxTCB = pxMutexHolder; UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse; const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1; @@ -4026,7 +4248,10 @@ TCB_t *pxTCB; { if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) { - taskRESET_READY_PRIORITY( pxTCB->uxPriority ); + /* It is known that the task is in its ready list so + there is no need to check again and the port level + reset macro can be called directly. */ + portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority ); } else { @@ -4139,7 +4364,7 @@ TCB_t *pxTCB; } /* Terminate. */ - pcBuffer[ x ] = 0x00; + pcBuffer[ x ] = ( char ) 0x00; /* Return the new end of string. */ return &( pcBuffer[ x ] ); @@ -4153,7 +4378,7 @@ TCB_t *pxTCB; void vTaskList( char * pcWriteBuffer ) { TaskStatus_t *pxTaskStatusArray; - volatile UBaseType_t uxArraySize, x; + UBaseType_t uxArraySize, x; char cStatus; /* @@ -4182,7 +4407,7 @@ TCB_t *pxTCB; /* Make sure the write buffer does not contain a string. */ - *pcWriteBuffer = 0x00; + *pcWriteBuffer = ( char ) 0x00; /* Take a snapshot of the number of tasks in case it changes while this function is executing. */ @@ -4191,7 +4416,7 @@ TCB_t *pxTCB; /* Allocate an array index for each task. NOTE! if configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will equate to NULL. */ - pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); + pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */ if( pxTaskStatusArray != NULL ) { @@ -4218,9 +4443,10 @@ TCB_t *pxTCB; case eDeleted: cStatus = tskDELETED_CHAR; break; + case eInvalid: /* Fall through. */ default: /* Should not get here, but it is included to prevent static checking errors. */ - cStatus = 0x00; + cStatus = ( char ) 0x00; break; } @@ -4229,8 +4455,8 @@ TCB_t *pxTCB; pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName ); /* Write the rest of the string. */ - sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); - pcWriteBuffer += strlen( pcWriteBuffer ); + sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */ + pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */ } /* Free the array again. NOTE! If configSUPPORT_DYNAMIC_ALLOCATION @@ -4251,7 +4477,7 @@ TCB_t *pxTCB; void vTaskGetRunTimeStats( char *pcWriteBuffer ) { TaskStatus_t *pxTaskStatusArray; - volatile UBaseType_t uxArraySize, x; + UBaseType_t uxArraySize, x; uint32_t ulTotalTime, ulStatsAsPercentage; #if( configUSE_TRACE_FACILITY != 1 ) @@ -4286,7 +4512,7 @@ TCB_t *pxTCB; */ /* Make sure the write buffer does not contain a string. */ - *pcWriteBuffer = 0x00; + *pcWriteBuffer = ( char ) 0x00; /* Take a snapshot of the number of tasks in case it changes while this function is executing. */ @@ -4295,7 +4521,7 @@ TCB_t *pxTCB; /* Allocate an array index for each task. NOTE! If configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will equate to NULL. */ - pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); + pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */ if( pxTaskStatusArray != NULL ) { @@ -4306,7 +4532,7 @@ TCB_t *pxTCB; ulTotalTime /= 100UL; /* Avoid divide by zero errors. */ - if( ulTotalTime > 0 ) + if( ulTotalTime > 0UL ) { /* Create a human readable table from the binary data. */ for( x = 0; x < uxArraySize; x++ ) @@ -4331,7 +4557,7 @@ TCB_t *pxTCB; { /* sizeof( int ) == sizeof( long ) so a smaller printf() library can be used. */ - sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); + sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */ } #endif } @@ -4347,12 +4573,12 @@ TCB_t *pxTCB; { /* sizeof( int ) == sizeof( long ) so a smaller printf() library can be used. */ - sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); + sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */ } #endif } - pcWriteBuffer += strlen( pcWriteBuffer ); + pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */ } } else @@ -4389,7 +4615,7 @@ TickType_t uxReturn; #if ( configUSE_MUTEXES == 1 ) - void *pvTaskIncrementMutexHeldCount( void ) + TaskHandle_t pvTaskIncrementMutexHeldCount( void ) { /* If xSemaphoreCreateMutex() is called before any tasks have been created then pxCurrentTCB will be NULL. */ @@ -4561,7 +4787,7 @@ TickType_t uxReturn; uint8_t ucOriginalNotifyState; configASSERT( xTaskToNotify ); - pxTCB = ( TCB_t * ) xTaskToNotify; + pxTCB = xTaskToNotify; taskENTER_CRITICAL(); { @@ -4604,6 +4830,14 @@ TickType_t uxReturn; /* The task is being notified without its notify value being updated. */ break; + + default: + /* Should not get here if all enums are handled. + Artificially force an assert by testing a value the + compiler can't assume is const. */ + configASSERT( pxTCB->ulNotifiedValue == ~0UL ); + + break; } traceTASK_NOTIFY(); @@ -4687,7 +4921,7 @@ TickType_t uxReturn; http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); - pxTCB = ( TCB_t * ) xTaskToNotify; + pxTCB = xTaskToNotify; uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); { @@ -4729,6 +4963,13 @@ TickType_t uxReturn; /* The task is being notified without its notify value being updated. */ break; + + default: + /* Should not get here if all enums are handled. + Artificially force an assert by testing a value the + compiler can't assume is const. */ + configASSERT( pxTCB->ulNotifiedValue == ~0UL ); + break; } traceTASK_NOTIFY_FROM_ISR(); @@ -4760,13 +5001,11 @@ TickType_t uxReturn; { *pxHigherPriorityTaskWoken = pdTRUE; } - else - { - /* Mark that a yield is pending in case the user is not - using the "xHigherPriorityTaskWoken" parameter to an ISR - safe FreeRTOS function. */ - xYieldPending = pdTRUE; - } + + /* Mark that a yield is pending in case the user is not + using the "xHigherPriorityTaskWoken" parameter to an ISR + safe FreeRTOS function. */ + xYieldPending = pdTRUE; } else { @@ -4810,7 +5049,7 @@ TickType_t uxReturn; http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); - pxTCB = ( TCB_t * ) xTaskToNotify; + pxTCB = xTaskToNotify; uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); { @@ -4850,13 +5089,11 @@ TickType_t uxReturn; { *pxHigherPriorityTaskWoken = pdTRUE; } - else - { - /* Mark that a yield is pending in case the user is not - using the "xHigherPriorityTaskWoken" parameter in an ISR - safe FreeRTOS function. */ - xYieldPending = pdTRUE; - } + + /* Mark that a yield is pending in case the user is not + using the "xHigherPriorityTaskWoken" parameter in an ISR + safe FreeRTOS function. */ + xYieldPending = pdTRUE; } else { @@ -4868,7 +5105,6 @@ TickType_t uxReturn; } #endif /* configUSE_TASK_NOTIFICATIONS */ - /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) @@ -4902,6 +5138,41 @@ TickType_t uxReturn; #endif /* configUSE_TASK_NOTIFICATIONS */ /*-----------------------------------------------------------*/ +#if( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear ) + { + TCB_t *pxTCB; + uint32_t ulReturn; + + /* If null is passed in here then it is the calling task that is having + its notification state cleared. */ + pxTCB = prvGetTCBFromHandle( xTask ); + + taskENTER_CRITICAL(); + { + /* Return the notification as it was before the bits were cleared, + then clear the bit mask. */ + ulReturn = pxCurrentTCB->ulNotifiedValue; + pxTCB->ulNotifiedValue &= ~ulBitsToClear; + } + taskEXIT_CRITICAL(); + + return ulReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + uint32_t ulTaskGetIdleRunTimeCounter( void ) + { + return xIdleTaskHandle->ulRunTimeCounter; + } + +#endif +/*-----------------------------------------------------------*/ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) { @@ -4923,7 +5194,7 @@ const TickType_t xConstTickCount = xTickCount; { /* The current task must be in a ready list, so there is no need to check, and the port reset macro can be called directly. */ - portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); + portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */ } else { @@ -5027,12 +5298,12 @@ when performing module tests). */ #include "freertos_tasks_c_additions.h" - static void freertos_tasks_c_additions_init( void ) - { - #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT + #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT + static void freertos_tasks_c_additions_init( void ) + { FREERTOS_TASKS_C_ADDITIONS_INIT(); - #endif - } + } + #endif #endif diff --git a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/timers.c b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/timers.c index 8a5d99c..d10c832 100644 --- a/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/timers.c +++ b/Software/VNA_embedded/Middlewares/Third_Party/FreeRTOS/Source/timers.c @@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.0.1 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -42,11 +42,11 @@ task.h is included from an application file. */ #error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available. #endif -/* Lint e961 and e750 are suppressed as a MISRA exception justified because the -MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the -header files above, but not in this file, in order to generate the correct -privileged Vs unprivileged linkage and placement. */ -#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */ +/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified +because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined +for the header files above, but not in this file, in order to generate the +correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */ /* This entire source file will be skipped if the application is not configured @@ -64,22 +64,23 @@ defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */ #define configTIMER_SERVICE_TASK_NAME "Tmr Svc" #endif +/* Bit definitions used in the ucStatus member of a timer structure. */ +#define tmrSTATUS_IS_ACTIVE ( ( uint8_t ) 0x01 ) +#define tmrSTATUS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 0x02 ) +#define tmrSTATUS_IS_AUTORELOAD ( ( uint8_t ) 0x04 ) + /* The definition of the timers themselves. */ -typedef struct tmrTimerControl +typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */ { const char *pcTimerName; /*<< Text name. This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ ListItem_t xTimerListItem; /*<< Standard linked list item as used by all kernel features for event management. */ TickType_t xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */ - UBaseType_t uxAutoReload; /*<< Set to pdTRUE if the timer should be automatically restarted once expired. Set to pdFALSE if the timer is, in effect, a one-shot timer. */ void *pvTimerID; /*<< An ID to identify the timer. This allows the timer to be identified when the same callback is used for multiple timers. */ TimerCallbackFunction_t pxCallbackFunction; /*<< The function that will be called when the timer expires. */ #if( configUSE_TRACE_FACILITY == 1 ) UBaseType_t uxTimerNumber; /*<< An ID assigned by trace tools such as FreeRTOS+Trace */ #endif - - #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) - uint8_t ucStaticallyAllocated; /*<< Set to pdTRUE if the timer was created statically so no attempt is made to free the memory again if the timer is later deleted. */ - #endif + uint8_t ucStatus; /*<< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */ } xTIMER; /* The old xTIMER name is maintained above then typedefed to the new Timer_t @@ -127,11 +128,14 @@ which static variables must be declared volatile. */ /* The list in which active timers are stored. Timers are referenced in expire time order, with the nearest expiry time at the front of the list. Only the -timer service task is allowed to access these lists. */ -PRIVILEGED_DATA static List_t xActiveTimerList1 = {0}; -PRIVILEGED_DATA static List_t xActiveTimerList2 = {0}; -PRIVILEGED_DATA static List_t *pxCurrentTimerList = NULL; -PRIVILEGED_DATA static List_t *pxOverflowTimerList = NULL; +timer service task is allowed to access these lists. +xActiveTimerList1 and xActiveTimerList2 could be at function scope but that +breaks some kernel aware debuggers, and debuggers that reply on removing the +static qualifier. */ +PRIVILEGED_DATA static List_t xActiveTimerList1; +PRIVILEGED_DATA static List_t xActiveTimerList2; +PRIVILEGED_DATA static List_t *pxCurrentTimerList; +PRIVILEGED_DATA static List_t *pxOverflowTimerList; /* A queue that is used to send commands to the timer service task. */ PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL; @@ -162,7 +166,7 @@ static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION; * task. Other tasks communicate with the timer service task using the * xTimerQueue queue. */ -static void prvTimerTask( void *pvParameters ) PRIVILEGED_FUNCTION; +static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION; /* * Called by the timer service task to interpret and process a command it @@ -178,7 +182,7 @@ static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const Tic /* * An active timer has reached its expire time. Reload the timer if it is an - * auto reload timer, then call its callback. + * auto-reload timer, then call its callback. */ static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) PRIVILEGED_FUNCTION; @@ -283,26 +287,21 @@ BaseType_t xReturn = pdFAIL; { Timer_t *pxNewTimer; - pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); + pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */ if( pxNewTimer != NULL ) { + /* Status is thus far zero as the timer is not created statically + and has not been started. The auto-reload bit may get set in + prvInitialiseNewTimer. */ + pxNewTimer->ucStatus = 0x00; prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); - - #if( configSUPPORT_STATIC_ALLOCATION == 1 ) - { - /* Timers can be created statically or dynamically, so note this - timer was created dynamically in case the timer is later - deleted. */ - pxNewTimer->ucStaticallyAllocated = pdFALSE; - } - #endif /* configSUPPORT_STATIC_ALLOCATION */ } return pxNewTimer; } -#endif /* configSUPPORT_STATIC_ALLOCATION */ +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ /*-----------------------------------------------------------*/ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) @@ -323,24 +322,22 @@ BaseType_t xReturn = pdFAIL; structure. */ volatile size_t xSize = sizeof( StaticTimer_t ); configASSERT( xSize == sizeof( Timer_t ) ); + ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ } #endif /* configASSERT_DEFINED */ /* A pointer to a StaticTimer_t structure MUST be provided, use it. */ configASSERT( pxTimerBuffer ); - pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ + pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */ if( pxNewTimer != NULL ) { - prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); + /* Timers can be created statically or dynamically so note this + timer was created statically in case it is later deleted. The + auto-reload bit may get set in prvInitialiseNewTimer(). */ + pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED; - #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) - { - /* Timers can be created statically or dynamically so note this - timer was created statically in case it is later deleted. */ - pxNewTimer->ucStaticallyAllocated = pdTRUE; - } - #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); } return pxNewTimer; @@ -369,10 +366,13 @@ static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e97 parameters. */ pxNewTimer->pcTimerName = pcTimerName; pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks; - pxNewTimer->uxAutoReload = uxAutoReload; pxNewTimer->pvTimerID = pvTimerID; pxNewTimer->pxCallbackFunction = pxCallbackFunction; vListInitialiseItem( &( pxNewTimer->xTimerListItem ) ); + if( uxAutoReload != pdFALSE ) + { + pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD; + } traceTIMER_CREATE( pxNewTimer ); } } @@ -392,7 +392,7 @@ DaemonTaskMessage_t xMessage; /* Send a command to the timer service task to start the xTimer timer. */ xMessage.xMessageID = xCommandID; xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; - xMessage.u.xTimerParameters.pxTimer = ( Timer_t * ) xTimer; + xMessage.u.xTimerParameters.pxTimer = xTimer; if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) { @@ -432,16 +432,61 @@ TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) { -Timer_t *pxTimer = ( Timer_t * ) xTimer; +Timer_t *pxTimer = xTimer; configASSERT( xTimer ); return pxTimer->xTimerPeriodInTicks; } /*-----------------------------------------------------------*/ +void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) +{ +Timer_t * pxTimer = xTimer; + + configASSERT( xTimer ); + taskENTER_CRITICAL(); + { + if( uxAutoReload != pdFALSE ) + { + pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD; + } + else + { + pxTimer->ucStatus &= ~tmrSTATUS_IS_AUTORELOAD; + } + } + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) +{ +Timer_t * pxTimer = xTimer; +UBaseType_t uxReturn; + + configASSERT( xTimer ); + taskENTER_CRITICAL(); + { + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0 ) + { + /* Not an auto-reload timer. */ + uxReturn = ( UBaseType_t ) pdFALSE; + } + else + { + /* Is an auto-reload timer. */ + uxReturn = ( UBaseType_t ) pdTRUE; + } + } + taskEXIT_CRITICAL(); + + return uxReturn; +} +/*-----------------------------------------------------------*/ + TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) { -Timer_t * pxTimer = ( Timer_t * ) xTimer; +Timer_t * pxTimer = xTimer; TickType_t xReturn; configASSERT( xTimer ); @@ -452,7 +497,7 @@ TickType_t xReturn; const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ { -Timer_t *pxTimer = ( Timer_t * ) xTimer; +Timer_t *pxTimer = xTimer; configASSERT( xTimer ); return pxTimer->pcTimerName; @@ -462,16 +507,16 @@ Timer_t *pxTimer = ( Timer_t * ) xTimer; static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) { BaseType_t xResult; -Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); +Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ /* Remove the timer from the list of active timers. A check has already been performed to ensure the list is not empty. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); traceTIMER_EXPIRED( pxTimer ); - /* If the timer is an auto reload timer then calculate the next + /* If the timer is an auto-reload timer then calculate the next expiry time and re-insert the timer in the list of active timers. */ - if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE ) + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) { /* The timer is inserted into a list using a time relative to anything other than the current time. It will therefore be inserted into the @@ -491,6 +536,7 @@ Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTi } else { + pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; mtCOVERAGE_TEST_MARKER(); } @@ -499,7 +545,7 @@ Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTi } /*-----------------------------------------------------------*/ -static void prvTimerTask( void *pvParameters ) +static portTASK_FUNCTION( prvTimerTask, pvParameters ) { TickType_t xNextExpireTime; BaseType_t xListWasEmpty; @@ -747,11 +793,12 @@ TickType_t xTimeNow; switch( xMessage.xMessageID ) { case tmrCOMMAND_START : - case tmrCOMMAND_START_FROM_ISR : - case tmrCOMMAND_RESET : - case tmrCOMMAND_RESET_FROM_ISR : + case tmrCOMMAND_START_FROM_ISR : + case tmrCOMMAND_RESET : + case tmrCOMMAND_RESET_FROM_ISR : case tmrCOMMAND_START_DONT_TRACE : /* Start or restart a timer. */ + pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) { /* The timer expired before it was added to the active @@ -759,7 +806,7 @@ TickType_t xTimeNow; pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); traceTIMER_EXPIRED( pxTimer ); - if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE ) + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY ); configASSERT( xResult ); @@ -778,12 +825,13 @@ TickType_t xTimeNow; case tmrCOMMAND_STOP : case tmrCOMMAND_STOP_FROM_ISR : - /* The timer has already been removed from the active list. - There is nothing to do here. */ + /* The timer has already been removed from the active list. */ + pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; break; case tmrCOMMAND_CHANGE_PERIOD : case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR : + pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); @@ -797,29 +845,28 @@ TickType_t xTimeNow; break; case tmrCOMMAND_DELETE : - /* The timer has already been removed from the active list, - just free up the memory if the memory was dynamically - allocated. */ - #if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { - /* The timer can only have been allocated dynamically - - free it again. */ - vPortFree( pxTimer ); - } - #elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) - { - /* The timer could have been allocated statically or - dynamically, so check before attempting to free the - memory. */ - if( pxTimer->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) + /* The timer has already been removed from the active list, + just free up the memory if the memory was dynamically + allocated. */ + if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) { vPortFree( pxTimer ); } else { - mtCOVERAGE_TEST_MARKER(); + pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; } } + #else + { + /* If dynamic allocation is not enabled, the memory + could not have been dynamically allocated. So there is + no need to free the memory - just mark the timer as + "not active". */ + pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; + } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ break; @@ -848,7 +895,7 @@ BaseType_t xResult; xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); /* Remove the timer from the list. */ - pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); + pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); traceTIMER_EXPIRED( pxTimer ); @@ -857,7 +904,7 @@ BaseType_t xResult; have not yet been switched. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); - if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE ) + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) { /* Calculate the reload value, and if the reload value results in the timer going into the same timer list then it has already expired @@ -944,28 +991,32 @@ static void prvCheckForValidListAndQueue( void ) BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) { -BaseType_t xTimerIsInActiveList; -Timer_t *pxTimer = ( Timer_t * ) xTimer; +BaseType_t xReturn; +Timer_t *pxTimer = xTimer; configASSERT( xTimer ); /* Is the timer in the list of active timers? */ taskENTER_CRITICAL(); { - /* Checking to see if it is in the NULL list in effect checks to see if - it is referenced from either the current or the overflow timer lists in - one go, but the logic has to be reversed, hence the '!'. */ - xTimerIsInActiveList = ( BaseType_t ) !( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) ); /*lint !e961. Cast is only redundant when NULL is passed into the macro. */ + if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } } taskEXIT_CRITICAL(); - return xTimerIsInActiveList; + return xReturn; } /*lint !e818 Can't be pointer to const due to the typedef. */ /*-----------------------------------------------------------*/ void *pvTimerGetTimerID( const TimerHandle_t xTimer ) { -Timer_t * const pxTimer = ( Timer_t * ) xTimer; +Timer_t * const pxTimer = xTimer; void *pvReturn; configASSERT( xTimer ); @@ -982,7 +1033,7 @@ void *pvReturn; void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) { -Timer_t * const pxTimer = ( Timer_t * ) xTimer; +Timer_t * const pxTimer = xTimer; configASSERT( xTimer ); diff --git a/Software/VNA_embedded/New_configuration.cfg b/Software/VNA_embedded/New_configuration.cfg deleted file mode 100644 index 87ae1cd..0000000 --- a/Software/VNA_embedded/New_configuration.cfg +++ /dev/null @@ -1,36 +0,0 @@ -# This is an VNA_embedded board with a single STM32L432KCUx chip -# -# Generated by System Workbench for STM32 -# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s) - -source [find interface/stlink.cfg] - -set WORKAREASIZE 0x8000 - -transport select "hla_swd" - -set CHIPNAME STM32G432CBUx -set BOARDNAME VNA_embedded - -# CHIPNAMES state -set CHIPNAME_CPU0_ACTIVATED 1 - -# Enable debug when in low power modes -set ENABLE_LOW_POWER 1 - -# Stop Watchdog counters when halt -set STOP_WATCHDOG 1 - -# STlink Debug clock frequency -set CLOCK_FREQ 8000 - -# use hardware reset, connect under reset -# connect_assert_srst needed if low power mode application running (WFI...) -reset_config srst_only srst_nogate connect_assert_srst -set CONNECT_UNDER_RESET 1 - -# BCTM CPU variables - - - -source [find target/stm32g4x.cfg] diff --git a/Software/VNA_embedded/STM32G431CBUx_FLASH.ld b/Software/VNA_embedded/STM32G431CBUX_FLASH.ld similarity index 50% rename from Software/VNA_embedded/STM32G431CBUx_FLASH.ld rename to Software/VNA_embedded/STM32G431CBUX_FLASH.ld index 79f439c..8dbfaf1 100644 --- a/Software/VNA_embedded/STM32G431CBUx_FLASH.ld +++ b/Software/VNA_embedded/STM32G431CBUX_FLASH.ld @@ -1,189 +1,185 @@ -/* -****************************************************************************** -** - -** File : LinkerScript.ld -** -** Author : Auto-generated by Ac6 System Workbench -** -** Abstract : Linker script for STM32G431CBUx series -** 128Kbytes FLASH and 32Kbytes RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** Target : STMicroelectronics STM32 -** -** Distribution: The file is distributed “as is,†without any warranty -** of any kind. -** -***************************************************************************** -** @attention -** -**

© COPYRIGHT(c) 2014 Ac6

-** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** 1. Redistributions of source code must retain the above copyright notice, -** this list of conditions and the following disclaimer. -** 2. Redistributions in binary form must reproduce the above copyright notice, -** this list of conditions and the following disclaimer in the documentation -** and/or other materials provided with the distribution. -** 3. Neither the name of Ac6 nor the names of its contributors -** may be used to endorse or promote products derived from this software -** without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x20008000; /* end of RAM */ -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ -RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K -FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data goes into FLASH */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >RAM AT> FLASH - - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} - - +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32G431CBUx Device from STM32G4 series +** 128Kbytes FLASH +** 32Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200 ; /* required amount of heap */ +_Min_Stack_Size = 0x400 ; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/Software/VNA_embedded/Src/app_freertos.c b/Software/VNA_embedded/Src/app_freertos.c index c3e077d..28bd50e 100644 --- a/Software/VNA_embedded/Src/app_freertos.c +++ b/Software/VNA_embedded/Src/app_freertos.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -50,7 +49,7 @@ /* Private function prototypes -----------------------------------------------*/ /* USER CODE BEGIN FunctionPrototypes */ - + /* USER CODE END FunctionPrototypes */ /* GetIdleTaskMemory prototype (linked to static allocation support) */ @@ -59,19 +58,18 @@ void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackTy /* USER CODE BEGIN GET_IDLE_TASK_MEMORY */ static StaticTask_t xIdleTaskTCBBuffer; static StackType_t xIdleStack[configMINIMAL_STACK_SIZE]; - + void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) { *ppxIdleTaskTCBBuffer = &xIdleTaskTCBBuffer; *ppxIdleTaskStackBuffer = &xIdleStack[0]; *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; /* place for user code */ -} +} /* USER CODE END GET_IDLE_TASK_MEMORY */ /* Private application code --------------------------------------------------*/ /* USER CODE BEGIN Application */ - + /* USER CODE END Application */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Src/main.c b/Software/VNA_embedded/Src/main.c index d1e597b..51c7663 100644 --- a/Software/VNA_embedded/Src/main.c +++ b/Software/VNA_embedded/Src/main.c @@ -6,22 +6,19 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ - /* Includes ------------------------------------------------------------------*/ #include "main.h" #include "cmsis_os.h" -#include "usbpd.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ @@ -35,7 +32,6 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN PD */ - /* USER CODE END PD */ /* Private macro -------------------------------------------------------------*/ @@ -132,8 +128,6 @@ int main(void) /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ - /* USBPD initialisation ---------------------------------*/ - MX_USBPD_Init(); /* USER CODE BEGIN RTOS_MUTEX */ /* add mutexes, ... */ @@ -164,7 +158,6 @@ int main(void) osKernelStart(); /* We should never get here as control is now taken by the scheduler */ - /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) @@ -184,12 +177,12 @@ void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; /** Configure the main internal regulator output voltage */ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSI48; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -206,7 +199,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -215,19 +208,7 @@ void SystemClock_Config(void) RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) - { - Error_Handler(); - } - /** Initializes the peripherals clocks - */ - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_I2C2 - |RCC_PERIPHCLK_USB|RCC_PERIPHCLK_ADC12; - PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; - PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1; - PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { Error_Handler(); } @@ -254,7 +235,7 @@ static void MX_ADC1_Init(void) /** Common config */ hadc1.Instance = ADC1; - hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; + hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; hadc1.Init.Resolution = ADC_RESOLUTION_12B; hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; hadc1.Init.GainCompensation = 0; @@ -438,7 +419,6 @@ static void MX_TIM1_Init(void) TIM_ClockConfigTypeDef sClockSourceConfig = {0}; TIM_MasterConfigTypeDef sMasterConfig = {0}; - TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; /* USER CODE BEGIN TIM1_Init 1 */ @@ -466,12 +446,6 @@ static void MX_TIM1_Init(void) { Error_Handler(); } - sBreakDeadTimeConfig.BreakAFMode = TIM_BREAK_AFMODE_INPUT; - sBreakDeadTimeConfig.Break2AFMode = TIM_BREAK_AFMODE_INPUT; - if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) - { - Error_Handler(); - } /* USER CODE BEGIN TIM1_Init 2 */ /* USER CODE END TIM1_Init 2 */ @@ -549,9 +523,26 @@ static void MX_UCPD1_Init(void) /* USER CODE END UCPD1_Init 0 */ + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + /* Peripheral clock enable */ LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_UCPD1); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB); + /**UCPD1 GPIO Configuration + PB4 ------> UCPD1_CC2 + PB6 ------> UCPD1_CC1 + */ + GPIO_InitStruct.Pin = LL_GPIO_PIN_4; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LL_GPIO_PIN_6; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + /* UCPD1 DMA Init */ /* UCPD1_RX Init */ @@ -687,6 +678,7 @@ static void MX_USB_PCD_Init(void) */ static void MX_DMA_Init(void) { + /* DMA controller clock enable */ __HAL_RCC_DMAMUX1_CLK_ENABLE(); __HAL_RCC_DMA1_CLK_ENABLE(); @@ -782,13 +774,12 @@ static void MX_GPIO_Init(void) /* USER CODE BEGIN Header_StartDefaultTask */ /** * @brief Function implementing the defaultTask thread. - * @param argument: Not used + * @param argument: Not used * @retval None */ /* USER CODE END Header_StartDefaultTask */ void StartDefaultTask(void const * argument) { - /* USER CODE BEGIN 5 */ App_Start(); /* Infinite loop */ @@ -828,7 +819,10 @@ void Error_Handler(void) { /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ - + __disable_irq(); + while (1) + { + } /* USER CODE END Error_Handler_Debug */ } @@ -844,9 +838,8 @@ void assert_failed(uint8_t *file, uint32_t line) { /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, - tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ /* USER CODE END 6 */ } #endif /* USE_FULL_ASSERT */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Src/stm32g4xx_hal_msp.c b/Software/VNA_embedded/Src/stm32g4xx_hal_msp.c index de401e9..ae1f1e5 100644 --- a/Software/VNA_embedded/Src/stm32g4xx_hal_msp.c +++ b/Software/VNA_embedded/Src/stm32g4xx_hal_msp.c @@ -1,19 +1,18 @@ /* USER CODE BEGIN Header */ /** ****************************************************************************** - * File Name : stm32g4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization - * and de-Initialization codes. + * @file stm32g4xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -35,7 +34,7 @@ extern DMA_HandleTypeDef hdma_spi1_tx; /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ - + /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ @@ -92,11 +91,21 @@ void HAL_MspInit(void) */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; if(hadc->Instance==ADC1) { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ + /** Initializes the peripherals clocks + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12; + PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + /* Peripheral clock enable */ __HAL_RCC_ADC12_CLK_ENABLE(); /* USER CODE BEGIN ADC1_MspInit 1 */ @@ -137,11 +146,20 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) { GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; if(hi2c->Instance==I2C2) { /* USER CODE BEGIN I2C2_MspInit 0 */ /* USER CODE END I2C2_MspInit 0 */ + /** Initializes the peripherals clocks + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C2; + PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); @@ -457,11 +475,21 @@ void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) void HAL_UART_MspInit(UART_HandleTypeDef* huart) { GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; if(huart->Instance==USART3) { /* USER CODE BEGIN USART3_MspInit 0 */ /* USER CODE END USART3_MspInit 0 */ + /** Initializes the peripherals clocks + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3; + PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); @@ -531,23 +559,20 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) */ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; if(hpcd->Instance==USB) { /* USER CODE BEGIN USB_MspInit 0 */ /* USER CODE END USB_MspInit 0 */ - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USB GPIO Configuration - PA11 ------> USB_DM - PA12 ------> USB_DP - */ - GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + /** Initializes the peripherals clocks + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } /* Peripheral clock enable */ __HAL_RCC_USB_CLK_ENABLE(); @@ -573,13 +598,6 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd) /* USER CODE END USB_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USB_CLK_DISABLE(); - - /**USB GPIO Configuration - PA11 ------> USB_DM - PA12 ------> USB_DP - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); - /* USER CODE BEGIN USB_MspDeInit 1 */ /* USER CODE END USB_MspDeInit 1 */ @@ -591,4 +609,3 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd) /* USER CODE END 1 */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Src/stm32g4xx_hal_timebase_tim.c b/Software/VNA_embedded/Src/stm32g4xx_hal_timebase_tim.c index a2ee498..448c061 100644 --- a/Software/VNA_embedded/Src/stm32g4xx_hal_timebase_tim.c +++ b/Software/VNA_embedded/Src/stm32g4xx_hal_timebase_tim.c @@ -1,18 +1,17 @@ /* USER CODE BEGIN Header */ /** ****************************************************************************** - * @file stm32g4xx_hal_timebase_TIM.c + * @file stm32g4xx_hal_timebase_TIM.c * @brief HAL time base based on the hardware TIM. ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -45,12 +44,7 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) uint32_t uwTimclock = 0; uint32_t uwPrescalerValue = 0; uint32_t pFLatency; - - /*Configure the TIM17 IRQ priority */ - HAL_NVIC_SetPriority(TIM1_TRG_COM_TIM17_IRQn, TickPriority ,0); - - /* Enable the TIM17 global Interrupt */ - HAL_NVIC_EnableIRQ(TIM1_TRG_COM_TIM17_IRQn); + HAL_StatusTypeDef status = HAL_OK; /* Enable TIM17 clock */ __HAL_RCC_TIM17_CLK_ENABLE(); @@ -60,9 +54,8 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) /* Compute TIM17 clock */ uwTimclock = HAL_RCC_GetPCLK2Freq(); - /* Compute the prescaler value to have TIM17 counter clock equal to 1MHz */ - uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1); + uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); /* Initialize TIM17 */ htim17.Instance = TIM17; @@ -73,18 +66,35 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) + ClockDivision = 0 + Counter direction = Up */ - htim17.Init.Period = (1000000 / 1000) - 1; + htim17.Init.Period = (1000000U / 1000U) - 1U; htim17.Init.Prescaler = uwPrescalerValue; htim17.Init.ClockDivision = 0; htim17.Init.CounterMode = TIM_COUNTERMODE_UP; - if(HAL_TIM_Base_Init(&htim17) == HAL_OK) + + status = HAL_TIM_Base_Init(&htim17); + if (status == HAL_OK) { /* Start the TIM time Base generation in interrupt mode */ - return HAL_TIM_Base_Start_IT(&htim17); + status = HAL_TIM_Base_Start_IT(&htim17); + if (status == HAL_OK) + { + /* Enable the TIM17 global Interrupt */ + HAL_NVIC_EnableIRQ(TIM1_TRG_COM_TIM17_IRQn); + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + /* Configure the TIM IRQ priority */ + HAL_NVIC_SetPriority(TIM1_TRG_COM_TIM17_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + status = HAL_ERROR; + } + } } - - /* Return function status */ - return HAL_ERROR; + /* Return function status */ + return status; } /** @@ -111,4 +121,3 @@ void HAL_ResumeTick(void) __HAL_TIM_ENABLE_IT(&htim17, TIM_IT_UPDATE); } -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Src/stm32g4xx_it.c b/Software/VNA_embedded/Src/stm32g4xx_it.c index bcf8bc7..b1e3206 100644 --- a/Software/VNA_embedded/Src/stm32g4xx_it.c +++ b/Software/VNA_embedded/Src/stm32g4xx_it.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -21,7 +20,6 @@ /* Includes ------------------------------------------------------------------*/ #include "main.h" #include "stm32g4xx_it.h" -#include "cmsis_os.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ @@ -33,7 +31,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN PD */ - + /* USER CODE END PD */ /* Private macro -------------------------------------------------------------*/ @@ -78,7 +76,9 @@ void NMI_Handler(void) /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ - + while (1) + { + } /* USER CODE END NonMaskableInt_IRQn 1 */ } @@ -249,4 +249,4 @@ void UCPD1_IRQHandler(void) /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Software/VNA_embedded/Src/syscalls.c b/Software/VNA_embedded/Src/syscalls.c index d457e10..8370509 100644 --- a/Software/VNA_embedded/Src/syscalls.c +++ b/Software/VNA_embedded/Src/syscalls.c @@ -1,204 +1,155 @@ -/** -***************************************************************************** -** -** File : syscalls.c -** -** Abstract : System Workbench Minimal System calls file -** -** For more information about which c-functions -** need which of these lowlevel functions -** please consult the Newlib libc-manual -** -** Environment : System Workbench for MCU -** -** Distribution: The file is distributed “as is,†without any warranty -** of any kind. -** -***************************************************************************** -** -**

© COPYRIGHT(c) 2014 Ac6

-** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** 1. Redistributions of source code must retain the above copyright notice, -** this list of conditions and the following disclaimer. -** 2. Redistributions in binary form must reproduce the above copyright notice, -** this list of conditions and the following disclaimer in the documentation -** and/or other materials provided with the distribution. -** 3. Neither the name of Ac6 nor the names of its contributors -** may be used to endorse or promote products derived from this software -** without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -***************************************************************************** -*/ - -/* Includes */ -#include -#include -#include -#include -#include -#include -#include -#include - - -/* Variables */ -//#undef errno -extern int errno; -extern int __io_putchar(int ch) __attribute__((weak)); -extern int __io_getchar(void) __attribute__((weak)); - -register char * stack_ptr asm("sp"); - -char *__env[1] = { 0 }; -char **environ = __env; - - -/* Functions */ -void initialise_monitor_handles() -{ -} - -int _getpid(void) -{ - return 1; -} - -int _kill(int pid, int sig) -{ - errno = EINVAL; - return -1; -} - -void _exit (int status) -{ - _kill(status, -1); - while (1) {} /* Make sure we hang here */ -} - -__attribute__((weak)) int _read(int file, char *ptr, int len) -{ - int DataIdx; - - for (DataIdx = 0; DataIdx < len; DataIdx++) - { - *ptr++ = __io_getchar(); - } - -return len; -} - -__attribute__((weak)) int _write(int file, char *ptr, int len) -{ - int DataIdx; - - for (DataIdx = 0; DataIdx < len; DataIdx++) - { - __io_putchar(*ptr++); - } - return len; -} - -caddr_t _sbrk(int incr) -{ - extern char end asm("end"); - static char *heap_end; - char *prev_heap_end; - - if (heap_end == 0) - heap_end = &end; - - prev_heap_end = heap_end; - if (heap_end + incr > stack_ptr) - { -// write(1, "Heap and stack collision\n", 25); -// abort(); - errno = ENOMEM; - return (caddr_t) -1; - } - - heap_end += incr; - - return (caddr_t) prev_heap_end; -} - -int _close(int file) -{ - return -1; -} - - -int _fstat(int file, struct stat *st) -{ - st->st_mode = S_IFCHR; - return 0; -} - -int _isatty(int file) -{ - return 1; -} - -int _lseek(int file, int ptr, int dir) -{ - return 0; -} - -int _open(char *path, int flags, ...) -{ - /* Pretend like we always fail */ - return -1; -} - -int _wait(int *status) -{ - errno = ECHILD; - return -1; -} - -int _unlink(char *name) -{ - errno = ENOENT; - return -1; -} - -int _times(struct tms *buf) -{ - return -1; -} - -int _stat(char *file, struct stat *st) -{ - st->st_mode = S_IFCHR; - return 0; -} - -int _link(char *old, char *new) -{ - errno = EMLINK; - return -1; -} - -int _fork(void) -{ - errno = EAGAIN; - return -1; -} - -int _execve(char *name, char **argv, char **env) -{ - errno = ENOMEM; - return -1; -} +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeIDE + * @brief STM32CubeIDE Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib libc-manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + +return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + return 0; +} + +int _open(char *path, int flags, ...) +{ + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + return -1; +} + +int _stat(char *file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + errno = ENOMEM; + return -1; +} diff --git a/Software/VNA_embedded/Src/sysmem.c b/Software/VNA_embedded/Src/sysmem.c new file mode 100644 index 0000000..4353a47 --- /dev/null +++ b/Software/VNA_embedded/Src/sysmem.c @@ -0,0 +1,79 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeIDE + * @brief STM32CubeIDE System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the newlib libc manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} diff --git a/Software/VNA_embedded/Src/system_stm32g4xx.c b/Software/VNA_embedded/Src/system_stm32g4xx.c index 723411b..d20700b 100644 --- a/Software/VNA_embedded/Src/system_stm32g4xx.c +++ b/Software/VNA_embedded/Src/system_stm32g4xx.c @@ -53,13 +53,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -79,7 +78,7 @@ #include "stm32g4xx.h" #if !defined (HSE_VALUE) - #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSI_VALUE) @@ -103,11 +102,29 @@ */ /************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00UL /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ /******************************************************************************/ /** * @} @@ -167,11 +184,9 @@ void SystemInit(void) #endif /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ } /** @@ -200,7 +215,7 @@ void SystemInit(void) * in voltage and temperature. * * (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * 24 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. * @@ -267,5 +282,4 @@ void SystemCoreClockUpdate(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Src/usbpd.c b/Software/VNA_embedded/Src/usbpd.c deleted file mode 100644 index f577815..0000000 --- a/Software/VNA_embedded/Src/usbpd.c +++ /dev/null @@ -1,70 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file usbpd.c - * @author MCD Application Team - * @brief This file contains the device define. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbpd.h" - -/* USER CODE BEGIN 0 */ -/* USER CODE END 0 */ - -/* USER CODE BEGIN 1 */ -/* USER CODE END 1 */ - -/* Global variables ---------------------------------------------------------*/ - -/* USER CODE BEGIN 2 */ -/* USER CODE END 2 */ - -/* USBPD init function */ -void MX_USBPD_Init(void) -{ - - /* Global Init of USBPD HW */ - USBPD_HW_IF_GlobalHwInit(); - - /* Initialize the Device Policy Manager */ - if(USBPD_OK != USBPD_DPM_InitCore()) - { - while(1); - } - - /* Initialise the DPM application */ - if (USBPD_OK != USBPD_DPM_UserInit()) - { - while(1); - } - - /* USER CODE BEGIN 3 */ - /* USER CODE END 3 */ - -} - -/* USER CODE BEGIN 4 */ -/* USER CODE END 4 */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Src/usbpd_dpm_core.c b/Software/VNA_embedded/Src/usbpd_dpm_core.c deleted file mode 100644 index 990ae22..0000000 --- a/Software/VNA_embedded/Src/usbpd_dpm_core.c +++ /dev/null @@ -1,350 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file usbpd_dpm_core.c - * @author MCD Application Team - * @brief USBPD dpm core file - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -#define __USBPD_DPM_CORE_C - -/* Includes ------------------------------------------------------------------*/ -#include "usbpd_core.h" -#include "usbpd_trace.h" -#include "usbpd_dpm_core.h" -#include "usbpd_dpm_user.h" -#include "usbpd_dpm_conf.h" -#include "cmsis_os.h" - -/* Private enum */ -enum -{ - USBPD_THREAD_PORT_0 = USBPD_PORT_0, -#if USBPD_PORT_COUNT == 2 - USBPD_THREAD_PORT_1 = USBPD_PORT_1, -#endif - USBPD_THREAD_CAD -}; - -/* Generic STM32 prototypes */ -extern uint32_t HAL_GetTick(void); - -/* Private function prototypes -----------------------------------------------*/ -void USBPD_DPM_CADCallback(uint8_t PortNum, USBPD_CAD_EVENT State, CCxPin_TypeDef Cc); -void USBPD_PE_Task(void const *argument); -void USBPD_CAD_Task(void const *argument); - -static void USBPD_PE_TaskWakeUp(uint8_t PortNum); -static void USBPD_DPM_CADTaskWakeUp(void); - -/* Private typedef -----------------------------------------------------------*/ -osThreadDef(PE_0, USBPD_PE_Task, osPriorityHigh, 0, 200); -osThreadDef(PE_1, USBPD_PE_Task, osPriorityHigh, 0, 200); - -/* Private define ------------------------------------------------------------*/ -#define MAX_TREAD_POWER (USBPD_PORT_COUNT + 1) - -#define OSTHREAD_PE(__VAL__) __VAL__==USBPD_PORT_0?osThread(PE_0):osThread(PE_1) - -/* Private macro -------------------------------------------------------------*/ -#define CHECK_PE_FUNCTION_CALL(_function_) if(USBPD_OK != _function_) {return USBPD_ERROR;} -#define CHECK_CAD_FUNCTION_CALL(_function_) if(USBPD_CAD_OK != _function_) {return USBPD_ERROR;} - -#if defined(_DEBUG_TRACE) -#define DPM_CORE_DEBUG_TRACE(_PORTNUM_, __MESSAGE__) USBPD_TRACE_Add(USBPD_TRACE_DEBUG, _PORTNUM_, 0u, (uint8_t *)(__MESSAGE__), sizeof(__MESSAGE__) - 1u); -#else -#define DPM_CORE_DEBUG_TRACE(_PORTNUM_, __MESSAGE__) -#endif /* _DEBUG_TRACE */ - -/* Private variables ---------------------------------------------------------*/ -static uint32_t DPM_Sleep_time[MAX_TREAD_POWER]; -static osThreadId DPM_Thread_Table[MAX_TREAD_POWER]; -osMessageQDef(queuePE, 2, uint16_t); -osMessageQDef(queueCAD, 1, uint16_t); -static osMessageQId PEQueueId[USBPD_PORT_COUNT], CADQueueId; - -USBPD_ParamsTypeDef DPM_Params[USBPD_PORT_COUNT]; - -/* Private functions ---------------------------------------------------------*/ -static void DPM_ManageAttachedState(uint8_t PortNum, USBPD_CAD_EVENT State, CCxPin_TypeDef Cc); - -/** - * @brief Initialize the core stack (port power role, PWR_IF, CAD and PE Init procedures) - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_DPM_InitCore(void) -{ -/* variable to get dynamique memory allocated by usbpd stack */ - uint32_t stack_dynamemsize; - -static const USBPD_PE_Callbacks dpmCallbacks = -{ - NULL, - NULL, - USBPD_DPM_EvaluatePowerRoleSwap, - USBPD_DPM_Notification, - NULL, - USBPD_DPM_GetDataInfo, - USBPD_DPM_SetDataInfo, - NULL, - USBPD_DPM_SNK_EvaluateCapabilities, - NULL, - USBPD_PE_TaskWakeUp, - NULL, - NULL, - NULL, - USBPD_DPM_EvaluateDataRoleSwap, - USBPD_DPM_IsPowerReady -}; - - static const USBPD_CAD_Callbacks CAD_cbs = { USBPD_DPM_CADCallback, USBPD_DPM_CADTaskWakeUp }; - - /* Check the lib selected */ - if( USBPD_TRUE != USBPD_PE_CheckLIB(_LIB_ID)) - { - return USBPD_ERROR; - } - - /* to get how much memory are dynamically allocated by the stack - the memory return is corresponding to 2 ports so if the application - managed only one port divide the value return by 2 */ - stack_dynamemsize = USBPD_PE_GetMemoryConsumption(); - - /* done to avoid warning */ - stack_dynamemsize--; - - /* Variable to be sure that DPM is correctly initialized */ - DPM_Params[USBPD_PORT_0].DPM_Initialized = USBPD_FALSE; -#if USBPD_PORT_COUNT == 2 - DPM_Params[USBPD_PORT_1].DPM_Initialized = USBPD_FALSE; -#endif /* USBPD_PORT_COUNT == 2 */ - - /* check the stack settings */ - DPM_Params[USBPD_PORT_0].PE_SpecRevision = DPM_Settings[USBPD_PORT_0].PE_SpecRevision; - DPM_Params[USBPD_PORT_0].PE_PowerRole = DPM_Settings[USBPD_PORT_0].PE_DefaultRole; - DPM_Params[USBPD_PORT_0].PE_SwapOngoing = USBPD_FALSE; - DPM_Params[USBPD_PORT_0].ActiveCCIs = CCNONE; - DPM_Params[USBPD_PORT_0].VconnCCIs = CCNONE; - DPM_Params[USBPD_PORT_0].VconnStatus = USBPD_FALSE; -#if USBPD_PORT_COUNT == 2 - DPM_Params[USBPD_PORT_1].PE_SpecRevision = DPM_Settings[USBPD_PORT_1].PE_SpecRevision; - DPM_Params[USBPD_PORT_1].PE_PowerRole = DPM_Settings[USBPD_PORT_1].PE_DefaultRole; - DPM_Params[USBPD_PORT_1].PE_SwapOngoing = USBPD_FALSE; - DPM_Params[USBPD_PORT_1].ActiveCCIs = CCNONE; - DPM_Params[USBPD_PORT_1].VconnCCIs = CCNONE; - DPM_Params[USBPD_PORT_1].VconnStatus = USBPD_FALSE; -#endif /* USBPD_PORT_COUNT == 2 */ - - /* CAD SET UP : Port 0 */ - CHECK_CAD_FUNCTION_CALL(USBPD_CAD_Init(USBPD_PORT_0, (USBPD_CAD_Callbacks *)&CAD_cbs, (USBPD_SettingsTypeDef *)&DPM_Settings[USBPD_PORT_0], &DPM_Params[USBPD_PORT_0])); -#if USBPD_PORT_COUNT == 2 - CHECK_CAD_FUNCTION_CALL(USBPD_CAD_Init(USBPD_PORT_1, (USBPD_CAD_Callbacks *)&CAD_cbs, (USBPD_SettingsTypeDef *)&DPM_Settings[USBPD_PORT_1], &DPM_Params[USBPD_PORT_1])); -#endif /* USBPD_PORT_COUNT == 2 */ - - /* PE SET UP : Port 0 */ - CHECK_PE_FUNCTION_CALL(USBPD_PE_Init(USBPD_PORT_0, (USBPD_SettingsTypeDef *)&DPM_Settings[USBPD_PORT_0], &DPM_Params[USBPD_PORT_0], &dpmCallbacks)); -#if USBPD_PORT_COUNT == 2 - CHECK_PE_FUNCTION_CALL(USBPD_PE_Init(USBPD_PORT_1, (USBPD_SettingsTypeDef *)&DPM_Settings[USBPD_PORT_1], &DPM_Params[USBPD_PORT_1], &dpmCallbacks)); -#endif /* USBPD_PORT_COUNT == 2 */ - - /* DPM is correctly initialized */ - DPM_Params[USBPD_PORT_0].DPM_Initialized = USBPD_TRUE; -#if USBPD_PORT_COUNT == 2 - DPM_Params[USBPD_PORT_1].DPM_Initialized = USBPD_TRUE; -#endif /* USBPD_PORT_COUNT == 2 */ - - /* Enable CAD on Port 0 */ - USBPD_CAD_PortEnable(USBPD_PORT_0, USBPD_CAD_ENABLE); -#if USBPD_PORT_COUNT == 2 - USBPD_CAD_PortEnable(USBPD_PORT_1, USBPD_CAD_ENABLE); -#endif /* USBPD_PORT_COUNT == 2 */ - - return USBPD_OK; -} - -/** - * @brief Initialize the OS parts (task, queue,... ) - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_DPM_InitOS(void) -{ - osThreadDef(CAD, USBPD_CAD_Task, osPriorityRealtime, 0, 300); - if((DPM_Thread_Table[USBPD_THREAD_CAD] = osThreadCreate(osThread(CAD), NULL)) == NULL) - { - return USBPD_ERROR; - } - CADQueueId = osMessageCreate(osMessageQ(queueCAD), NULL); - - /* Create the queue corresponding to PE task */ - PEQueueId[0] = osMessageCreate(osMessageQ(queuePE), NULL); -#if USBPD_PORT_COUNT == 2 - PEQueueId[1] = osMessageCreate(osMessageQ(queuePE), NULL); -#endif /* USBPD_PORT_COUNT == 2 */ - - /* PE task to be created on attachment */ - DPM_Thread_Table[USBPD_THREAD_PORT_0] = NULL; -#if USBPD_PORT_COUNT == 2 - DPM_Thread_Table[USBPD_THREAD_PORT_1] = NULL; -#endif /* USBPD_PORT_COUNT == 2 */ - - return USBPD_OK; -} - -/** - * @brief Initialize the OS parts (port power role, PWR_IF, CAD and PE Init procedures) - * @retval None - */ -void USBPD_DPM_Run(void) -{ - osKernelStart(); -} - -/** - * @brief Initialize DPM (port power role, PWR_IF, CAD and PE Init procedures) - * @retval USBPD status - */ -void USBPD_DPM_TimerCounter(void) -{ - /* Call PE/PRL timers functions only if DPM is initialized */ - if (USBPD_TRUE == DPM_Params[USBPD_PORT_0].DPM_Initialized) - { - USBPD_DPM_UserTimerCounter(USBPD_PORT_0); - USBPD_PE_TimerCounter(USBPD_PORT_0); - USBPD_PRL_TimerCounter(USBPD_PORT_0); - } -#if USBPD_PORT_COUNT==2 - if (USBPD_TRUE == DPM_Params[USBPD_PORT_1].DPM_Initialized) - { - USBPD_DPM_UserTimerCounter(USBPD_PORT_1); - USBPD_PE_TimerCounter(USBPD_PORT_1); - USBPD_PRL_TimerCounter(USBPD_PORT_1); - } -#endif /* USBPD_PORT_COUNT == 2 */ - -} - -/** - * @brief WakeUp PE task - * @param PortNum port number - * @retval None - */ -static void USBPD_PE_TaskWakeUp(uint8_t PortNum) -{ - osMessagePut(PEQueueId[PortNum], 0xFFFF, 0); -} - -/** - * @brief WakeUp CAD task - * @retval None - */ -static void USBPD_DPM_CADTaskWakeUp(void) -{ - osMessagePut(CADQueueId, 0xFFFF, 0); -} - -/** - * @brief Main task for PE layer - * @param argument Not used - * @retval None - */ -void USBPD_PE_Task(void const *argument) -{ - uint8_t _port = (uint32_t)argument; - - for(;;) - { - DPM_Sleep_time[_port] = - USBPD_PE_StateMachine_SNK(_port); - osMessageGet(PEQueueId[_port], DPM_Sleep_time[_port]); - - } -} - -/** - * @brief Main task for CAD layer - * @param argument Not used - * @retval None - */ -void USBPD_CAD_Task(void const *argument) -{ - for(;;) - { - DPM_Sleep_time[USBPD_THREAD_CAD] = USBPD_CAD_Process(); - osMessageGet(CADQueueId, DPM_Sleep_time[USBPD_THREAD_CAD]); - } -} - -/** - * @brief CallBack reporting events on a specified port from CAD layer. - * @param PortNum The handle of the port - * @param State CAD state - * @param Cc The Communication Channel for the USBPD communication - * @retval None - */ -void USBPD_DPM_CADCallback(uint8_t PortNum, USBPD_CAD_EVENT State, CCxPin_TypeDef Cc) -{ - - switch(State) - { - case USBPD_CAD_EVENT_ATTEMC : - { - DPM_ManageAttachedState(PortNum, State, Cc); - break; - } - case USBPD_CAD_EVENT_ATTACHED : - DPM_ManageAttachedState(PortNum, State, Cc); - break; - case USBPD_CAD_EVENT_DETACHED : - case USBPD_CAD_EVENT_EMC : - { - /* The ufp is detached */ - (void)USBPD_PE_IsCableConnected(PortNum, 0); - /* Terminate PE task */ - if (DPM_Thread_Table[PortNum] != NULL) - { - osThreadTerminate(DPM_Thread_Table[PortNum]); - DPM_Thread_Table[PortNum] = NULL; - } - USBPD_DPM_UserCableDetection(PortNum, State); - DPM_Params[PortNum].ActiveCCIs = CCNONE; - DPM_Params[PortNum].PE_Power = USBPD_POWER_NO; - break; - } - default : - /* nothing to do */ - break; - } -} - -static void DPM_ManageAttachedState(uint8_t PortNum, USBPD_CAD_EVENT State, CCxPin_TypeDef Cc) -{ - DPM_Params[PortNum].ActiveCCIs = Cc; - (void)USBPD_PE_IsCableConnected(PortNum, 1); - - USBPD_DPM_UserCableDetection(PortNum, State); - - /* Create PE task */ - if (DPM_Thread_Table[PortNum] == NULL) - { - DPM_Thread_Table[PortNum] = osThreadCreate(OSTHREAD_PE(PortNum), (void *)((uint32_t)PortNum)); - if (DPM_Thread_Table[PortNum] == NULL) - { - /* should not occurr. May be an issue with FreeRTOS heap size too small */ - while(1); - } - } -} -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Src/usbpd_dpm_user.c b/Software/VNA_embedded/Src/usbpd_dpm_user.c deleted file mode 100644 index 09f6cd9..0000000 --- a/Software/VNA_embedded/Src/usbpd_dpm_user.c +++ /dev/null @@ -1,405 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file usbpd_dpm_user.c - * @author MCD Application Team - * @brief USBPD DPM user code - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -#define USBPD_DPM_USER_C -/* Includes ------------------------------------------------------------------*/ -#include "usbpd_core.h" -#include "usbpd_pdo_defs.h" -#include "usbpd_dpm_core.h" -#include "usbpd_dpm_conf.h" -#include "usbpd_dpm_user.h" -#include "usbpd_vdm_user.h" -#include "usbpd_trace.h" -#include "usbpd_pwr_if.h" -#include "string.h" -#include "cmsis_os.h" -#include "usbpd_pwr_user.h" - -/** @addtogroup STM32_USBPD_APPLICATION - * @{ - */ - -/** @addtogroup STM32_USBPD_APPLICATION_DPM_USER - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN Private_Typedef */ - -/* USER CODE END Private_Typedef */ - -/* Private define ------------------------------------------------------------*/ -/** @defgroup USBPD_USER_PRIVATE_DEFINES USBPD USER Private Defines - * @{ - */ -/* USER CODE BEGIN Private_Define */ - -/* USER CODE END Private_Define */ -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup USBPD_USER_PRIVATE_MACROS USBPD USER Private Macros - * @{ - */ -/* USER CODE BEGIN Private_Macro */ - -/* USER CODE END Private_Macro */ -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup USBPD_USER_PRIVATE_VARIABLES USBPD USER Private Variables - * @{ - */ -/* USER CODE BEGIN Private_Variables */ - -/* USER CODE END Private_Variables */ -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup USBPD_USER_PRIVATE_FUNCTIONS USBPD USER Private Functions - * @{ - */ -/* USER CODE BEGIN USBPD_USER_PRIVATE_FUNCTIONS_Prototypes */ - -/* USER CODE END USBPD_USER_PRIVATE_FUNCTIONS_Prototypes */ -/** - * @} - */ - -/* Exported functions ------- ------------------------------------------------*/ -/** @defgroup USBPD_USER_EXPORTED_FUNCTIONS USBPD USER Exported Functions - * @{ - */ -/* USER CODE BEGIN USBPD_USER_EXPORTED_FUNCTIONS */ - -/* USER CODE END USBPD_USER_EXPORTED_FUNCTIONS */ - -/** @defgroup USBPD_USER_EXPORTED_FUNCTIONS_GROUP1 USBPD USER Exported Functions called by DPM CORE - * @{ - */ -/* USER CODE BEGIN USBPD_USER_EXPORTED_FUNCTIONS_GROUP1 */ - -/* USER CODE END USBPD_USER_EXPORTED_FUNCTIONS_GROUP1 */ - -/** - * @brief Initialize DPM (port power role, PWR_IF, CAD and PE Init procedures) - * @retval USBPD Status - */ -USBPD_StatusTypeDef USBPD_DPM_UserInit(void) -{ -/* USER CODE BEGIN USBPD_DPM_UserInit */ - return USBPD_OK; -/* USER CODE END USBPD_DPM_UserInit */ -} - -/** - * @brief User delay implementation which is OS dependant - * @param Time time in ms - * @retval None - */ -void USBPD_DPM_WaitForTime(uint32_t Time) -{ -/* USER CODE BEGIN USBPD_DPM_WaitForTime */ -#ifdef _RTOS - osDelay(Time); -#else - HAL_Delay(Time); -#endif -/* USER CODE END USBPD_DPM_WaitForTime */ -} - -/** - * @brief User processing time, it is recommended to avoid blocking task for long time - * @param argument DPM User event - * @retval None - */ -void USBPD_DPM_UserExecute(void const *argument) -{ -/* USER CODE BEGIN USBPD_DPM_UserExecute */ - -/* USER CODE END USBPD_DPM_UserExecute */ -} - -/** - * @brief UserCableDetection reporting events on a specified port from CAD layer. - * @param PortNum The handle of the port - * @param State CAD state - * @retval None - */ -void USBPD_DPM_UserCableDetection(uint8_t PortNum, USBPD_CAD_EVENT State) -{ -/* USER CODE BEGIN USBPD_DPM_UserCableDetection */ - -/* USER CODE END USBPD_DPM_UserCableDetection */ -} - -/** - * @brief function used to manage user timer. - * @param PortNum Port number - * @retval None - */ -void USBPD_DPM_UserTimerCounter(uint8_t PortNum) -{ -/* USER CODE BEGIN USBPD_DPM_UserTimerCounter */ - -/* USER CODE END USBPD_DPM_UserTimerCounter */ -} - -/** - * @} - */ - -/** @defgroup USBPD_USER_EXPORTED_FUNCTIONS_GROUP2 USBPD USER Exported Callbacks functions called by PE - * @{ - */ - -/** - * @brief Callback function called by PE layer when HardReset message received from PRL - * @param PortNum The current port number - * @param CurrentRole the current role - * @param Status status on hard reset event - * @retval None - */ -void USBPD_DPM_HardReset(uint8_t PortNum, USBPD_PortPowerRole_TypeDef CurrentRole, USBPD_HR_Status_TypeDef Status) -{ -/* USER CODE BEGIN USBPD_DPM_HardReset */ - -/* USER CODE END USBPD_DPM_HardReset */ -} - -/** - * @brief Request the DPM to setup the new power level. - * @param PortNum The current port number - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_DPM_SetupNewPower(uint8_t PortNum) -{ -/* USER CODE BEGIN USBPD_DPM_SetupNewPower */ - return USBPD_PWR_IF_SetProfile(PortNum); -/* USER CODE END USBPD_DPM_SetupNewPower */ -} - -/** - * @brief Evaluate the swap request from PE. - * @param PortNum The current port number - * @retval USBPD_ACCEPT, USBPD_WAIT, USBPD_REJECT - */ -USBPD_StatusTypeDef USBPD_DPM_EvaluatePowerRoleSwap(uint8_t PortNum) -{ -/* USER CODE BEGIN USBPD_DPM_EvaluatePowerRoleSwap */ - return USBPD_REJECT; -/* USER CODE END USBPD_DPM_EvaluatePowerRoleSwap */ -} - -/** - * @brief Callback function called by PE to inform DPM about PE event. - * @param PortNum The current port number - * @param EventVal @ref USBPD_NotifyEventValue_TypeDef - * @retval None - */ -void USBPD_DPM_Notification(uint8_t PortNum, USBPD_NotifyEventValue_TypeDef EventVal) -{ -/* USER CODE BEGIN USBPD_DPM_Notification */ - -/* USER CODE END USBPD_DPM_Notification */ -} - -/** - * @brief DPM callback to allow PE to retrieve information from DPM/PWR_IF. - * @param PortNum Port number - * @param DataId Type of data to be updated in DPM based on @ref USBPD_CORE_DataInfoType_TypeDef - * @param Ptr Pointer on address where DPM data should be written (u8 pointer) - * @param Size Pointer on nb of u8 written by DPM - * @retval None - */ -void USBPD_DPM_GetDataInfo(uint8_t PortNum, USBPD_CORE_DataInfoType_TypeDef DataId, uint8_t *Ptr, uint32_t *Size) -{ -/* USER CODE BEGIN USBPD_DPM_GetDataInfo */ - -/* USER CODE END USBPD_DPM_GetDataInfo */ -} - -/** - * @brief DPM callback to allow PE to update information in DPM/PWR_IF. - * @param PortNum Port number - * @param DataId Type of data to be updated in DPM based on @ref USBPD_CORE_DataInfoType_TypeDef - * @param Ptr Pointer on the data - * @param Size Nb of bytes to be updated in DPM - * @retval None - */ -void USBPD_DPM_SetDataInfo(uint8_t PortNum, USBPD_CORE_DataInfoType_TypeDef DataId, uint8_t *Ptr, uint32_t Size) -{ -/* USER CODE BEGIN USBPD_DPM_SetDataInfo */ - -/* USER CODE END USBPD_DPM_SetDataInfo */ -} - -/** - * @brief Evaluate received Request Message from Sink port - * @param PortNum Port number - * @param PtrPowerObject Pointer on the power data object - * @retval USBPD status : USBPD_ACCEPT, USBPD_REJECT, USBPD_WAIT, USBPD_GOTOMIN - */ -USBPD_StatusTypeDef USBPD_DPM_EvaluateRequest(uint8_t PortNum, USBPD_CORE_PDO_Type_TypeDef *PtrPowerObject) -{ -/* USER CODE BEGIN USBPD_DPM_EvaluateRequest */ - return USBPD_REJECT; -/* USER CODE END USBPD_DPM_EvaluateRequest */ -} - -/** - * @brief Evaluate received Capabilities Message from Source port and prepare the request message - * @param PortNum Port number - * @param PtrRequestData Pointer on selected request data object - * @param PtrPowerObjectType Pointer on the power data object - * @retval None - */ -void USBPD_DPM_SNK_EvaluateCapabilities(uint8_t PortNum, uint32_t *PtrRequestData, USBPD_CORE_PDO_Type_TypeDef *PtrPowerObjectType) -{ -/* USER CODE BEGIN USBPD_DPM_SNK_EvaluateCapabilities */ - -/* USER CODE END USBPD_DPM_SNK_EvaluateCapabilities */ -} - -/** - * @brief Power role swap status update - * @param PortNum Port number - * @param CurrentRole the current role - * @param Status status on power role swap event - */ -void USBPD_DPM_PowerRoleSwap(uint8_t PortNum, USBPD_PortPowerRole_TypeDef CurrentRole, USBPD_PRS_Status_TypeDef Status) -{ -/* USER CODE BEGIN USBPD_DPM_PowerRoleSwap */ - -/* USER CODE END USBPD_DPM_PowerRoleSwap */ -} - -/** - * @brief Callback to be used by PE to evaluate a Vconn swap - * @param PortNum Port number - * @retval USBPD_ACCEPT, USBPD_REJECT, USBPD_WAIT - */ -USBPD_StatusTypeDef USBPD_DPM_EvaluateVconnSwap(uint8_t PortNum) -{ -/* USER CODE BEGIN USBPD_DPM_EvaluateVconnSwap */ - return USBPD_REJECT; -/* USER CODE END USBPD_DPM_EvaluateVconnSwap */ -} - -/** - * @brief Callback to be used by PE to manage VConn - * @param PortNum Port number - * @param State Enable or Disable VConn on CC lines - * @retval USBPD_ACCEPT, USBPD_REJECT - */ -USBPD_StatusTypeDef USBPD_DPM_PE_VconnPwr(uint8_t PortNum, USBPD_FunctionalState State) -{ -/* USER CODE BEGIN USBPD_DPM_PE_VconnPwr */ - return USBPD_ERROR; -/* USER CODE END USBPD_DPM_PE_VconnPwr */ -} - -/** - * @brief DPM callback to allow PE to forward extended message information. - * @param PortNum Port number - * @param MsgType Type of message to be handled in DPM - * This parameter can be one of the following values: - * @arg @ref USBPD_EXT_SECURITY_REQUEST Security Request extended message - * @arg @ref USBPD_EXT_SECURITY_RESPONSE Security Response extended message - * @param ptrData Pointer on address Extended Message data could be read (u8 pointer) - * @param DataSize Nb of u8 that compose Extended message - * @retval None - */ -void USBPD_DPM_ExtendedMessageReceived(uint8_t PortNum, USBPD_ExtendedMsg_TypeDef MsgType, uint8_t *ptrData, uint16_t DataSize) -{ -/* USER CODE BEGIN USBPD_DPM_ExtendedMessageReceived */ - -/* USER CODE END USBPD_DPM_ExtendedMessageReceived */ -} - -/** - * @brief DPM callback used to know user choice about Data Role Swap. - * @param PortNum Port number - * @retval USBPD_REJECT, UBPD_ACCEPT - */ -USBPD_StatusTypeDef USBPD_DPM_EvaluateDataRoleSwap(uint8_t PortNum) -{ -/* USER CODE BEGIN USBPD_DPM_EvaluateDataRoleSwap */ - return USBPD_REJECT; -/* USER CODE END USBPD_DPM_EvaluateDataRoleSwap */ -} - -/** - * @brief Callback to be used by PE to check is VBUS is ready or present - * @param PortNum Port number - * @param Vsafe Vsafe status based on @ref USBPD_VSAFE_StatusTypeDef - * @retval USBPD_DISABLE or USBPD_ENABLE - */ -USBPD_FunctionalState USBPD_DPM_IsPowerReady(uint8_t PortNum, USBPD_VSAFE_StatusTypeDef Vsafe) -{ -/* USER CODE BEGIN USBPD_DPM_IsPowerReady */ - return ((USBPD_OK == USBPD_PWR_IF_SupplyReady(PortNum, Vsafe)) ? USBPD_ENABLE : USBPD_DISABLE); -/* USER CODE END USBPD_DPM_IsPowerReady */ -} - -/** - * @} - */ - -/** @defgroup USBPD_USER_EXPORTED_FUNCTIONS_GROUP3 USBPD USER Functions PD messages requests - * @{ - */ - -/** - * @} - */ - -/** @addtogroup USBPD_USER_PRIVATE_FUNCTIONS - * @{ - */ - -/* USER CODE BEGIN USBPD_USER_PRIVATE_FUNCTIONS */ - -/* USER CODE END USBPD_USER_PRIVATE_FUNCTIONS */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Src/usbpd_pwr_if.c b/Software/VNA_embedded/Src/usbpd_pwr_if.c deleted file mode 100644 index 32f510a..0000000 --- a/Software/VNA_embedded/Src/usbpd_pwr_if.c +++ /dev/null @@ -1,341 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file usbpd_pwr_if.c - * @author MCD Application Team - * @brief This file contains power interface control functions. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -#define __USBPD_PWR_IF_C - -/* Includes ------------------------------------------------------------------*/ -#include "usbpd_pwr_if.h" -#include "usbpd_hw_if.h" -#include "usbpd_pwr_if.h" -#include "usbpd_dpm_core.h" -#include "usbpd_dpm_conf.h" -#include "usbpd_pdo_defs.h" -#include "usbpd_core.h" -#include "usbpd_trace.h" - -/* USER CODE BEGIN Include */ - -/* USER CODE END Include */ - -/** @addtogroup STM32_USBPD_APPLICATION - * @{ - */ - -/** @addtogroup STM32_USBPD_APPLICATION_POWER_IF - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN Private_Typedef */ - -/* USER CODE END Private_Typedef */ - -/* Private define ------------------------------------------------------------*/ -/** @addtogroup STM32_USBPD_APPLICATION_POWER_IF_Private_Defines - * @{ - */ -/* USER CODE BEGIN Private_Define */ - -/* USER CODE END Private_Define */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup STM32_USBPD_APPLICATION_POWER_IF_Private_Macros - * @{ - */ -/* USER CODE BEGIN Private_Macro */ - -/* USER CODE END Private_Macro */ -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @addtogroup STM32_USBPD_APPLICATION_POWER_IF_Private_Variables - * @{ - */ -/* USER CODE BEGIN Private_Variables */ - -/* USER CODE END Private_Variables */ - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup STM32_USBPD_APPLICATION_POWER_IF_Private_Functions - * @{ - */ - -/* USER CODE BEGIN USBPD_USER_PRIVATE_FUNCTIONS_Prototypes */ - -/* Functions to initialize Source PDOs */ -uint32_t _PWR_SRCFixedPDO(float _C_, float _V_, - USBPD_CORE_PDO_PeakCurr_TypeDef _PK_, - USBPD_CORE_PDO_DRDataSupport_TypeDef DRDSupport, - USBPD_CORE_PDO_USBCommCapable_TypeDef UsbCommCapable, - USBPD_CORE_PDO_ExtPowered_TypeDef ExtPower, - USBPD_CORE_PDO_USBSuspendSupport_TypeDef UsbSuspendSupport, - USBPD_CORE_PDO_DRPowerSupport_TypeDef DRPSupport); - -uint32_t _PWR_SRCVariablePDO(float _MAXV_, float _MINV_, float _C_); - -uint32_t _PWR_SRCBatteryPDO(float _MAXV_,float _MINV_,float _PWR_); -/* Functions to initialize Sink PDOs */ - -uint32_t _PWR_SNKFixedPDO(float _C_, float _V_, - USBPD_CORE_PDO_DRDataSupport_TypeDef DRDSupport, - USBPD_CORE_PDO_USBCommCapable_TypeDef UsbCommCapable, - USBPD_CORE_PDO_ExtPowered_TypeDef ExtPower, - USBPD_CORE_PDO_HigherCapability_TypeDef HigherCapab, - USBPD_CORE_PDO_DRPowerSupport_TypeDef DRPSupport); - -uint32_t _PWR_SNKVariablePDO(float _MAXV_,float _MINV_,float _C_); - -uint32_t _PWR_SNKBatteryPDO(float _MAXV_,float _MINV_,float _PWR_); - -/* USER CODE END USBPD_USER_PRIVATE_FUNCTIONS_Prototypes */ - -/** - * @} - */ - -/** @addtogroup STM32_USBPD_APPLICATION_POWER_IF_Exported_Functions - * @{ - */ - -/** - * @brief Initialize structures and variables related to power board profiles - * used by Sink and Source, for all available ports. - * @retval USBPD status -*/ -USBPD_StatusTypeDef USBPD_PWR_IF_Init(void) -{ -/* USER CODE BEGIN USBPD_PWR_IF_Init */ - return USBPD_ERROR; -/* USER CODE END USBPD_PWR_IF_Init */ -} - -/** - * @brief Sets the required power profile, now it works only with Fixed ones - * @param PortNum Port number - * @retval USBPD status -*/ -USBPD_StatusTypeDef USBPD_PWR_IF_SetProfile(uint8_t PortNum) -{ -/* USER CODE BEGIN USBPD_PWR_IF_SetProfile */ - return USBPD_ERROR; -/* USER CODE END USBPD_PWR_IF_SetProfile */ -} - -/** - * @brief Resets the Power Board - * @retval USBPD status -*/ -USBPD_StatusTypeDef USBPD_PWR_IF_PowerResetGlobal(void) -{ -/* USER CODE BEGIN USBPD_PWR_IF_PowerResetGlobal */ - return USBPD_ERROR; -/* USER CODE END USBPD_PWR_IF_PowerResetGlobal */ -} - -/** - * @brief Resets the Power on a specified port - * @param PortNum Port number - * @retval USBPD status -*/ -USBPD_StatusTypeDef USBPD_PWR_IF_PowerReset(uint8_t PortNum) -{ -/* USER CODE BEGIN USBPD_PWR_IF_PowerReset */ - return USBPD_ERROR; -/* USER CODE END USBPD_PWR_IF_PowerReset */ -} - -/** - * @brief Checks if the power on a specified port is ready - * @param PortNum Port number - * @param Vsafe Vsafe status based on @ref USBPD_VSAFE_StatusTypeDef - * @retval USBPD status -*/ -USBPD_StatusTypeDef USBPD_PWR_IF_SupplyReady(uint8_t PortNum, USBPD_VSAFE_StatusTypeDef Vsafe) -{ -/* USER CODE BEGIN USBPD_PWR_IF_SupplyReady */ - return USBPD_ERROR; -/* USER CODE END USBPD_PWR_IF_SupplyReady */ -} - -/** - * @brief Enables VBUS power on a specified port - * @param PortNum Port number - * @retval USBPD status -*/ -USBPD_StatusTypeDef USBPD_PWR_IF_VBUSEnable(uint8_t PortNum) -{ -/* USER CODE BEGIN USBPD_PWR_IF_VBUSEnable */ - return USBPD_ERROR; -/* USER CODE END USBPD_PWR_IF_VBUSEnable */ -} - -/** - * @brief Disbale VBUS/VCONN the power on a specified port - * @param PortNum Port number - * @retval USBPD status -*/ -USBPD_StatusTypeDef USBPD_PWR_IF_VBUSDisable(uint8_t PortNum) -{ -/* USER CODE BEGIN USBPD_PWR_IF_VBUSDisable */ - return USBPD_ERROR; -/* USER CODE END USBPD_PWR_IF_VBUSDisable */ -} - -/** - * @brief Disable the SNK to stop current consumption - * @param PortNum Port number - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_PWR_IF_SNKDisable(uint8_t PortNum) -{ -/* USER CODE BEGIN USBPD_PWR_IF_SNKDisable */ - return USBPD_ERROR; -/* USER CODE END USBPD_PWR_IF_SNKDisable */ -} - -/** - * @brief Initialize power on a specified port - * @param PortNum Port number - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_PWR_IF_InitPower(uint8_t PortNum) -{ - return USBPD_OK; -} - -/** - * @brief Checks if the power on a specified port is enabled - * @param PortNum Port number - * @retval USBPD_ENABLE or USBPD_DISABLE -*/ -USBPD_FunctionalState USBPD_PWR_IF_VBUSIsEnabled(uint8_t PortNum) -{ - /* Get the Status of the port */ - return USBPD_PORT_IsValid(PortNum) ? (USBPD_FunctionalState)HW_IF_PWR_VBUSIsEnabled(PortNum) : USBPD_DISABLE; -} - -/** - * @brief Reads the voltage and the current on a specified port - * @param PortNum Port number - * @param pVoltage: The Voltage in mV - * @param pCurrent: The Current in mA - * @retval USBPD_ERROR or USBPD_OK -*/ -USBPD_StatusTypeDef USBPD_PWR_IF_ReadVA(uint8_t PortNum, uint16_t *pVoltage, uint16_t *pCurrent) -{ -/* USER CODE BEGIN USBPD_PWR_IF_ReadVA */ - return USBPD_ERROR; -/* USER CODE END USBPD_PWR_IF_ReadVA */ -} - -/** - * @brief Enables the VConn on the port. - * @param PortNum Port number - * @param CC Specifies the CCx to be selected based on @ref CCxPin_TypeDef structure - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_PWR_IF_Enable_VConn(uint8_t PortNum, CCxPin_TypeDef CC) -{ -/* USER CODE BEGIN USBPD_PWR_IF_Enable_VConn */ - return USBPD_ERROR; -/* USER CODE END USBPD_PWR_IF_Enable_VConn */ -} - -/** - * @brief Disable the VConn on the port. - * @param PortNum Port number - * @param CC Specifies the CCx to be selected based on @ref CCxPin_TypeDef structure - * @retval USBPD status - */ -USBPD_StatusTypeDef USBPD_PWR_IF_Disable_VConn(uint8_t PortNum, CCxPin_TypeDef CC) -{ -/* USER CODE BEGIN USBPD_PWR_IF_Disable_VConn */ - return USBPD_ERROR; -/* USER CODE END USBPD_PWR_IF_Disable_VConn */ -} - -/** - * @brief Allow PDO data reading from PWR_IF storage. - * @param PortNum Port number - * @param DataId Type of data to be read from PWR_IF - * This parameter can be one of the following values: - * @arg @ref USBPD_CORE_DATATYPE_SRC_PDO Source PDO reading requested - * @arg @ref USBPD_CORE_DATATYPE_SNK_PDO Sink PDO reading requested - * @param Ptr Pointer on address where PDO values should be written (u8 pointer) - * @param Size Pointer on nb of u32 written by PWR_IF (nb of PDOs) - * @retval None - */ -void USBPD_PWR_IF_GetPortPDOs(uint8_t PortNum, USBPD_CORE_DataInfoType_TypeDef DataId, uint8_t *Ptr, uint32_t *Size) -{ -/* USER CODE BEGIN USBPD_PWR_IF_GetPortPDOs */ - -/* USER CODE END USBPD_PWR_IF_GetPortPDOs */ -} - -/** - * @brief Find out SRC PDO pointed out by a position provided in a Request DO (from Sink). - * @param PortNum Port number - * @param RdoPosition RDO Position in list of provided PDO - * @param Pdo Pointer on PDO value pointed out by RDO position (u32 pointer) - * @retval Status of search - * USBPD_OK : Src PDO found for requested DO position (output Pdo parameter is set) - * USBPD_FAIL : Position is not compliant with current Src PDO for this port (no corresponding PDO value) - */ -USBPD_StatusTypeDef USBPD_PWR_IF_SearchRequestedPDO(uint8_t PortNum, uint32_t RdoPosition, uint32_t *Pdo) -{ -/* USER CODE BEGIN USBPD_PWR_IF_SearchRequestedPDO */ - return USBPD_FAIL; -/* USER CODE END USBPD_PWR_IF_SearchRequestedPDO */ -} - -/** - * @brief the function is called in case of critical issue is detected to switch in safety mode. - * @retval None - */ -void USBPD_PWR_IF_Alarm() -{ -/* USER CODE BEGIN USBPD_PWR_IF_Alarm */ - -/* USER CODE END USBPD_PWR_IF_Alarm */ -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/Src/usbpd_pwr_user.c b/Software/VNA_embedded/Src/usbpd_pwr_user.c deleted file mode 100644 index 5052f2c..0000000 --- a/Software/VNA_embedded/Src/usbpd_pwr_user.c +++ /dev/null @@ -1,457 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file usbpd_pwr_user.c - * @author MCD Application Team - * @brief USBPD PWR user code - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbpd_pwr_user.h" -#include "stm32g4xx_hal.h" - -/* USER CODE BEGIN include */ - -/* USER CODE END include */ - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup POWER - * @{ - */ -/** @defgroup POWER_Private_Typedef Private Typedef - * @{ - */ -/* USER CODE BEGIN POWER_Private_Typedef */ - -/* USER CODE END POWER_Private_Typedef */ -/** - * @} - */ - -/** @defgroup POWER_Private_Constants Private Constants -* @{ -*/ -/* USER CODE BEGIN POWER_Private_Constants */ - -/* USER CODE END POWER_Private_Constants */ -/** - * @} - */ - -/** @defgroup POWER_Private_Macros Private Macros - * @{ - */ -/* USER CODE BEGIN POWER_Private_Macros */ - -/* USER CODE END POWER_Private_Macros */ -/** - * @} - */ - -/** @defgroup POWER_Private_Variables Private Variables - * @{ - */ -/* USER CODE BEGIN POWER_Private_Variables */ - -/* USER CODE END POWER_Private_Variables */ -/** - * @} - */ - -/** @defgroup POWER_Private_Functions Private Functions - * @{ - */ -/* USER CODE BEGIN POWER_Private_Prototypes */ - -/* USER CODE END POWER_Private_Prototypes */ -/** - * @} - */ - -/** @defgroup POWER_Exported_Variables Exported Variables - * @{ - */ -/* USER CODE BEGIN POWER_Exported_Variables */ - -/* USER CODE END POWER_Exported_Variables */ -/** - * @} - */ - -/** @addtogroup POWER_Exported_Functions - * @{ - */ -/** - * @brief Initialize the hardware resources used by the Type-C power delivery (PD) - * controller. - * @param PortId Type-C port identifier - * This parameter can be take one of the following values: - * @arg TYPE_C_PORT_1 - * @arg TYPE_C_PORT_2 - * @retval PD controller status - */ -PWR_StatusTypeDef BSP_PWR_VBUSInit(uint32_t PortId) -{ -/* USER CODE BEGIN BSP_PWR_VBUSInit */ - return PWR_ERROR; -/* USER CODE END BSP_PWR_VBUSInit */ -} - -/** - * @brief Release the hardware resources used by the Type-C power delivery (PD) - * controller. - * @param PortId Type-C port identifier - * This parameter can be take one of the following values: - * @arg TYPE_C_PORT_1 - * @arg TYPE_C_PORT_2 - * @retval PD controller status - */ -PWR_StatusTypeDef BSP_PWR_VBUSDeInit(uint32_t PortId) -{ -/* USER CODE BEGIN BSP_PWR_VBUSDeInit */ - return PWR_ERROR; -/* USER CODE END BSP_PWR_VBUSDeInit */ -} - -/** - * @brief Enable power supply over VBUS. - * @param PortId Type-C port identifier - * This parameter can be take one of the following values: - * @arg TYPE_C_PORT_1 - * @retval PD controller status - */ -PWR_StatusTypeDef BSP_PWR_VBUSOn(uint32_t PortId) -{ -/* USER CODE BEGIN BSP_PWR_VBUSOn */ - return PWR_ERROR; -/* USER CODE END BSP_PWR_VBUSOn */ -} - -/** - * @brief Disable power supply over VBUS. - * @param PortId Type-C port identifier - * This parameter can be take one of the following values: - * @arg TYPE_C_PORT_1 - * @retval PD controller status - */ -PWR_StatusTypeDef BSP_PWR_VBUSOff(uint32_t PortId) -{ -/* USER CODE BEGIN BSP_PWR_VBUSOff */ - return PWR_ERROR; -/* USER CODE END BSP_PWR_VBUSOff */ -} - -/** - * @brief Set a fixed/variable PDO and manage the power control. - * @param PortId Type-C port identifier - * This parameter can be take one of the following values: - * @arg TYPE_C_PORT_1 - * @param VbusTargetInmv the vbus Target (in mV) - * @param OperatingCurrent the Operating Current (in mA) - * @param MaxOperatingCurrent the Max Operating Current (in mA) - * @retval PD controller status - */ -PWR_StatusTypeDef BSP_PWR_VBUSSetVoltage_Fixed(uint32_t PortId, - uint32_t VbusTargetInmv, - uint32_t OperatingCurrent, - uint32_t MaxOperatingCurrent) -{ -/* USER CODE BEGIN BSP_PWR_VBUSSetVoltage_Fixed */ - return PWR_ERROR; -/* USER CODE END BSP_PWR_VBUSSetVoltage_Fixed */ -} - -/** - * @brief Set a fixed/variable PDO and manage the power control. - * @param PortId Type-C port identifier - * This parameter can be take one of the following values: - * @arg TYPE_C_PORT_1 - * @param VbusTargetMinInmv the vbus Target min (in mV) - * @param VbusTargetMaxInmv the vbus Target max (in mV) - * @param OperatingCurrent the Operating Current (in mA) - * @param MaxOperatingCurrent the Max Operating Current (in mA) - * @retval PD controller status - */ -PWR_StatusTypeDef BSP_PWR_VBUSSetVoltage_Variable(uint32_t PortId, - uint32_t VbusTargetMinInmv, - uint32_t VbusTargetMaxInmv, - uint32_t OperatingCurrent, - uint32_t MaxOperatingCurrent) -{ -/* USER CODE BEGIN BSP_PWR_VBUSSetVoltage_Variable */ - return PWR_ERROR; -/* USER CODE BEGIN BSP_PWR_VBUSSetVoltage_Variable */ -} - -/** - * @brief Set a Battery PDO and manage the power control. - * @param PortId Type-C port identifier - * This parameter can be take one of the following values: - * @arg TYPE_C_PORT_1 - * @param VbusTargetMin the vbus Target min (in mV) - * @param VbusTargetMax the vbus Target max (in mV) - * @param OperatingPower the Operating Power (in mW) - * @param MaxOperatingPower the Max Operating Power (in mW) - * @retval PD controller status - */ -PWR_StatusTypeDef BSP_PWR_VBUSSetVoltage_Battery(uint32_t PortId, - uint32_t VbusTargetMin, - uint32_t VbusTargetMax, - uint32_t OperatingPower, - uint32_t MaxOperatingPower) -{ -/* USER CODE BEGIN BSP_PWR_VBUSSetVoltage_Battery */ - return PWR_ERROR; -/* USER CODE BEGIN BSP_PWR_VBUSSetVoltage_Battery */ -} - -/** -* @brief Set a APDO and manage the power control. -* @param PortId Type-C port identifier -* This parameter can be take one of the following values: -* @arg TYPE_C_PORT_1 -* @param VbusTargetInmv the vbus Target (in mV) -* @param OperatingCurrent the Operating current (in mA) -* @param Delta Delta between with previous APDO (in mV), 0 means APDO start -* @retval PD controller status -*/ -PWR_StatusTypeDef BSP_PWR_VBUSSetVoltage_APDO(uint32_t PortId, - uint32_t VbusTargetInmv, - uint32_t OperatingCurrent, - int32_t Delta) -{ -/* USER CODE BEGIN BSP_PWR_VBUSSetVoltage_APDO */ - return PWR_ERROR; -/* USER CODE BEGIN BSP_PWR_VBUSSetVoltage_APDO */ -} - -/** - * @brief Get actual voltage level measured on the VBUS line. - * @param PortId Type-C port identifier - * This parameter can be take one of the following values: - * @arg TYPE_C_PORT_1 - * @arg TYPE_C_PORT_2 - * @retval Voltage measured voltage level (in mV) - */ -uint32_t BSP_PWR_VBUSGetVoltage(uint32_t PortId) -{ -/* USER CODE BEGIN BSP_PWR_VBUSGetVoltage */ - return 0; -/* USER CODE END BSP_PWR_VBUSGetVoltage */ -} - -/** - * @brief Get actual current level measured on the VBUS line. - * @param PortId Type-C port identifier - * This parameter can be take one of the following values: - * @arg TYPE_C_PORT_1 - * @arg TYPE_C_PORT_2 - * @retval Current measured current level (in mA) - */ -int32_t BSP_PWR_VBUSGetCurrent(uint32_t PortId) -{ -/* USER CODE BEGIN BSP_PWR_VBUSGetCurrent */ - return 0; -/* USER CODE END BSP_PWR_VBUSGetCurrent */ -} - -/** - * @brief Initialize VCONN sourcing. - * @param PortId Type-C port identifier - * This parameter can be take one of the following values: - * @arg TYPE_C_PORT_1 - * @arg TYPE_C_PORT_2 - * @param CCPinId Type-C CC pin identifier - * This parameter can be take one of the following values: - * @arg TYPE_C_CC1 - * @arg TYPE_C_CC2 - * @retval PD controller status - */ -PWR_StatusTypeDef BSP_PWR_VCONNInit(uint32_t PortId, - uint32_t CCPinId) -{ -/* USER CODE BEGIN BSP_PWR_VCONNInit */ - return PWR_ERROR; -/* USER CODE END BSP_PWR_VCONNInit */ -} - -/** - * @brief Un-Initialize VCONN sourcing. - * @param PortId Type-C port identifier - * This parameter can be take one of the following values: - * @arg TYPE_C_PORT_1 - * @arg TYPE_C_PORT_2 - * @param CCPinId Type-C CC pin identifier - * This parameter can be take one of the following values: - * @arg TYPE_C_CC1 - * @arg TYPE_C_CC2 - * @retval PD controller status - */ -PWR_StatusTypeDef BSP_PWR_VCONNDeInit(uint32_t PortId, - uint32_t CCPinId) -{ -/* USER CODE BEGIN BSP_PWR_VCONNDeInit */ - return PWR_ERROR; -/* USER CODE END BSP_PWR_VCONNDeInit */ -} - -/** - * @brief Enable VCONN sourcing. - * @param PortId Type-C port identifier - * This parameter can be take one of the following values: - * @arg TYPE_C_PORT_1 - * @arg TYPE_C_PORT_2 - * @param CCPinId Type-C CC pin identifier - * This parameter can be take one of the following values: - * @arg TYPE_C_CC1 - * @arg TYPE_C_CC2 - * @retval PD controller status - */ -PWR_StatusTypeDef BSP_PWR_VCONNOn(uint32_t PortId, - uint32_t CCPinId) -{ -/* USER CODE BEGIN BSP_PWR_VCONNOn */ - return PWR_ERROR; -/* USER CODE END BSP_PWR_VCONNOn */ -} - -/** - * @brief Disable VCONN sourcing. - * @param PortId Type-C port identifier - * This parameter can be take one of the following values: - * @arg TYPE_C_PORT_1 - * @arg TYPE_C_PORT_2 - * @param CCPinId CC pin identifier - * This parameter can be take one of the following values: - * @arg TYPE_C_CC1 - * @arg TYPE_C_CC2 - * @retval PD controller status - */ -PWR_StatusTypeDef BSP_PWR_VCONNOff(uint32_t PortId, - uint32_t CCPinId) -{ -/* USER CODE BEGIN BSP_PWR_VCONNOff */ - return PWR_ERROR; -/* USER CODE END BSP_PWR_VCONNOff */ -} - -/** - * @brief Set the VBUS disconnection voltage threshold. - * @note Callback funtion registered through BSP_PWR_RegisterVBUSDetectCallback - * function call is invoked when VBUS falls below programmed threshold. - * @note By default VBUS disconnection threshold is set to 3.3V - * @param PortId Type-C port identifier - * This parameter can be take one of the following values: - * @arg TYPE_C_PORT_1 - * @arg TYPE_C_PORT_2 - * @param VoltageThreshold: VBUS disconnection voltage threshold (in mV) - * @retval PD controller status - */ -void BSP_PWR_SetVBUSDisconnectionThreshold(uint32_t PortId, - uint32_t VoltageThreshold) -{ -/* USER CODE BEGIN BSP_PWR_SetVBUSDisconnectionThreshold */ - -/* USER CODE END BSP_PWR_SetVBUSDisconnectionThreshold */ -} - -/** - * @brief Register USB Type-C Current callback function. - * @note Callback function invoked when VBUS rises above 4V (VBUS present) or - * when VBUS falls below programmed threshold (VBUS absent). - * @note Callback funtion is un-registered when callback function pointer - * argument is NULL. - * @param PortId Type-C port identifier - * This parameter can be take one of the following values: - * @arg TYPE_C_PORT_1 - * @arg TYPE_C_PORT_2 - * @param pfnVBUSDetectCallback callback function pointer -* @retval 0 success else fail - */ -PWR_StatusTypeDef BSP_PWR_RegisterVBUSDetectCallback(uint32_t PortId, - PWR_VBUSDetectCallbackFunc * pfnVBUSDetectCallback) -{ -/* USER CODE BEGIN BSP_PWR_RegisterVBUSDetectCallback */ - return PWR_ERROR; -/* USER CODE END BSP_PWR_RegisterVBUSDetectCallback */ -} - -/** - * @brief Get actual VBUS status. - * @param PortId Type-C port identifier - * This parameter can be take one of the following values: - * @arg TYPE_C_PORT_1 - * @retval VBUS status (1: On, 0: Off) - */ -uint8_t BSP_PWR_VBUSIsOn(uint32_t PortId) -{ -/* USER CODE BEGIN BSP_PWR_VBUSIsOn */ - return 0; -/* USER CODE END BSP_PWR_VBUSIsOn */ -} - -/** - * @brief Get actual VCONN status. - * @param PortId Type-C port identifier - * This parameter can be take one of the following values: - * @arg TYPE_C_PORT_1 - * @param CCPinId Type-C CC pin identifier - * This parameter can be take one of the following values: - * @arg TYPE_C_CC1 - * @arg TYPE_C_CC2 - * @retval VCONN status (1: On, 0: Off) - */ -uint8_t BSP_PWR_VCONNIsOn(uint32_t PortId, - uint32_t CCPinId) -{ -/* USER CODE BEGIN BSP_PWR_VCONNIsOn */ - return 0; -/* USER CODE END BSP_PWR_VCONNIsOn */ -} - -/** - * @} - */ - -/** @addtogroup POWER_Private_Functions - * @{ - */ - -/* USER CODE BEGIN POWER_Private_Functions */ - -/* USER CODE END POWER_Private_Functions */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/Software/VNA_embedded/Src/usbpd_vdm_user.c b/Software/VNA_embedded/Src/usbpd_vdm_user.c deleted file mode 100644 index add28e9..0000000 --- a/Software/VNA_embedded/Src/usbpd_vdm_user.c +++ /dev/null @@ -1,470 +0,0 @@ -/** - ****************************************************************************** - * @file usbpd_vdm_user.c - * @author MCD Application Team - * @brief USBPD provider demo file - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbpd_core.h" -#include "usbpd_dpm_conf.h" -#include "usbpd_vdm_user.h" -#include "usbpd_dpm_user.h" -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/** @addtogroup STM32_USBPD_APPLICATION - * @{ - */ - -/** @addtogroup STM32_USBPD_APPLICATION_VDM_USER - * @{ - */ - -/* Private define ------------------------------------------------------------*/ -/* USER CODE BEGIN Private_define */ - -/* USER CODE END Private_define */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN Private_typedef */ - -/* USER CODE END Private_typedef */ - -/* Private macro -------------------------------------------------------------*/ -/* USER CODE BEGIN Private_macro */ - -/* USER CODE END Private_macro */ - -/* Private function prototypes -----------------------------------------------*/ -static USBPD_StatusTypeDef USBPD_VDM_DiscoverIdentity(uint8_t PortNum, USBPD_DiscoveryIdentity_TypeDef *pIdentity); -static USBPD_StatusTypeDef USBPD_VDM_DiscoverSVIDs(uint8_t PortNum, uint16_t **p_SVID_Info, uint8_t *nb); -static USBPD_StatusTypeDef USBPD_VDM_DiscoverModes(uint8_t PortNum, uint16_t SVID, uint32_t **p_ModeInfo, uint8_t *nbMode); -static USBPD_StatusTypeDef USBPD_VDM_ModeEnter(uint8_t PortNum, uint16_t SVID, uint32_t ModeIndex); -static USBPD_StatusTypeDef USBPD_VDM_ModeExit(uint8_t PortNum, uint16_t SVID, uint32_t ModeIndex); -static void USBPD_VDM_SendAttention(uint8_t PortNum, uint8_t *NbData, uint32_t *VDO); -static void USBPD_VDM_ReceiveAttention(uint8_t PortNum, uint8_t NbData, uint32_t VDO); -static USBPD_StatusTypeDef USBPD_VDM_ReceiveSpecific(uint8_t PortNum, USBPD_VDM_Command_Typedef VDMCommand, uint8_t *pNbData, uint32_t *pVDO); -static void USBPD_VDM_InformIdentity(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, USBPD_DiscoveryIdentity_TypeDef *pIdentity); -static void USBPD_VDM_InformSVID(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, USBPD_SVIDInfo_TypeDef *pListSVID); -static void USBPD_VDM_InformMode(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, USBPD_ModeInfo_TypeDef *pModesInfo); -static void USBPD_VDM_InformModeEnter(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, uint16_t SVID, uint32_t ModeIndex); -static void USBPD_VDM_InformModeExit(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, uint16_t SVID, uint32_t ModeIndex); -static void USBPD_VDM_InformSpecific(uint8_t PortNum, USBPD_VDM_Command_Typedef VDMCommand, uint8_t *NbData, uint32_t *VDO); -static void USBPD_VDM_SendSpecific(uint8_t PortNum, USBPD_VDM_Command_Typedef VDMCommand, uint8_t *NbData, uint32_t *VDO); -static void USBPD_VDM_SendUVDM(uint8_t PortNum, USBPD_UVDMHeader_TypeDef *pUVDM_Header, uint8_t *pNbData, uint32_t *pVDO); -static USBPD_StatusTypeDef USBPD_VDM_ReceiveUVDM(uint8_t PortNum, USBPD_UVDMHeader_TypeDef UVDM_Header, uint8_t *pNbData, uint32_t *pVDO); - -/* USER CODE BEGIN Private_prototypes */ - -/* USER CODE END Private_prototypes */ - -/* Private variables ---------------------------------------------------------*/ -/* USER CODE BEGIN Private_variables */ -const USBPD_VDM_Callbacks vdmCallbacks = -{ - USBPD_VDM_DiscoverIdentity, - USBPD_VDM_DiscoverSVIDs, - USBPD_VDM_DiscoverModes, - USBPD_VDM_ModeEnter, - USBPD_VDM_ModeExit, - USBPD_VDM_InformIdentity, - USBPD_VDM_InformSVID, - USBPD_VDM_InformMode, - USBPD_VDM_InformModeEnter, - USBPD_VDM_InformModeExit, - USBPD_VDM_SendAttention, - USBPD_VDM_ReceiveAttention, - USBPD_VDM_SendSpecific, - USBPD_VDM_ReceiveSpecific, - USBPD_VDM_InformSpecific, - USBPD_VDM_SendUVDM, - USBPD_VDM_ReceiveUVDM, -}; -/* USER CODE END Private_variables */ - -/* Private functions ---------------------------------------------------------*/ -/** - * @brief VDM Discovery identity callback - * @note Function is called to get Discovery identity information linked to the device and answer - * to SVDM Discovery identity init message sent by port partner - * @param PortNum current port number - * @param pIdentity Pointer on @ref USBPD_DiscoveryIdentity_TypeDef structure - * @retval USBPD status: @ref USBPD_ACK or @ref USBPD_BUSY - */ -static USBPD_StatusTypeDef USBPD_VDM_DiscoverIdentity(uint8_t PortNum, USBPD_DiscoveryIdentity_TypeDef *pIdentity) -{ -/* USER CODE BEGIN USBPD_VDM_DiscoverIdentity */ - return USBPD_NAK; -/* USER CODE END USBPD_VDM_DiscoverIdentity */ -} - -/** - * @brief VDM Discover SVID callback - * @note Function is called to retrieve SVID supported by device and answer - * to SVDM Discovery SVID init message sent by port partner - * @param PortNum current port number - * @param p_SVID_Info Pointer on @ref USBPD_SVIDInfo_TypeDef structure - * @param pNbSVID Pointer on number of SVID - * @retval USBPD status @ref USBPD_BUSY or @ref USBPD_ACK or @ref USBPD_NAK - */ -static USBPD_StatusTypeDef USBPD_VDM_DiscoverSVIDs(uint8_t PortNum, uint16_t **p_SVID_Info, uint8_t *pNbSVID) -{ -/* USER CODE BEGIN USBPD_VDM_DiscoverSVIDs */ - return USBPD_NAK; -/* USER CODE END USBPD_VDM_DiscoverSVIDs */ -} - -/** - * @brief VDM Discover Mode callback (report all the modes supported by SVID) - * @note Function is called to report all the modes supported by selected SVID and answer - * to SVDM Discovery Mode init message sent by port partner - * @param PortNum current port number - * @param SVID SVID value - * @param p_ModeTab Pointer on the mode value - * @param NumberOfMode Number of mode available - * @retval USBPD status - */ -static USBPD_StatusTypeDef USBPD_VDM_DiscoverModes(uint8_t PortNum, uint16_t SVID, uint32_t **p_ModeTab, uint8_t *NumberOfMode) -{ -/* USER CODE BEGIN USBPD_VDM_DiscoverModes */ - return USBPD_NAK; -/* USER CODE END USBPD_VDM_DiscoverModes */ -} - -/** - * @brief VDM Mode enter callback - * @note Function is called to check if device can enter in the mode received for the selected SVID in the - * SVDM enter mode init message sent by port partner - * @param PortNum current port number - * @param SVID SVID value - * @param ModeIndex Index of the mode to be entered - * @retval USBPD status @ref USBPD_ACK/@ref USBPD_NAK - */ -static USBPD_StatusTypeDef USBPD_VDM_ModeEnter(uint8_t PortNum, uint16_t SVID, uint32_t ModeIndex) -{ -/* USER CODE BEGIN USBPD_VDM_ModeEnter */ - return USBPD_NAK; -/* USER CODE END USBPD_VDM_ModeEnter */ -} - -/** - * @brief VDM Mode exit callback - * @note Function is called to check if device can exit from the mode received for the selected SVID in the - * SVDM exit mode init message sent by port partner - * @param PortNum current port number - * @param SVID SVID value - * @param ModeIndex Index of the mode to be exited - * @retval USBPD status @ref USBPD_ACK/@ref USBPD_NAK - */ -static USBPD_StatusTypeDef USBPD_VDM_ModeExit(uint8_t PortNum, uint16_t SVID, uint32_t ModeIndex) -{ -/* USER CODE BEGIN USBPD_VDM_ModeExit */ - return USBPD_NAK; -/* USER CODE END USBPD_VDM_ModeExit */ -} - -/** - * @brief Send VDM Attention message callback - * @note Function is called when device wants to send a SVDM attention message to port partner - * (for instance DP status can be filled through this function) - * @param PortNum current port number - * @param pNbData Pointer of number of VDO to send - * @param pVDO Pointer of VDO to send - * @retval None - */ -static void USBPD_VDM_SendAttention(uint8_t PortNum, uint8_t *pNbData, uint32_t *pVDO) -{ -/* USER CODE BEGIN USBPD_VDM_SendAttention */ - -/* USER CODE END USBPD_VDM_SendAttention */ -} - -/** - * @brief Receive VDM Attention callback - * @note Function is called when a SVDM attention init message has been received from port partner - * (for instance, save DP status data through this function) - * @param PortNum current port number - * @param NbData Number of received VDO - * @param VDO Received VDO - * @retval None - */ -static void USBPD_VDM_ReceiveAttention(uint8_t PortNum, uint8_t NbData, uint32_t VDO) -{ -/* USER CODE BEGIN USBPD_VDM_ReceiveAttention */ - -/* USER CODE END USBPD_VDM_ReceiveAttention */ -} - -/** - * @brief VDM Receive Specific message callback - * @note Function is called to answer to a SVDM specific init message received by port partner. - * (for instance, retrieve DP status or DP configure data through this function) - * @param PortNum Current port number - * @param VDMCommand VDM command based on @ref USBPD_VDM_Command_Typedef - * @param pNbData Pointer of number of received VDO and used for the answer - * @param pVDO Pointer of received VDO and use for the answer - * @retval USBPD Status - */ -static USBPD_StatusTypeDef USBPD_VDM_ReceiveSpecific(uint8_t PortNum, USBPD_VDM_Command_Typedef VDMCommand, uint8_t *pNbData, uint32_t *pVDO) -{ -/* USER CODE BEGIN USBPD_VDM_ReceiveSpecific */ - return USBPD_NAK; -/* USER CODE END USBPD_VDM_ReceiveSpecific */ -} - -/** - * @brief Inform identity callback - * @note Function is called to save Identity information received in Discovery identity from port partner - (answer to SVDM discovery identity sent by device) - * @param PortNum current port number - * @param SOPType SOP type - * @param CommandStatus Command status based on @ref USBPD_VDM_CommandType_Typedef - * @param pIdentity Pointer on the discovery identity information based on @ref USBPD_DiscoveryIdentity_TypeDef - * @retval None -*/ -static void USBPD_VDM_InformIdentity(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, USBPD_DiscoveryIdentity_TypeDef *pIdentity) -{ -/* USER CODE BEGIN USBPD_VDM_InformIdentity */ - switch(CommandStatus) - { - case SVDM_RESPONDER_ACK : - break; - case SVDM_RESPONDER_NAK : - break; - case SVDM_RESPONDER_BUSY : - break; - default : - break; - } -/* USER CODE END USBPD_VDM_InformIdentity */ -} - -/** - * @brief Inform SVID callback - * @note Function is called to save list of SVID received in Discovery SVID from port partner - (answer to SVDM discovery SVID sent by device) - * @param PortNum current port number - * @param SOPType SOP type - * @param CommandStatus Command status based on @ref USBPD_VDM_CommandType_Typedef - * @param pListSVID Pointer of list of SVID based on @ref USBPD_SVIDInfo_TypeDef - * @retval None - */ -static void USBPD_VDM_InformSVID(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, USBPD_SVIDInfo_TypeDef *pListSVID) -{ -/* USER CODE BEGIN USBPD_VDM_InformSVID */ - switch(CommandStatus) - { - case SVDM_RESPONDER_ACK : - break; - case SVDM_RESPONDER_NAK : - break; - case SVDM_RESPONDER_BUSY : - break; - default : - break; - } -/* USER CODE END USBPD_VDM_InformSVID */ -} - -/** - * @brief Inform Mode callback ( received in Discovery Modes ACK) - * @note Function is called to save list of modes linked to SVID received in Discovery mode from port partner - (answer to SVDM discovery mode sent by device) - * @param PortNum current port number - * @param SOPType SOP type - * @param CommandStatus Command status based on @ref USBPD_VDM_CommandType_Typedef - * @param pModesInfo Pointer of Modes info based on @ref USBPD_ModeInfo_TypeDef - * @retval None - */ -static void USBPD_VDM_InformMode(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, USBPD_ModeInfo_TypeDef *pModesInfo) -{ -/* USER CODE BEGIN USBPD_VDM_InformMode */ - switch(CommandStatus) - { - case SVDM_RESPONDER_ACK : - break; - case SVDM_RESPONDER_NAK : - break; - case SVDM_RESPONDER_BUSY : - break; - default : - break; - } -/* USER CODE END USBPD_VDM_InformMode */ -} - -/** - * @brief Inform Mode enter callback - * @note Function is called to inform if port partner accepted or not to enter in the mode - * specified in the SVDM enter mode sent by the device - * @param PortNum current port number - * @param SOPType SOP type - * @param CommandStatus Command status based on @ref USBPD_VDM_CommandType_Typedef - * @param SVID SVID ID - * @param ModeIndex Index of the mode to be entered - * @retval None - */ -static void USBPD_VDM_InformModeEnter(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, uint16_t SVID, uint32_t ModeIndex) -{ -/* USER CODE BEGIN USBPD_VDM_InformModeEnter */ - switch(CommandStatus) - { - case SVDM_RESPONDER_ACK : - break; - case SVDM_RESPONDER_NAK : - break; - case SVDM_RESPONDER_BUSY : - /* retry in 50ms */ - break; - default : - break; - } -/* USER CODE END USBPD_VDM_InformModeEnter */ -} - -/** - * @brief Inform Exit enter callback - * @param PortNum current port number - * @param SVID SVID ID - * @param ModeIndex Index of the mode to be entered - * @retval None - */ -static void USBPD_VDM_InformModeExit(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, uint16_t SVID, uint32_t ModeIndex) -{ -/* USER CODE BEGIN USBPD_VDM_InformModeExit */ - switch(CommandStatus) - { - case SVDM_RESPONDER_ACK : - break; - case SVDM_RESPONDER_NAK : - break; - case SVDM_RESPONDER_BUSY : - /* retry in 50ms */ - break; - default : - break; - } -/* USER CODE END USBPD_VDM_InformModeExit */ -} - -/** - * @brief VDM Send Specific message callback - * @note Function is called when device wants to send a SVDM specific init message to port partner - * (for instance DP status or DP configure can be filled through this function) - * @param PortNum current port number - * @param VDMCommand VDM command based on @ref USBPD_VDM_Command_Typedef - * @param pNbData Pointer of number of VDO to send - * @param pVDO Pointer of VDO to send - * @retval None - */ -static void USBPD_VDM_SendSpecific(uint8_t PortNum, USBPD_VDM_Command_Typedef VDMCommand, uint8_t *pNbData, uint32_t *pVDO) -{ -/* USER CODE BEGIN USBPD_VDM_SendSpecific */ - -/* USER CODE END USBPD_VDM_SendSpecific */ -} - -/** - * @brief VDM Specific message callback to inform user of reception of VDM specific message - * @note Function is called when answer from SVDM specific init message has been received by the device - * (for instance, save DP status and DP configure data through this function) - * @param PortNum current port number - * @param VDMCommand VDM command based on @ref USBPD_VDM_Command_Typedef - * @param pNbData Pointer of number of received VDO - * @param pVDO Pointer of received VDO - * @retval None - */ -static void USBPD_VDM_InformSpecific(uint8_t PortNum, USBPD_VDM_Command_Typedef VDMCommand, uint8_t *pNbData, uint32_t *pVDO) -{ -/* USER CODE BEGIN USBPD_VDM_InformSpecific */ - -/* USER CODE END USBPD_VDM_InformSpecific */ -} - -/** - * @brief VDM Send Unstructured message callback - * @param PortNum current port number - * @param pUVDM_Header Pointer on UVDM header based on @ref USBPD_UVDMHeader_TypeDef - * @param pNbData Pointer of number of VDO to send - * @param pVDO Pointer of VDO to send - * @retval None - */ -static void USBPD_VDM_SendUVDM(uint8_t PortNum, USBPD_UVDMHeader_TypeDef *pUVDM_Header, uint8_t *pNbData, uint32_t *pVDO) -{ -/* USER CODE BEGIN USBPD_VDM_SendUVDM */ - -/* USER CODE END USBPD_VDM_SendUVDM */ -} - -/** - * @brief Unstructured VDM message callback to inform user of reception of UVDM message - * @param PortNum current port number - * @param UVDM_Header UVDM header based on @ref USBPD_UVDMHeader_TypeDef - * @param pNbData Pointer of number of received VDO - * @param pVDO Pointer of received VDO - * @retval USBPD Status - */ -static USBPD_StatusTypeDef USBPD_VDM_ReceiveUVDM(uint8_t PortNum, USBPD_UVDMHeader_TypeDef UVDM_Header, uint8_t *pNbData, uint32_t *pVDO) -{ -/* USER CODE BEGIN USBPD_VDM_ReceiveUVDM */ - return USBPD_ERROR; -/* USER CODE END USBPD_VDM_ReceiveUVDM */ -} - -/* USER CODE BEGIN Private_functions */ - -/* USER CODE END Private_functions */ - -/* Exported functions ---------------------------------------------------------*/ -/** - * @brief VDM Initialization function - * @param PortNum Index of current used port - * @retval status - */ -USBPD_StatusTypeDef USBPD_VDM_UserInit(uint8_t PortNum) -{ -/* USER CODE BEGIN USBPD_VDM_UserInit */ - return USBPD_OK; -/* USER CODE END USBPD_VDM_UserInit */ -} - -/** - * @brief VDM Reset function - * @param PortNum Index of current used port - * @retval status - */ -void USBPD_VDM_UserReset(uint8_t PortNum) -{ -/* USER CODE BEGIN USBPD_VDM_UserReset */ - -/* USER CODE END USBPD_VDM_UserReset */ -} - -/* USER CODE BEGIN Exported_functions */ - -/* USER CODE END Exported_functions */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/Software/VNA_embedded/startup/startup_stm32g431xx.s b/Software/VNA_embedded/Startup/startup_stm32g431cbux.s similarity index 92% rename from Software/VNA_embedded/startup/startup_stm32g431xx.s rename to Software/VNA_embedded/Startup/startup_stm32g431cbux.s index 1d6e034..9ea4773 100644 --- a/Software/VNA_embedded/startup/startup_stm32g431xx.s +++ b/Software/VNA_embedded/Startup/startup_stm32g431cbux.s @@ -15,13 +15,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -496,4 +495,3 @@ g_pfnVectors: .weak FMAC_IRQHandler .thumb_set FMAC_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Software/VNA_embedded/VNA_embedded Debug.cfg b/Software/VNA_embedded/VNA_embedded Debug.cfg deleted file mode 100644 index 9abf4c7..0000000 --- a/Software/VNA_embedded/VNA_embedded Debug.cfg +++ /dev/null @@ -1,36 +0,0 @@ -# This is an VNA_embedded board with a single STM32G431CBUx chip -# -# Generated by System Workbench for STM32 -# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s) - -source [find interface/stlink.cfg] - -set WORKAREASIZE 0x5800 - -transport select "hla_swd" - -set CHIPNAME STM32G431CBUx -set BOARDNAME VNA_embedded - -# CHIPNAMES state -set CHIPNAME_CPU0_ACTIVATED 1 - -# Enable debug when in low power modes -set ENABLE_LOW_POWER 1 - -# Stop Watchdog counters when halt -set STOP_WATCHDOG 1 - -# STlink Debug clock frequency -set CLOCK_FREQ 8000 - -# use hardware reset, connect under reset -# connect_assert_srst needed if low power mode application running (WFI...) -reset_config srst_only srst_nogate connect_assert_srst -set CONNECT_UNDER_RESET 1 - -# BCTM CPU variables - - - -source [find target/stm32g4x.cfg] diff --git a/Software/VNA_embedded/VNA_embedded Debug.launch b/Software/VNA_embedded/VNA_embedded Debug.launch new file mode 100644 index 0000000..bcd0e30 --- /dev/null +++ b/Software/VNA_embedded/VNA_embedded Debug.launch @@ -0,0 +1,80 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Software/VNA_embedded/VNA_embedded.ioc b/Software/VNA_embedded/VNA_embedded.ioc index 185e95d..b2ba0ff 100644 --- a/Software/VNA_embedded/VNA_embedded.ioc +++ b/Software/VNA_embedded/VNA_embedded.ioc @@ -103,7 +103,6 @@ Mcu.IP10=TIM2 Mcu.IP11=UCPD1 Mcu.IP12=USART3 Mcu.IP13=USB -Mcu.IP14=USBPD Mcu.IP2=FREERTOS Mcu.IP3=I2C2 Mcu.IP4=NVIC @@ -112,7 +111,7 @@ Mcu.IP6=SPI1 Mcu.IP7=SPI2 Mcu.IP8=SYS Mcu.IP9=TIM1 -Mcu.IPNb=15 +Mcu.IPNb=14 Mcu.Name=STM32G431C(6-8-B)Ux Mcu.Package=UFQFPN48 Mcu.Pin0=PF1-OSC_OUT @@ -141,22 +140,21 @@ Mcu.Pin29=VP_ADC1_TempSens_Input Mcu.Pin3=PA3 Mcu.Pin30=VP_FREERTOS_VS_CMSIS_V1 Mcu.Pin31=VP_SYS_VS_tim17 -Mcu.Pin32=VP_TIM1_VS_ClockSourceINT -Mcu.Pin33=VP_TIM2_VS_ClockSourceINT -Mcu.Pin34=VP_USBPD_VS_USBPD1 -Mcu.Pin35=VP_USBPD_VS_usbpd_tim3 +Mcu.Pin32=VP_SYS_VS_DBSignals +Mcu.Pin33=VP_TIM1_VS_ClockSourceINT +Mcu.Pin34=VP_TIM2_VS_ClockSourceINT Mcu.Pin4=PA4 Mcu.Pin5=PA5 Mcu.Pin6=PA6 Mcu.Pin7=PA7 Mcu.Pin8=PC4 Mcu.Pin9=PB0 -Mcu.PinsNb=36 +Mcu.PinsNb=35 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32G431CBUx -MxCube.Version=5.2.1 -MxDb.Version=DB.5.0.21 +MxCube.Version=6.4.0 +MxDb.Version=DB.6.0.40 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.DMA1_Channel1_IRQn=true\:7\:0\:true\:false\:true\:true\:false\:true NVIC.DMA1_Channel2_IRQn=true\:7\:0\:true\:false\:true\:true\:false\:true @@ -173,7 +171,7 @@ NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false NVIC.SavedPendsvIrqHandlerGenerated=true NVIC.SavedSvcallIrqHandlerGenerated=true NVIC.SavedSystickIrqHandlerGenerated=true -NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false +NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:true NVIC.TIM1_TRG_COM_TIM17_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true NVIC.TimeBase=TIM1_TRG_COM_TIM17_IRQn NVIC.TimeBaseIP=TIM17 @@ -232,6 +230,8 @@ PA7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH PA7.Locked=true PA7.Mode=Full_Duplex_Master PA7.Signal=SPI1_MOSI +PA8.GPIOParameters=GPIO_Pu +PA8.GPIO_Pu=GPIO_PULLUP PA8.Locked=true PA8.Mode=I2C PA8.Signal=I2C2_SDA @@ -285,6 +285,8 @@ PB9.Signal=GPIO_Input PC10.Locked=true PC10.Mode=Asynchronous PC10.Signal=USART3_TX +PC4.GPIOParameters=GPIO_Pu +PC4.GPIO_Pu=GPIO_PULLUP PC4.Locked=true PC4.Mode=I2C PC4.Signal=I2C2_SCL @@ -302,7 +304,7 @@ ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32G431CBUx -ProjectManager.FirmwarePackage=STM32Cube FW_G4 V1.0.1 +ProjectManager.FirmwarePackage=STM32Cube FW_G4 V1.5.0 ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 @@ -317,7 +319,7 @@ ProjectManager.ProjectFileName=VNA_embedded.ioc ProjectManager.ProjectName=VNA_embedded ProjectManager.RegisterCallBack= ProjectManager.StackSize=0x400 -ProjectManager.TargetToolchain=SW4STM32 +ProjectManager.TargetToolchain=STM32CubeIDE ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=true ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_I2C2_Init-I2C2-false-HAL-true,5-MX_SPI1_Init-SPI1-false-HAL-true,6-MX_SPI2_Init-SPI2-false-HAL-true,7-MX_UCPD1_Init-UCPD1-false-LL-true,8-MX_USART3_UART_Init-USART3-false-HAL-true,9-MX_USB_PCD_Init-USB-false-HAL-true,10-MX_USBPD_Init-USBPD-false-HAL-false,11-MX_TIM1_Init-TIM1-false-HAL-true,12-MX_TIM2_Init-TIM2-false-HAL-true,13-MX_ADC1_Init-ADC1-false-HAL-true @@ -400,14 +402,13 @@ VP_ADC1_TempSens_Input.Mode=IN-TempSens VP_ADC1_TempSens_Input.Signal=ADC1_TempSens_Input VP_FREERTOS_VS_CMSIS_V1.Mode=CMSIS_V1 VP_FREERTOS_VS_CMSIS_V1.Signal=FREERTOS_VS_CMSIS_V1 +VP_SYS_VS_DBSignals.Mode=DisableDeadBatterySignals +VP_SYS_VS_DBSignals.Signal=SYS_VS_DBSignals VP_SYS_VS_tim17.Mode=TIM17 VP_SYS_VS_tim17.Signal=SYS_VS_tim17 VP_TIM1_VS_ClockSourceINT.Mode=Internal VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT VP_TIM2_VS_ClockSourceINT.Mode=Internal VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT -VP_USBPD_VS_USBPD1.Mode=USBPD_P0 -VP_USBPD_VS_USBPD1.Signal=USBPD_VS_USBPD1 -VP_USBPD_VS_usbpd_tim3.Mode=TIM3 -VP_USBPD_VS_usbpd_tim3.Signal=USBPD_VS_usbpd_tim3 board=custom +isbadioc=false diff --git a/Software/VNA_embedded/VNA_embedded.xml b/Software/VNA_embedded/VNA_embedded.xml deleted file mode 100644 index 72f5d11..0000000 --- a/Software/VNA_embedded/VNA_embedded.xml +++ /dev/null @@ -1,18 +0,0 @@ - - - - - - - - -]> - - - VNA_embedded - SWD - ST-Link - stm32g431cbux - -