mirror of
https://github.com/jankae/LibreVNA.git
synced 2025-12-06 07:12:10 +01:00
WIP: preparations for ADC rate switching
This commit is contained in:
Jan Käberich
parent
fe08937bb7
commit
b9f3c694d1
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@ -85,7 +85,17 @@ entity SPICommands is
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DFT_NEXT_OUTPUT : out STD_LOGIC;
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DFT_ENABLE : out STD_LOGIC;
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DEBUG_STATUS : in STD_LOGIC_VECTOR(10 downto 0));
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DEBUG_STATUS : in STD_LOGIC_VECTOR(10 downto 0);
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ADC_PRESCALER_ALT1 : out STD_LOGIC_VECTOR(7 downto 0);
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ADC_PHASEINC_ALT1 : out STD_LOGIC_VECTOR(11 downto 0);
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ADC_PRESCALER_ALT2 : out STD_LOGIC_VECTOR(7 downto 0);
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ADC_PHASEINC_ALT2 : out STD_LOGIC_VECTOR(11 downto 0);
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ADC_PRESCALER_ALT3 : out STD_LOGIC_VECTOR(7 downto 0);
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ADC_PHASEINC_ALT3 : out STD_LOGIC_VECTOR(11 downto 0);
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ADC_PRESCALER_ALT4 : out STD_LOGIC_VECTOR(7 downto 0);
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ADC_PHASEINC_ALT4 : out STD_LOGIC_VECTOR(11 downto 0)
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);
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end SPICommands;
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architecture Behavioral of SPICommands is
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@ -270,6 +280,14 @@ begin
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when 15 => MAX2871_DEF_4(31 downto 16) <= spi_buf_out;
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when 18 => DFT_BIN1_PHASEINC <= spi_buf_out;
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when 19 => DFT_DIFFBIN_PHASEINC <= spi_buf_out;
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when 24 => ADC_PRESCALER_ALT1 <= spi_buf_out(7 downto 0);
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when 25 => ADC_PHASEINC_ALT1 <= spi_buf_out(11 downto 0);
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when 26 => ADC_PRESCALER_ALT2 <= spi_buf_out(7 downto 0);
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when 27 => ADC_PHASEINC_ALT2 <= spi_buf_out(11 downto 0);
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when 28 => ADC_PRESCALER_ALT3 <= spi_buf_out(7 downto 0);
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when 29 => ADC_PHASEINC_ALT3 <= spi_buf_out(11 downto 0);
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when 30 => ADC_PRESCALER_ALT4 <= spi_buf_out(7 downto 0);
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when 31 => ADC_PHASEINC_ALT4 <= spi_buf_out(11 downto 0);
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when others =>
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end case;
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selected_register <= selected_register + 1;
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@ -82,6 +82,8 @@ entity Sweep is
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SOURCE_CE : out STD_LOGIC;
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ADC_SEL : out STD_LOGIC_VECTOR(2 downto 0);
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-- Debug signals
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DEBUG_STATUS : out STD_LOGIC_VECTOR (10 downto 0);
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RESULT_INDEX : out STD_LOGIC_VECTOR (15 downto 0)
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@ -124,15 +126,16 @@ begin
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SOURCE_FILTER <= config_reg(89 downto 88);
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BAND_SELECT <= config_reg(48);
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SOURCE_CE <= source_active;
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ADC_SEL <= config_reg(92 downto 90);
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NSAMPLES <= USER_NSAMPLES when config_reg(92 downto 90) = "000" else
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std_logic_vector(to_unsigned(6, 13)) when config_reg(92 downto 90) = "001" else
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std_logic_vector(to_unsigned(19, 13)) when config_reg(92 downto 90) = "010" else
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std_logic_vector(to_unsigned(57, 13)) when config_reg(92 downto 90) = "011" else
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std_logic_vector(to_unsigned(190, 13)) when config_reg(92 downto 90) = "100" else
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std_logic_vector(to_unsigned(571, 13)) when config_reg(92 downto 90) = "101" else
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std_logic_vector(to_unsigned(1904, 13)) when config_reg(92 downto 90) = "110" else
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std_logic_vector(to_unsigned(5712, 13));
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NSAMPLES <= USER_NSAMPLES;-- when config_reg(92 downto 90) = "000" else
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--std_logic_vector(to_unsigned(6, 13)) when config_reg(92 downto 90) = "001" else
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--std_logic_vector(to_unsigned(19, 13)) when config_reg(92 downto 90) = "010" else
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--std_logic_vector(to_unsigned(57, 13)) when config_reg(92 downto 90) = "011" else
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--std_logic_vector(to_unsigned(190, 13)) when config_reg(92 downto 90) = "100" else
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--std_logic_vector(to_unsigned(571, 13)) when config_reg(92 downto 90) = "101" else
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--std_logic_vector(to_unsigned(1904, 13)) when config_reg(92 downto 90) = "110" else
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--std_logic_vector(to_unsigned(5712, 13));
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DEBUG_STATUS(10 downto 7) <= "0000" when state = TriggerSetup else
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"0001" when state = SettingUp else
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@ -178,6 +178,7 @@
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<transform xil_pn:end_ts="1708955295" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1708955295">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForInputs"/>
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<outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
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<outfile xil_pn:name="ipcore_dir/DSP_SLICE.vhd"/>
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<outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
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@ -257,7 +258,7 @@
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1708953094" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1708953094">
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<transform xil_pn:end_ts="1716659207" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1716659207">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
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@ -286,7 +287,7 @@
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1708958126" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1708958116">
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<transform xil_pn:end_ts="1716659296" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1716659286">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="WarningsGenerated"/>
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<status xil_pn:value="ReadyToRun"/>
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@ -308,7 +309,7 @@
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1708958131" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1708958126">
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<transform xil_pn:end_ts="1716659313" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1716659309">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="_ngo"/>
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@ -317,7 +318,7 @@
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<outfile xil_pn:name="top.ngd"/>
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<outfile xil_pn:name="top_ngdbuild.xrpt"/>
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</transform>
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<transform xil_pn:end_ts="1708958154" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1708958131">
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<transform xil_pn:end_ts="1716659337" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1716659313">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="WarningsGenerated"/>
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<status xil_pn:value="ReadyToRun"/>
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@ -331,7 +332,7 @@
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<outfile xil_pn:name="top_summary.xml"/>
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<outfile xil_pn:name="top_usage.xml"/>
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</transform>
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<transform xil_pn:end_ts="1708958170" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1708958154">
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<transform xil_pn:end_ts="1716659352" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1716659337">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
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@ -345,7 +346,7 @@
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<outfile xil_pn:name="top_pad.txt"/>
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<outfile xil_pn:name="top_par.xrpt"/>
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</transform>
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<transform xil_pn:end_ts="1708958180" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1708958170">
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<transform xil_pn:end_ts="1716659362" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1716659352">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
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@ -398,7 +399,7 @@
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<status xil_pn:value="InputChanged"/>
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<status xil_pn:value="InputRemoved"/>
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</transform>
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<transform xil_pn:end_ts="1708958170" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1708958166">
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<transform xil_pn:end_ts="1716659352" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1716659348">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
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BIN
FPGA/VNA/top.bin
BIN
FPGA/VNA/top.bin
Binary file not shown.
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@ -152,6 +152,9 @@ architecture Behavioral of top is
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PORT1_ACTIVE : out STD_LOGIC;
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PORT2_ACTIVE : out STD_LOGIC;
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SOURCE_CE : out STD_LOGIC;
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ADC_SEL : out STD_LOGIC_VECTOR(2 downto 0);
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RESULT_INDEX : out STD_LOGIC_VECTOR (15 downto 0);
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DEBUG_STATUS : out STD_LOGIC_VECTOR (10 downto 0)
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);
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@ -284,7 +287,16 @@ architecture Behavioral of top is
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DFT_OUTPUT : in STD_LOGIC_VECTOR (191 downto 0);
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DFT_NEXT_OUTPUT : out STD_LOGIC;
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DFT_ENABLE : out STD_LOGIC;
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DEBUG_STATUS : in STD_LOGIC_VECTOR (10 downto 0)
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DEBUG_STATUS : in STD_LOGIC_VECTOR (10 downto 0);
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ADC_PRESCALER_ALT1 : out STD_LOGIC_VECTOR(7 downto 0);
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ADC_PHASEINC_ALT1 : out STD_LOGIC_VECTOR(11 downto 0);
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ADC_PRESCALER_ALT2 : out STD_LOGIC_VECTOR(7 downto 0);
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ADC_PHASEINC_ALT2 : out STD_LOGIC_VECTOR(11 downto 0);
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ADC_PRESCALER_ALT3 : out STD_LOGIC_VECTOR(7 downto 0);
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ADC_PHASEINC_ALT3 : out STD_LOGIC_VECTOR(11 downto 0);
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ADC_PRESCALER_ALT4 : out STD_LOGIC_VECTOR(7 downto 0);
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ADC_PHASEINC_ALT4 : out STD_LOGIC_VECTOR(11 downto 0)
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);
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END COMPONENT;
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@ -376,6 +388,17 @@ architecture Behavioral of top is
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signal sampling_prescaler : std_logic_vector(7 downto 0);
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signal sampling_phaseinc : std_logic_vector(11 downto 0);
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signal ADC_PRESCALER : STD_LOGIC_VECTOR(7 downto 0);
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signal ADC_PHASEINC : STD_LOGIC_VECTOR(11 downto 0);
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signal ADC_PRESCALER_ALT1 : STD_LOGIC_VECTOR(7 downto 0);
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signal ADC_PHASEINC_ALT1 : STD_LOGIC_VECTOR(11 downto 0);
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signal ADC_PRESCALER_ALT2 : STD_LOGIC_VECTOR(7 downto 0);
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signal ADC_PHASEINC_ALT2 : STD_LOGIC_VECTOR(11 downto 0);
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signal ADC_PRESCALER_ALT3 : STD_LOGIC_VECTOR(7 downto 0);
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signal ADC_PHASEINC_ALT3 : STD_LOGIC_VECTOR(11 downto 0);
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signal ADC_PRESCALER_ALT4 : STD_LOGIC_VECTOR(7 downto 0);
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signal ADC_PHASEINC_ALT4 : STD_LOGIC_VECTOR(11 downto 0);
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-- Sweep signals
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signal sweep_points : std_logic_vector(12 downto 0);
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signal sweep_stages : STD_LOGIC_VECTOR (2 downto 0);
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@ -405,6 +428,8 @@ architecture Behavioral of top is
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signal sweep_trigger_in : std_logic;
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signal sweep_trigger_out : std_logic;
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signal sweep_adc_sel : std_logic_vector(2 downto 0);
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-- Configuration signals
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signal settling_time : std_logic_vector(15 downto 0);
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signal def_reg_4 : std_logic_vector(31 downto 0);
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@ -727,6 +752,7 @@ begin
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PORT1_ACTIVE => sweep_excite_port1,
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PORT2_ACTIVE => sweep_excite_port2,
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SOURCE_CE => sweep_source_CE,
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ADC_SEL => sweep_adc_sel,
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DEBUG_STATUS => debug,
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RESULT_INDEX => sampling_result(303 downto 288)
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);
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@ -740,6 +766,18 @@ begin
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ATTENUATION <= sweep_attenuator when HW_overwrite_enabled = '0' else HW_overwrite_data(14 downto 8);
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-- ADC sample rate mapping
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sampling_prescaler <= ADC_PRESCALER when sweep_adc_sel(2) = '0' else
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ADC_PRESCALER_ALT1 when sweep_adc_sel(1 downto 0) = "00" else
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ADC_PRESCALER_ALT2 when sweep_adc_sel(1 downto 0) = "01" else
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ADC_PRESCALER_ALT3 when sweep_adc_sel(1 downto 0) = "10" else
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ADC_PRESCALER_ALT4;
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sampling_phaseinc <= ADC_PHASEINC when sweep_adc_sel(2) = '0' else
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ADC_PHASEINC_ALT1 when sweep_adc_sel(1 downto 0) = "00" else
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ADC_PHASEINC_ALT2 when sweep_adc_sel(1 downto 0) = "01" else
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ADC_PHASEINC_ALT3 when sweep_adc_sel(1 downto 0) = "10" else
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ADC_PHASEINC_ALT4;
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-- PLL/SPI mux
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-- only select FPGA SPI slave when both AUX1 and AUX2 are low
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fpga_select <= nss_sync when aux1_sync = '0' and aux2_sync = '0' else '1';
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@ -794,8 +832,8 @@ begin
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PORTSWITCH_EN => portswitch_en,
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LEDS => user_leds,
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WINDOW_SETTING => sampling_window,
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ADC_PRESCALER => sampling_prescaler,
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ADC_PHASEINC => sampling_phaseinc,
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ADC_PRESCALER => ADC_PRESCALER,
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ADC_PHASEINC => ADC_PHASEINC,
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INTERRUPT_ASSERTED => intr,
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RESET_MINMAX => adc_reset_minmax,
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SWEEP_HALTED => sweep_halted,
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@ -813,7 +851,15 @@ begin
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DFT_OUTPUT => dft_output,
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DFT_NEXT_OUTPUT => dft_next_output,
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DFT_ENABLE => dft_enable,
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DEBUG_STATUS => debug
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DEBUG_STATUS => debug,
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ADC_PRESCALER_ALT1 => ADC_PRESCALER_ALT1,
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ADC_PHASEINC_ALT1 => ADC_PHASEINC_ALT1,
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ADC_PRESCALER_ALT2 => ADC_PRESCALER_ALT2,
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ADC_PHASEINC_ALT2 => ADC_PHASEINC_ALT2,
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ADC_PRESCALER_ALT3 => ADC_PRESCALER_ALT3,
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ADC_PHASEINC_ALT3 => ADC_PHASEINC_ALT3,
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ADC_PRESCALER_ALT4 => ADC_PRESCALER_ALT4,
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ADC_PHASEINC_ALT4 => ADC_PHASEINC_ALT4
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);
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dft_reset <= not dft_enable;
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@ -199,7 +199,7 @@ void FPGA::WriteMAX2871Default(uint32_t *DefaultRegs) {
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}
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void FPGA::WriteSweepConfig(uint16_t pointnum, bool lowband, uint32_t *SourceRegs, uint32_t *LORegs,
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uint8_t attenuation, uint64_t frequency, SettlingTime settling, Samples samples, bool halt, LowpassFilter filter) {
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uint8_t attenuation, uint64_t frequency, SettlingTime settling, ADCSamplerate rate, bool halt, LowpassFilter filter) {
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uint16_t send[7];
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// select which point this sweep config is for
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send[0] = pointnum & 0x1FFF;
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@ -223,7 +223,7 @@ void FPGA::WriteSweepConfig(uint16_t pointnum, bool lowband, uint32_t *SourceReg
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send[1] |= 0x8000;
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}
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send[1] |= (int) settling << 13;
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send[1] |= (int) samples << 10;
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send[1] |= (int) rate << 10;
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if(filter == LowpassFilter::Auto) {
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// Select source LP filter
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if (frequency >= 3500000000) {
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@ -29,6 +29,14 @@ enum class Reg {
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MAX2871Def4MSB = 0x0F,
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DFTFirstBin = 0x12,
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DFTFreqSpacing = 0x13,
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ADCPrescalerAlt1 = 0x18,
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PhaseIncrementAlt1 = 0x19,
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ADCPrescalerAlt2 = 0x1A,
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PhaseIncrementAlt2 = 0x1B,
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ADCPrescalerAlt3 = 0x1C,
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PhaseIncrementAlt3 = 0x1D,
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ADCPrescalerAlt4 = 0x1E,
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PhaseIncrementAlt4 = 0x1F,
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};
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using SamplingResult = struct _samplingresult {
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@ -89,15 +97,12 @@ enum class SettlingTime {
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us540 = 0x03,
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};
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enum class Samples {
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SPPRegister = 0x00,
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S96 = 0x01,
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S304 = 0x02,
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S912 = 0x03,
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S3040 = 0x04,
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S9136 = 0x05,
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S30464 = 0x06,
|
||||
S91392 = 0x07,
|
||||
enum class ADCSamplerate {
|
||||
Default = 0x00,
|
||||
Alt1 = 0x04,
|
||||
Alt2 = 0x05,
|
||||
Alt3 = 0x06,
|
||||
Alt4 = 0x07,
|
||||
};
|
||||
|
||||
enum class Window {
|
||||
|
|
@ -124,7 +129,7 @@ void DisableInterrupt(Interrupt i);
|
|||
void DisableAllInterrupts();
|
||||
void WriteMAX2871Default(uint32_t *DefaultRegs);
|
||||
void WriteSweepConfig(uint16_t pointnum, bool lowband, uint32_t *SourceRegs, uint32_t *LORegs,
|
||||
uint8_t attenuation, uint64_t frequency, SettlingTime settling, Samples samples, bool halt = false, LowpassFilter filter = LowpassFilter::Auto);
|
||||
uint8_t attenuation, uint64_t frequency, SettlingTime settling, ADCSamplerate rate, bool halt = false, LowpassFilter filter = LowpassFilter::Auto);
|
||||
using ReadCallback = void(*)(const SamplingResult &result);
|
||||
bool InitiateSampleRead(ReadCallback cb);
|
||||
void SetupDFT(uint32_t f_firstBin, uint32_t f_binSpacing);
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@ void Manual::Setup(Protocol::ManualControl m) {
|
|||
// Configure single sweep point
|
||||
FPGA::WriteSweepConfig(0, !m.V1.SourceHighband, Source.GetRegisters(),
|
||||
LO1.GetRegisters(), m.V1.attenuator, 0, FPGA::SettlingTime::us60,
|
||||
FPGA::Samples::SPPRegister, 0,
|
||||
FPGA::ADCSamplerate::Default, 0,
|
||||
(FPGA::LowpassFilter) m.V1.SourceHighLowpass);
|
||||
|
||||
FPGA::SetWindow((FPGA::Window) m.V1.WindowType);
|
||||
|
|
|
|||
|
|
@ -175,7 +175,7 @@ static void StartNextSample() {
|
|||
|
||||
// Configure the sampling in the FPGA
|
||||
FPGA::WriteSweepConfig(0, trackingLowband, Source.GetRegisters(), LO1.GetRegisters(), attenuator,
|
||||
trackingFreq, FPGA::SettlingTime::us60, FPGA::Samples::SPPRegister, 0,
|
||||
trackingFreq, FPGA::SettlingTime::us60, FPGA::ADCSamplerate::Default, 0,
|
||||
FPGA::LowpassFilter::Auto);
|
||||
|
||||
if(firstSample && (signalIDstep == 0)) {
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@
|
|||
#include "usb.h"
|
||||
#include "Trigger.hpp"
|
||||
#include <cmath>
|
||||
#include <array>
|
||||
|
||||
#define LOG_LEVEL LOG_LEVEL_INFO
|
||||
#define LOG_MODULE "VNA"
|
||||
|
|
@ -51,6 +52,8 @@ static constexpr uint32_t reservedUSBbuffer = maxPointsBetweenHalts * (sizeof(Pr
|
|||
|
||||
using namespace HWHAL;
|
||||
|
||||
static constexpr uint8_t alternativePrescalers[] = {112, 113, 114, 115};
|
||||
|
||||
static uint64_t getPointFrequency(uint16_t pointNum) {
|
||||
if(!settings.logSweep) {
|
||||
return settings.f_start + (settings.f_stop - settings.f_start) * pointNum / (settings.points - 1);
|
||||
|
|
@ -70,51 +73,220 @@ static uint64_t getPointFrequency(uint16_t pointNum) {
|
|||
}
|
||||
}
|
||||
|
||||
static void setPLLFrequencies(uint64_t f) {
|
||||
if(f > HW::Info.limits_maxFreq) {
|
||||
Source.SetFrequency(f / sourceHarmonic);
|
||||
LO1.SetFrequency((f + HW::getIF1()) / LOHarmonic);
|
||||
} else {
|
||||
if(f >= HW::BandSwitchFrequency) {
|
||||
Source.SetFrequency(f);
|
||||
static uint32_t closestLOAlias(uint64_t LO1, uint64_t LO2, uint32_t IFBW) {
|
||||
constexpr uint64_t max_LO_harmonic = 2000000000;
|
||||
constexpr uint32_t max_ADC_alias = 5000000;
|
||||
|
||||
uint32_t closestAlias = std::numeric_limits<uint32_t>::max();
|
||||
|
||||
for(int64_t lo1 = LO1; lo1 <= (int64_t) max_LO_harmonic; lo1 += LO1) {
|
||||
// figure out which 2.LO harmonics we have to check
|
||||
uint64_t lo2_min = lo1 - max_ADC_alias;
|
||||
uint64_t lo2_max = lo1 + max_ADC_alias;
|
||||
|
||||
uint16_t lo2_min_harm = ((lo2_min + LO2 - 1) / LO2);
|
||||
uint16_t lo2_max_harm = lo2_max / LO2;
|
||||
|
||||
if(lo2_max_harm * LO2 > max_LO_harmonic) {
|
||||
lo2_max_harm = max_LO_harmonic / LO2;
|
||||
}
|
||||
LO1.SetFrequency(f + HW::getIF1());
|
||||
|
||||
if(lo2_min_harm > lo2_max_harm) {
|
||||
// no aliasing possible, skip 2.LO loop
|
||||
continue;
|
||||
}
|
||||
|
||||
for(int64_t lo2 = LO2 * lo2_min_harm; lo2 <= (int64_t) LO2 * lo2_max_harm; lo2 += LO2) {
|
||||
uint32_t mixing = llabs(lo1 - lo2);
|
||||
if(mixing > max_ADC_alias) {
|
||||
continue;
|
||||
}
|
||||
int32_t alias = Util::Alias(mixing, HW::getADCRate());
|
||||
uint32_t alias_dist = labs((int32_t) HW::getIF2() - alias);
|
||||
if(alias_dist < closestAlias) {
|
||||
closestAlias = alias_dist;
|
||||
}
|
||||
// if(abs(HW::getIF2() - alias) <= IFBW*3) {
|
||||
// // we do have LO mixing products aliasing into the 2.IF
|
||||
// return false;
|
||||
// }
|
||||
}
|
||||
}
|
||||
return closestAlias;
|
||||
}
|
||||
|
||||
static bool needs2LOshift(uint64_t f, uint32_t current2LO, uint32_t IFBW, uint32_t *new2LO) {
|
||||
// Check if 2.LO needs to be shifted
|
||||
uint64_t actualSource, actual1LO;
|
||||
static bool noLOAliasing(uint64_t LO1, uint64_t LO2, uint32_t IFBW) {
|
||||
constexpr uint64_t max_LO_harmonic = 2000000000;
|
||||
constexpr uint32_t max_ADC_alias = 5000000;
|
||||
|
||||
for(int64_t lo1 = LO1; lo1 <= (int64_t) max_LO_harmonic; lo1 += LO1) {
|
||||
// figure out which 2.LO harmonics we have to check
|
||||
uint64_t lo2_min = lo1 - max_ADC_alias;
|
||||
uint64_t lo2_max = lo1 + max_ADC_alias;
|
||||
|
||||
uint16_t lo2_min_harm = ((lo2_min + LO2 - 1) / LO2);
|
||||
uint16_t lo2_max_harm = lo2_max / LO2;
|
||||
|
||||
if(lo2_max_harm * LO2 > max_LO_harmonic) {
|
||||
lo2_max_harm = max_LO_harmonic / LO2;
|
||||
}
|
||||
|
||||
if(lo2_min_harm > lo2_max_harm) {
|
||||
// no aliasing possible, skip 2.LO loop
|
||||
continue;
|
||||
}
|
||||
|
||||
for(int64_t lo2 = LO2 * lo2_min_harm; lo2 <= (int64_t) LO2 * lo2_max_harm; lo2 += LO2) {
|
||||
uint32_t mixing = llabs(lo1 - lo2);
|
||||
if(mixing > max_ADC_alias) {
|
||||
continue;
|
||||
}
|
||||
int32_t alias = Util::Alias(mixing, HW::getADCRate());
|
||||
if(abs(HW::getIF2() - alias) <= IFBW*3) {
|
||||
// we do have LO mixing products aliasing into the 2.IF
|
||||
return false;
|
||||
}
|
||||
}
|
||||
}
|
||||
// all good, no aliasing
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool setPLLFrequencies(uint64_t f, uint32_t current2LO, uint32_t IFBW, uint32_t *new2LO) {
|
||||
const std::array<uint32_t, 21> IF_shifts = { 0, IFBW * 2, IFBW * 3,
|
||||
IFBW * 5, IFBW * 7, IFBW * 7 / 10, IFBW * 11 / 10, IFBW * 13
|
||||
/ 10, IFBW * 17 / 10, IFBW * 19 / 10, IFBW, IFBW * 23 / 10,
|
||||
IFBW * 29 / 10, IFBW * 31 / 10, IFBW * 37 / 10, IFBW * 41 / 10, IFBW
|
||||
* 43 / 10, IFBW * 47 / 10, IFBW * 53 / 10, IFBW * 59 / 10,
|
||||
IFBW * 61 / 10 };
|
||||
|
||||
uint64_t actualSource;
|
||||
// set the source, this will never change
|
||||
if (f > HW::Info.limits_maxFreq) {
|
||||
Source.SetFrequency(f / sourceHarmonic);
|
||||
actualSource = Source.GetActualFrequency() * sourceHarmonic;
|
||||
} else if (f >= HW::BandSwitchFrequency) {
|
||||
Source.SetFrequency(f);
|
||||
actualSource = Source.GetActualFrequency();
|
||||
actual1LO = LO1.GetActualFrequency();
|
||||
if(f > HW::Info.limits_maxFreq) {
|
||||
actualSource *= sourceHarmonic;
|
||||
actual1LO *= LOHarmonic;
|
||||
} else if(f < HW::BandSwitchFrequency) {
|
||||
// can use the lowband PLL with high frequency resolution, assume perfect frequency match
|
||||
} else {
|
||||
// source will be set in sweep halted interrupt
|
||||
actualSource = f;
|
||||
}
|
||||
|
||||
uint8_t maxIndex = IF_shifts.size();
|
||||
if(!settings.suppressPeaks) {
|
||||
maxIndex = 1;
|
||||
}
|
||||
|
||||
uint8_t bestIndex = 0;
|
||||
uint32_t furthestAliasDistance = 0;
|
||||
|
||||
for(uint8_t i = 0;i<maxIndex;i++) {
|
||||
auto shift = IF_shifts[i];
|
||||
// set the 1.LO
|
||||
uint64_t actual1LO;
|
||||
if(f > HW::Info.limits_maxFreq) {
|
||||
LO1.SetFrequency((f + HW::getIF1() + shift) / LOHarmonic);
|
||||
actual1LO = LO1.GetActualFrequency() * LOHarmonic;
|
||||
} else {
|
||||
LO1.SetFrequency(f + HW::getIF1() + shift);
|
||||
actual1LO = LO1.GetActualFrequency();
|
||||
}
|
||||
// adjust 2.LO if necessary
|
||||
*new2LO = current2LO;
|
||||
uint32_t actualFirstIF = actual1LO - actualSource;
|
||||
uint32_t actualFinalIF = actualFirstIF - current2LO;
|
||||
uint32_t actualFinalIF = actualFirstIF - *new2LO;
|
||||
uint32_t IFdeviation = abs(actualFinalIF - HW::getIF2());
|
||||
if(IFdeviation > IFBW / 2) {
|
||||
*new2LO = actualFirstIF - HW::getIF2();
|
||||
return true;
|
||||
} else {
|
||||
// no shift required
|
||||
return false;
|
||||
}
|
||||
|
||||
// LOG_ERR("Checking F=%lu, SRC=%lu, LO1=%lu", (uint32_t) f, (uint32_t) actualSource, (uint32_t) actual1LO);
|
||||
|
||||
auto closest_alias = closestLOAlias(actual1LO, *new2LO, IFBW);
|
||||
if(closest_alias > IFBW * 3) {
|
||||
// no need to look further, chose this option
|
||||
return true;
|
||||
} else if(closest_alias > furthestAliasDistance) {
|
||||
bestIndex = i;
|
||||
furthestAliasDistance = closest_alias;
|
||||
}
|
||||
|
||||
// // check if LO mixing product aliases into the ADC
|
||||
// if(noLOAliasing(actual1LO, *new2LO, IFBW)) {
|
||||
// // found an IF that can be used without problems
|
||||
// if(shift != 0) {
|
||||
//// LOG_WARN("Shifting IF for f=%lu, LO1=%lu, LO2= %lu", (uint32_t) f, (uint32_t) actual1LO, *new2LO);
|
||||
// }
|
||||
// return true;
|
||||
// }
|
||||
}
|
||||
// all available IF shifts result in aliasing in the ADC
|
||||
// LOG_ERR("Failed to shift IF for f=%lu", (uint32_t) f);
|
||||
// no perfect option, use best shift
|
||||
auto shift = IF_shifts[bestIndex];
|
||||
// set the 1.LO
|
||||
uint64_t actual1LO;
|
||||
if(f > HW::Info.limits_maxFreq) {
|
||||
LO1.SetFrequency((f + HW::getIF1() + shift) / LOHarmonic);
|
||||
actual1LO = LO1.GetActualFrequency() * LOHarmonic;
|
||||
} else {
|
||||
LO1.SetFrequency(f + HW::getIF1() + shift);
|
||||
actual1LO = LO1.GetActualFrequency();
|
||||
}
|
||||
// adjust 2.LO if necessary
|
||||
*new2LO = current2LO;
|
||||
uint32_t actualFirstIF = actual1LO - actualSource;
|
||||
uint32_t actualFinalIF = actualFirstIF - *new2LO;
|
||||
uint32_t IFdeviation = abs(actualFinalIF - HW::getIF2());
|
||||
if(IFdeviation > IFBW / 2) {
|
||||
*new2LO = actualFirstIF - HW::getIF2();
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
//static bool needs2LOshift(uint64_t f, uint32_t current2LO, uint32_t IFBW, uint32_t *new2LO) {
|
||||
// // Check if 2.LO needs to be shifted
|
||||
// uint64_t actualSource, actual1LO;
|
||||
// actualSource = Source.GetActualFrequency();
|
||||
// actual1LO = LO1.GetActualFrequency();
|
||||
// if(f > HW::Info.limits_maxFreq) {
|
||||
// actualSource *= sourceHarmonic;
|
||||
// actual1LO *= LOHarmonic;
|
||||
// } else if(f < HW::BandSwitchFrequency) {
|
||||
// // can use the lowband PLL with high frequency resolution, assume perfect frequency match
|
||||
// actualSource = f;
|
||||
// }
|
||||
// uint32_t actualFirstIF = actual1LO - actualSource;
|
||||
// uint32_t actualFinalIF = actualFirstIF - current2LO;
|
||||
// uint32_t IFdeviation = abs(actualFinalIF - HW::getIF2());
|
||||
// if(IFdeviation > IFBW / 2) {
|
||||
// *new2LO = actualFirstIF - HW::getIF2();
|
||||
// return true;
|
||||
// } else {
|
||||
// // no shift required
|
||||
// return false;
|
||||
// }
|
||||
//}
|
||||
|
||||
bool VNA::Setup(Protocol::SweepSettings s) {
|
||||
// Abort possible active sweep first
|
||||
VNA::Stop();
|
||||
vTaskDelay(5);
|
||||
data.clear();
|
||||
HW::SetMode(HW::Mode::VNA);
|
||||
// Abort possible active sweep first
|
||||
FPGA::SetMode(FPGA::Mode::FPGA);
|
||||
// Configure the ADC prescalers
|
||||
FPGA::WriteRegister(FPGA::Reg::ADCPrescaler, HW::getADCPrescaler());
|
||||
FPGA::WriteRegister(FPGA::Reg::PhaseIncrement, HW::getDFTPhaseInc());
|
||||
FPGA::WriteRegister(FPGA::Reg::ADCPrescalerAlt1, alternativePrescalers[0]);
|
||||
FPGA::WriteRegister(FPGA::Reg::PhaseIncrementAlt1, alternativePrescalers[0]*10);
|
||||
FPGA::WriteRegister(FPGA::Reg::ADCPrescalerAlt2, alternativePrescalers[1]);
|
||||
FPGA::WriteRegister(FPGA::Reg::PhaseIncrementAlt2, alternativePrescalers[1]*10);
|
||||
FPGA::WriteRegister(FPGA::Reg::ADCPrescalerAlt3, alternativePrescalers[2]);
|
||||
FPGA::WriteRegister(FPGA::Reg::PhaseIncrementAlt3, alternativePrescalers[2]*10);
|
||||
FPGA::WriteRegister(FPGA::Reg::ADCPrescalerAlt4, alternativePrescalers[3]);
|
||||
FPGA::WriteRegister(FPGA::Reg::PhaseIncrementAlt4, alternativePrescalers[3]*10);
|
||||
if(settings.points > FPGA::MaxPoints) {
|
||||
settings.points = FPGA::MaxPoints;
|
||||
}
|
||||
|
|
@ -192,12 +364,13 @@ bool VNA::Setup(Protocol::SweepSettings s) {
|
|||
}
|
||||
// SetFrequency only manipulates the register content in RAM, no SPI communication is done.
|
||||
// No mode-switch of FPGA necessary here.
|
||||
setPLLFrequencies(freq);
|
||||
if(s.suppressPeaks) {
|
||||
if(needs2LOshift(freq, last_LO2, actualBandwidth, &last_LO2)) {
|
||||
uint32_t new2LO;
|
||||
setPLLFrequencies(freq, last_LO2, actualBandwidth, &new2LO);
|
||||
if(new2LO != last_LO2 && s.suppressPeaks) {
|
||||
last_LO2 = new2LO;
|
||||
needs_halt = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (last_lowband && !lowband) {
|
||||
// additional halt before first highband point to enable highband source
|
||||
needs_halt = true;
|
||||
|
|
@ -233,7 +406,7 @@ bool VNA::Setup(Protocol::SweepSettings s) {
|
|||
|
||||
FPGA::WriteSweepConfig(i, lowband, Source.GetRegisters(),
|
||||
LO1.GetRegisters(), attenuator, freq, FPGA::SettlingTime::us60,
|
||||
FPGA::Samples::SPPRegister, needs_halt);
|
||||
FPGA::ADCSamplerate::Default, needs_halt);
|
||||
last_lowband = lowband;
|
||||
}
|
||||
// revert clk configuration to previous value (might have been changed in sweep calculation)
|
||||
|
|
@ -261,6 +434,7 @@ bool VNA::Setup(Protocol::SweepSettings s) {
|
|||
FPGA::EnableInterrupt(FPGA::Interrupt::NewData);
|
||||
FPGA::EnableInterrupt(FPGA::Interrupt::SweepHalted);
|
||||
// Start the sweep if not configured for standby
|
||||
last_LO2 = HW::getIF1() - HW::getIF2();
|
||||
firstPoint = true;
|
||||
if (settings.standby) {
|
||||
waitingInStandby = true;
|
||||
|
|
@ -426,8 +600,10 @@ void VNA::SweepHalted() {
|
|||
if(settings.suppressPeaks) {
|
||||
// does not actually change PLL settings, just calculates the register values and
|
||||
// is required to determine the need for a 2.LO shift
|
||||
setPLLFrequencies(frequency);
|
||||
if(needs2LOshift(frequency, last_LO2, actualBandwidth, &last_LO2)) {
|
||||
uint32_t new2LO;
|
||||
setPLLFrequencies(frequency, last_LO2, actualBandwidth, &new2LO);
|
||||
if(new2LO != last_LO2) {
|
||||
last_LO2 = new2LO;
|
||||
Si5351.SetCLK(SiChannel::Port1LO2, last_LO2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
|
||||
Si5351.SetCLK(SiChannel::Port2LO2, last_LO2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
|
||||
Si5351.SetCLK(SiChannel::RefLO2, last_LO2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
|
||||
|
|
|
|||
Loading…
Reference in a new issue