mirror of
https://github.com/jankae/LibreVNA.git
synced 2026-04-08 07:53:40 +00:00
Working dwell time feature
- Bugfixes: - improve SPI timing in FPGA - fix markers and reduce CPU load when using markers with fast traces - New features: - dwell time configurable in acquisition toolbar - PLL settling delay in device configuration - device configuration persistent across power cycles
This commit is contained in:
Jan Käberich
parent
24314e2361
commit
a4faeb28b0
35 changed files with 516 additions and 289 deletions
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@ -91,7 +91,8 @@ end SPICommands;
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architecture Behavioral of SPICommands is
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COMPONENT spi_slave
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Generic(W : integer);
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Generic(W : integer;
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PREWIDTH : integer);
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PORT(
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SPI_CLK : in STD_LOGIC;
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MISO : out STD_LOGIC;
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@ -100,7 +101,9 @@ architecture Behavioral of SPICommands is
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BUF_OUT : out STD_LOGIC_VECTOR (W-1 downto 0) := (others => '0');
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BUF_IN : in STD_LOGIC_VECTOR (W-1 downto 0);
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CLK : in STD_LOGIC;
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COMPLETE : out STD_LOGIC
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COMPLETE : out STD_LOGIC;
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PRE_COMPLETE : out STD_LOGIC;
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PRE_BUF_OUT : out STD_LOGIC_VECTOR (PREWIDTH-1 downto 0)
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);
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END COMPONENT;
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@ -108,6 +111,8 @@ architecture Behavioral of SPICommands is
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signal spi_buf_out : std_logic_vector(15 downto 0);
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signal spi_buf_in : std_logic_vector(15 downto 0);
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signal spi_complete : std_logic;
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signal spi_pre_complete : std_logic;
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signal spi_pre_buf_out : std_logic_vector(2 downto 0);
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signal word_cnt : integer range 0 to 19;
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type SPI_states is (FirstWord, WriteSweepConfig, ReadResult, WriteRegister);
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signal state : SPI_states;
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@ -128,7 +133,8 @@ architecture Behavioral of SPICommands is
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signal sweepconfig_buffer : std_logic_vector(79 downto 0);
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begin
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SPI: spi_slave
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GENERIC MAP(w => 16)
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GENERIC MAP(W => 16,
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PREWIDTH => 3)
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PORT MAP(
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SPI_CLK => SCLK,
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MISO => MISO,
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@ -137,7 +143,9 @@ begin
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BUF_OUT => spi_buf_out,
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BUF_IN => spi_buf_in,
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CLK => CLK,
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COMPLETE =>spi_complete
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COMPLETE => spi_complete,
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PRE_COMPLETE => spi_pre_complete,
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PRE_BUF_OUT => spi_pre_buf_out
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);
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SWEEP_WRITE(0) <= sweep_config_write;
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@ -205,91 +213,113 @@ begin
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word_cnt <= 0;
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spi_buf_in <= interrupt_status;
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state <= FirstWord;
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elsif spi_complete = '1' then
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word_cnt <= word_cnt + 1;
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else
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-- handle read operations when the first PREWIDTH bits are complete
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if spi_pre_complete = '1' then
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case state is
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when FirstWord =>
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-- initial word determines action
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case spi_buf_out(15 downto 13) is
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when "000" => state <= WriteSweepConfig;
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-- also extract the point number
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SWEEP_ADDRESS <= spi_buf_out(12 downto 0);
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when "001" => state <= FirstWord;
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SWEEP_RESUME <= '1';
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when "010" => state <= FirstWord;
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spi_buf_in <= "1111000010100101";
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when "011" => state <= FirstWord;
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RESET_MINMAX <= '1';
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when "100" => state <= WriteRegister;
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selected_register <= to_integer(unsigned(spi_buf_out(4 downto 0)));
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when "101" => state <= ReadResult;-- can use same state as read result, but the latched data will contain the DFT values
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latched_result(175 downto 0) <= DFT_OUTPUT(191 downto 16);
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spi_buf_in <= DFT_OUTPUT(15 downto 0);
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dft_next <= '1';
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when "110" => state <= ReadResult;
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latched_result <= SAMPLING_RESULT(303 downto 16);
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spi_buf_in <= SAMPLING_RESULT(15 downto 0);
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unread_sampling_data <= '0';
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when "111" => state <= ReadResult; -- can use same state as read result, but the latched data will contain the min/max ADC values
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latched_result(79 downto 0) <= ADC_MINMAX(95 downto 16);
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spi_buf_in <= ADC_MINMAX(15 downto 0);
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when others => state <= FirstWord;
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-- initial word determines the action
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case spi_pre_buf_out is
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when "010" => state <= FirstWord;
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spi_buf_in <= "1111000010100101";
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when "101" => state <= ReadResult;-- can use same state as read result, but the latched data will contain the DFT values
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latched_result(175 downto 0) <= DFT_OUTPUT(191 downto 16);
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spi_buf_in <= DFT_OUTPUT(15 downto 0);
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dft_next <= '1';
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when "110" => state <= ReadResult;
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latched_result <= SAMPLING_RESULT(303 downto 16);
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spi_buf_in <= SAMPLING_RESULT(15 downto 0);
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unread_sampling_data <= '0';
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when "111" => state <= ReadResult; -- can use same state as read result, but the latched data will contain the min/max ADC values
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latched_result(79 downto 0) <= ADC_MINMAX(95 downto 16);
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spi_buf_in <= ADC_MINMAX(15 downto 0);
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--ignore other options
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when others =>
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end case;
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when WriteRegister =>
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-- write received data into previously selected register
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case selected_register is
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when 0 => interrupt_mask <= spi_buf_out;
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when 1 => SWEEP_POINTS <= spi_buf_out(12 downto 0);
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when 2 => NSAMPLES <= spi_buf_out(12 downto 0);
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when 3 => PORTSWITCH_EN <= spi_buf_out(0);
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PORT1_EN <= spi_buf_out(15);
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PORT2_EN <= spi_buf_out(14);
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REF_EN <= spi_buf_out(13);
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AMP_SHDN <= not spi_buf_out(12);
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SOURCE_RF_EN <= spi_buf_out(11);
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LO_RF_EN <= spi_buf_out(10);
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LEDS <= not spi_buf_out(9 downto 7);
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WINDOW_SETTING <= spi_buf_out(6 downto 5);
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SOURCE_CE_EN <= spi_buf_out(4);
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LO_CE_EN <= spi_buf_out(3);
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SYNC_MASTER <= spi_buf_out(1);
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when 4 => ADC_PRESCALER <= spi_buf_out(7 downto 0);
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when 5 => ADC_PHASEINC <= spi_buf_out(11 downto 0);
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when 6 => STAGES <= spi_buf_out(15 downto 13);
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SYNC_ENABLED <= spi_buf_out(12);
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PORT1_STAGE <= spi_buf_out(5 downto 3);
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PORT2_STAGE <= spi_buf_out(2 downto 0);
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when 7 => SPI_OVERWRITE_ENABLED <= spi_buf_out(15);
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SPI_OVERWRITE_DATA <= spi_buf_out(14 downto 0);
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when 8 => MAX2871_DEF_0(15 downto 0) <= spi_buf_out;
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when 9 => MAX2871_DEF_0(31 downto 16) <= spi_buf_out;
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when 10 => MAX2871_DEF_1(15 downto 0) <= spi_buf_out;
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when 11 => MAX2871_DEF_1(31 downto 16) <= spi_buf_out;
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when 12 => MAX2871_DEF_3(15 downto 0) <= spi_buf_out;
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when 13 => MAX2871_DEF_3(31 downto 16) <= spi_buf_out;
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when 14 => MAX2871_DEF_4(15 downto 0) <= spi_buf_out;
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when 15 => MAX2871_DEF_4(31 downto 16) <= spi_buf_out;
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when 18 => DFT_BIN1_PHASEINC <= spi_buf_out;
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when 19 => DFT_DIFFBIN_PHASEINC <= spi_buf_out;
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when 20 => SETTLING_TIME(15 downto 0) <= spi_buf_out;
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when 21 => SETTLING_TIME(19 downto 16) <= spi_buf_out(3 downto 0);
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when others =>
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end case;
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selected_register <= selected_register + 1;
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when WriteSweepConfig =>
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if word_cnt = 6 then
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-- Sweep config data is complete pass on
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SWEEP_DATA <= sweepconfig_buffer & spi_buf_out;
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sweep_config_write <= '1';
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else
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-- shift next word into buffer
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sweepconfig_buffer <= sweepconfig_buffer(63 downto 0) & spi_buf_out;
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end if;
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when ReadResult =>
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-- pass on next word of latched result
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spi_buf_in <= latched_result(15 downto 0);
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latched_result <= "0000000000000000" & latched_result(287 downto 16);
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when ReadResult =>
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-- pass on next word of latched result
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spi_buf_in <= latched_result(15 downto 0);
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latched_result <= "0000000000000000" & latched_result(287 downto 16);
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when others =>
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end case;
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end if;
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-- handle write operations when the whole word is complete
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if spi_complete = '1' then
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word_cnt <= word_cnt + 1;
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case state is
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when FirstWord =>
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-- initial word determines action
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case spi_buf_out(15 downto 13) is
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when "000" => state <= WriteSweepConfig;
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-- also extract the point number
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SWEEP_ADDRESS <= spi_buf_out(12 downto 0);
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when "001" => state <= FirstWord;
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SWEEP_RESUME <= '1';
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when "011" => state <= FirstWord;
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RESET_MINMAX <= '1';
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when "100" => state <= WriteRegister;
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selected_register <= to_integer(unsigned(spi_buf_out(4 downto 0)));
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-- ignore read options (already handled in other state machine)
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when "010" =>
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when "101" =>
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when "110" =>
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when "111" =>
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when others => state <= FirstWord;
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end case;
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when WriteRegister =>
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-- write received data into previously selected register
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case selected_register is
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when 0 => interrupt_mask <= spi_buf_out;
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when 1 => SWEEP_POINTS <= spi_buf_out(12 downto 0);
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when 2 => NSAMPLES <= spi_buf_out(12 downto 0);
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when 3 => PORTSWITCH_EN <= spi_buf_out(0);
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PORT1_EN <= spi_buf_out(15);
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PORT2_EN <= spi_buf_out(14);
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REF_EN <= spi_buf_out(13);
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AMP_SHDN <= not spi_buf_out(12);
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SOURCE_RF_EN <= spi_buf_out(11);
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LO_RF_EN <= spi_buf_out(10);
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LEDS <= not spi_buf_out(9 downto 7);
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WINDOW_SETTING <= spi_buf_out(6 downto 5);
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SOURCE_CE_EN <= spi_buf_out(4);
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LO_CE_EN <= spi_buf_out(3);
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SYNC_MASTER <= spi_buf_out(1);
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when 4 => ADC_PRESCALER <= spi_buf_out(7 downto 0);
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when 5 => ADC_PHASEINC <= spi_buf_out(11 downto 0);
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when 6 => STAGES <= spi_buf_out(15 downto 13);
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SYNC_ENABLED <= spi_buf_out(12);
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PORT1_STAGE <= spi_buf_out(5 downto 3);
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PORT2_STAGE <= spi_buf_out(2 downto 0);
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when 7 => SPI_OVERWRITE_ENABLED <= spi_buf_out(15);
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SPI_OVERWRITE_DATA <= spi_buf_out(14 downto 0);
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when 8 => MAX2871_DEF_0(15 downto 0) <= spi_buf_out;
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when 9 => MAX2871_DEF_0(31 downto 16) <= spi_buf_out;
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when 10 => MAX2871_DEF_1(15 downto 0) <= spi_buf_out;
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when 11 => MAX2871_DEF_1(31 downto 16) <= spi_buf_out;
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when 12 => MAX2871_DEF_3(15 downto 0) <= spi_buf_out;
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when 13 => MAX2871_DEF_3(31 downto 16) <= spi_buf_out;
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when 14 => MAX2871_DEF_4(15 downto 0) <= spi_buf_out;
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when 15 => MAX2871_DEF_4(31 downto 16) <= spi_buf_out;
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when 18 => DFT_BIN1_PHASEINC <= spi_buf_out;
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when 19 => DFT_DIFFBIN_PHASEINC <= spi_buf_out;
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when 20 => SETTLING_TIME(15 downto 0) <= spi_buf_out;
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when 21 => SETTLING_TIME(19 downto 16) <= spi_buf_out(3 downto 0);
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when others =>
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end case;
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selected_register <= selected_register + 1;
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when WriteSweepConfig =>
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if word_cnt = 6 then
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-- Sweep config data is complete pass on
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SWEEP_DATA <= sweepconfig_buffer & spi_buf_out;
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sweep_config_write <= '1';
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else
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-- shift next word into buffer
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sweepconfig_buffer <= sweepconfig_buffer(63 downto 0) & spi_buf_out;
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end if;
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-- read already handled in pre_complete, ignore
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when ReadResult =>
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end case;
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end if;
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end if;
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end if;
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end if;
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@ -40,7 +40,8 @@ ARCHITECTURE behavior OF Test_SPI IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT spi_slave
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GENERIC(W : integer);
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GENERIC(W : integer;
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PREWIDTH : integer);
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PORT(
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SPI_CLK : IN std_logic;
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MISO : OUT std_logic;
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@ -49,7 +50,9 @@ ARCHITECTURE behavior OF Test_SPI IS
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BUF_OUT : OUT std_logic_vector(W-1 downto 0);
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BUF_IN : IN std_logic_vector(W-1 downto 0);
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CLK : IN std_logic;
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COMPLETE : OUT std_logic
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COMPLETE : OUT std_logic;
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PRE_COMPLETE : out STD_LOGIC;
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PRE_BUF_OUT : out STD_LOGIC_VECTOR (PREWIDTH-1 downto 0)
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);
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END COMPONENT;
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@ -65,6 +68,8 @@ ARCHITECTURE behavior OF Test_SPI IS
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signal MISO : std_logic;
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signal BUF_OUT : std_logic_vector(15 downto 0);
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signal COMPLETE : std_logic;
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signal PRE_COMPLETE : std_logic;
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signal PRE_BUF_OUT : std_logic_vector(2 downto 0);
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-- Clock period definitions
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constant CLK_period : time := 9.765625 ns;
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@ -76,7 +81,7 @@ BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: spi_slave
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GENERIC MAP(W => 16)
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GENERIC MAP(W => 16, PREWIDTH => 3)
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PORT MAP (
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SPI_CLK => SPI_CLK,
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MISO => MISO,
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@ -85,7 +90,9 @@ BEGIN
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BUF_OUT => BUF_OUT,
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BUF_IN => BUF_IN,
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CLK => CLK,
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COMPLETE => COMPLETE
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COMPLETE => COMPLETE,
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PRE_COMPLETE => PRE_COMPLETE,
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PRE_BUF_OUT => PRE_BUF_OUT
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);
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-- Clock process definitions
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@ -293,11 +293,30 @@ BEGIN
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wait for 100 ns;
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RESET <= '0';
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wait for CLK_period*10;
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-- read static test register
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NSS <= '0';
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SPI("0100000000000000");
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SPI("0000000000000000");
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NSS <= '1';
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wait for CLK_period*50;
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-- write register 3 = 0xFFFF (enable all periphery)
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NSS <= '0';
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SPI("1000000000000011");
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SPI("1111111111111111");
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NSS <= '1';
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wait for CLK_period*50;
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-- set sampling result and read first 4 words
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SAMPLING_RESULT(63 downto 0) <= "1111000011110000101010101010101001010101010101010000111100001111";
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NSS <= '0';
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SPI("1100000000000000");
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SPI("0000000000000000");
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SPI("0000000000000000");
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SPI("0000000000000000");
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SPI("0000000000000000");
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NSS <= '1';
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wait for CLK_period*50;
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-- insert stimulus here
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-- write number of points
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@ -137,13 +137,9 @@
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1735841254" xil_pn:in_ck="-3235419683908193302" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1735841254">
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<transform xil_pn:end_ts="1735897915" xil_pn:in_ck="-3235419683908193302" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1735897915">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForInputs"/>
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<status xil_pn:value="OutOfDateForOutputs"/>
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<status xil_pn:value="InputChanged"/>
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<status xil_pn:value="OutputChanged"/>
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<outfile xil_pn:name="DFT.vhd"/>
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<outfile xil_pn:name="MAX2871.vhd"/>
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<outfile xil_pn:name="MCP33131.vhd"/>
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@ -167,15 +163,15 @@
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<outfile xil_pn:name="top.vhd"/>
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<outfile xil_pn:name="window.vhd"/>
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</transform>
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<transform xil_pn:end_ts="1735841278" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="9011583378592605907" xil_pn:start_ts="1735841278">
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<transform xil_pn:end_ts="1735898132" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="9011583378592605907" xil_pn:start_ts="1735898132">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1735841278" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="2919554697640690001" xil_pn:start_ts="1735841278">
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<transform xil_pn:end_ts="1735898132" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="2919554697640690001" xil_pn:start_ts="1735898132">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1735834278" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1735834278">
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<transform xil_pn:end_ts="1735887598" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1735887598">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
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@ -188,14 +184,9 @@
|
|||
<outfile xil_pn:name="ipcore_dir/result_bram.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/result_bram.vhd"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735841254" xil_pn:in_ck="-9185925483828391381" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1735841254">
|
||||
<transform xil_pn:end_ts="1735897915" xil_pn:in_ck="-9185925483828391381" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1735897915">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="DFT.vhd"/>
|
||||
<outfile xil_pn:name="MAX2871.vhd"/>
|
||||
<outfile xil_pn:name="MCP33131.vhd"/>
|
||||
|
|
@ -224,13 +215,10 @@
|
|||
<outfile xil_pn:name="top.vhd"/>
|
||||
<outfile xil_pn:name="window.vhd"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735841280" xil_pn:in_ck="-9185925483828391381" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8439971377188504826" xil_pn:start_ts="1735841278">
|
||||
<transform xil_pn:end_ts="1735898134" xil_pn:in_ck="-9185925483828391381" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8439971377188504826" xil_pn:start_ts="1735898132">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="Test_SPICommands_beh.prj"/>
|
||||
<outfile xil_pn:name="Test_SPICommands_isim_beh.exe"/>
|
||||
|
|
@ -239,10 +227,9 @@
|
|||
<outfile xil_pn:name="isim.log"/>
|
||||
<outfile xil_pn:name="xilinxsim.ini"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735841280" xil_pn:in_ck="4191604156099045257" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-6574364550222252173" xil_pn:start_ts="1735841280">
|
||||
<transform xil_pn:end_ts="1735898134" xil_pn:in_ck="4191604156099045257" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-6574364550222252173" xil_pn:start_ts="1735898134">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="Test_SPICommands_isim_beh.wdb"/>
|
||||
|
|
@ -257,7 +244,7 @@
|
|||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735835257" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1735835257">
|
||||
<transform xil_pn:end_ts="1735889214" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1735889214">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
|
||||
|
|
@ -286,13 +273,11 @@
|
|||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735840845" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1735840834">
|
||||
<transform xil_pn:end_ts="1735898634" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1735898623">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<outfile xil_pn:name="top.lso"/>
|
||||
|
|
@ -306,33 +291,23 @@
|
|||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
<outfile xil_pn:name="xst"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735839469" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1735839469">
|
||||
<transform xil_pn:end_ts="1735898634" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1735898634">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735840849" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1735840845">
|
||||
<transform xil_pn:end_ts="1735898638" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1735898634">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<outfile xil_pn:name="_ngo"/>
|
||||
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
<outfile xil_pn:name="top.bld"/>
|
||||
<outfile xil_pn:name="top.ngd"/>
|
||||
<outfile xil_pn:name="top_ngdbuild.xrpt"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735840960" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1735840849">
|
||||
<transform xil_pn:end_ts="1735898720" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1735898638">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
|
||||
<outfile xil_pn:name="top.pcf"/>
|
||||
<outfile xil_pn:name="top_map.map"/>
|
||||
|
|
@ -343,12 +318,10 @@
|
|||
<outfile xil_pn:name="top_summary.xml"/>
|
||||
<outfile xil_pn:name="top_usage.xml"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735840975" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1735840960">
|
||||
<transform xil_pn:end_ts="1735898743" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1735898720">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
|
||||
<outfile xil_pn:name="top.ncd"/>
|
||||
<outfile xil_pn:name="top.pad"/>
|
||||
|
|
@ -360,10 +333,9 @@
|
|||
<outfile xil_pn:name="top_pad.txt"/>
|
||||
<outfile xil_pn:name="top_par.xrpt"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735840985" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1735840975">
|
||||
<transform xil_pn:end_ts="1735898752" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1735898743">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
|
||||
<outfile xil_pn:name="top.bgn"/>
|
||||
<outfile xil_pn:name="top.bin"/>
|
||||
|
|
@ -378,7 +350,6 @@
|
|||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
|
|
@ -389,7 +360,6 @@
|
|||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
|
|
@ -401,7 +371,6 @@
|
|||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
|
|
@ -413,17 +382,14 @@
|
|||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735840975" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1735840971">
|
||||
<transform xil_pn:end_ts="1735898743" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1735898738">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
<outfile xil_pn:name="top.twr"/>
|
||||
<outfile xil_pn:name="top.twx"/>
|
||||
|
|
|
|||
|
|
@ -31,7 +31,8 @@ use IEEE.numeric_std.all;
|
|||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity spi_slave is
|
||||
generic ( W : integer);
|
||||
generic ( W : integer;
|
||||
PREWIDTH : integer);
|
||||
Port ( SPI_CLK : in STD_LOGIC;
|
||||
MISO : out STD_LOGIC;
|
||||
MOSI : in STD_LOGIC;
|
||||
|
|
@ -39,9 +40,12 @@ entity spi_slave is
|
|||
BUF_OUT : out STD_LOGIC_VECTOR (W-1 downto 0) := (others => '0');
|
||||
BUF_IN : in STD_LOGIC_VECTOR (W-1 downto 0);
|
||||
CLK : in STD_LOGIC;
|
||||
COMPLETE : out STD_LOGIC
|
||||
-- RISING_TOGGLE : inout STD_LOGIC;
|
||||
-- FALLING_TOGGLE : inout STD_LOGIC
|
||||
COMPLETE : out STD_LOGIC;
|
||||
-- processing the complete word after it is complete leaves very little time
|
||||
-- for read operations. Indicate when the first PREWIDTH bits are ready which
|
||||
-- allows more time to prepare the response to the next word
|
||||
PRE_COMPLETE : out STD_LOGIC;
|
||||
PRE_BUF_OUT : out STD_LOGIC_VECTOR (PREWIDTH-1 downto 0) := (others => '0')
|
||||
);
|
||||
end spi_slave;
|
||||
|
||||
|
|
@ -52,6 +56,8 @@ architecture Behavioral of spi_slave is
|
|||
signal data_valid : STD_LOGIC_VECTOR(2 downto 0);
|
||||
signal data_synced : STD_LOGIC_VECTOR(2 downto 0);
|
||||
signal data : STD_LOGIC_VECTOR(W-1 downto 0);
|
||||
signal pre_data : STD_LOGIC_VECTOR(PREWIDTH-1 downto 0);
|
||||
signal pre_data_valid : STD_LOGIC_VECTOR(3 downto 0);
|
||||
|
||||
signal bit_cnt : integer range 0 to W-1;
|
||||
begin
|
||||
|
|
@ -59,9 +65,11 @@ begin
|
|||
process(CLK)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
data_valid(2 downto 1) <= data_valid(1 downto 0);
|
||||
COMPLETE <= '0';
|
||||
if data_valid(1) = '1' then
|
||||
PRE_COMPLETE <= '0';
|
||||
data_valid(2 downto 1) <= data_valid(1 downto 0);
|
||||
pre_data_valid(3 downto 1) <= pre_data_valid(2 downto 0);
|
||||
if data_valid(2) = '1' then
|
||||
if data_synced(0) = '0' then
|
||||
BUF_OUT <= data;
|
||||
COMPLETE <= '1';
|
||||
|
|
@ -70,19 +78,33 @@ begin
|
|||
else
|
||||
data_synced(0) <= '0';
|
||||
end if;
|
||||
if pre_data_valid(3 downto 2) = "01" then
|
||||
-- pre_data has just become valid
|
||||
PRE_BUF_OUT <= pre_data;
|
||||
PRE_COMPLETE <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--MISO <= BUF_IN(W - 1 - bit_cnt);-- when bit_cnt = 0 else miso_buffer(W-2);
|
||||
MISO <= BUF_IN(15) when bit_cnt = 0 else miso_buffer(W-2);
|
||||
|
||||
slave_in: process(SPI_CLK)
|
||||
slave_in: process(SPI_CLK, CS)
|
||||
begin
|
||||
if rising_edge(SPI_CLK) then
|
||||
-- FALLING_TOGGLE <= not FALLING_TOGGLE;
|
||||
if CS = '1' then
|
||||
bit_cnt <= 0;
|
||||
data_valid(0) <= '0';
|
||||
pre_data_valid(0) <= '0';
|
||||
elsif rising_edge(SPI_CLK) then
|
||||
-- data input process: sample on the rising edge
|
||||
data_synced(2 downto 1) <= data_synced(1 downto 0);
|
||||
if bit_cnt = PREWIDTH-1 then
|
||||
-- first couple of bits are ready
|
||||
pre_data <= mosi_buffer(PREWIDTH-2 downto 0) & MOSI;
|
||||
pre_data_valid(0) <= '1';
|
||||
end if;
|
||||
if bit_cnt = W-1 then
|
||||
-- this was the last bit
|
||||
pre_data_valid(0) <= '0';
|
||||
data_valid(0) <= '1';
|
||||
data <= mosi_buffer(W-2 downto 0) & MOSI;
|
||||
else
|
||||
|
|
@ -91,14 +113,9 @@ begin
|
|||
end if;
|
||||
mosi_buffer <= mosi_buffer(W-3 downto 0) & MOSI;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
slave_out: process(SPI_CLK, CS, BUF_IN, bit_cnt)
|
||||
begin
|
||||
if CS = '1' then
|
||||
bit_cnt <= 0;
|
||||
elsif falling_edge(SPI_CLK) then
|
||||
|
||||
-- data output process: data should be launched on the falling edge
|
||||
-- but the delay is too large. Launch on the rising edge instead
|
||||
if bit_cnt < W-1 then
|
||||
bit_cnt <= bit_cnt + 1;
|
||||
if bit_cnt = 0 then
|
||||
|
|
@ -108,9 +125,27 @@ begin
|
|||
end if;
|
||||
else
|
||||
bit_cnt <= 0;
|
||||
--miso_buffer <= BUF_IN;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- slave_out: process(SPI_CLK, CS, BUF_IN, bit_cnt)
|
||||
-- begin
|
||||
-- if CS = '1' then
|
||||
-- bit_cnt <= 0;
|
||||
-- elsif falling_edge(SPI_CLK) then
|
||||
-- if bit_cnt < W-1 then
|
||||
-- bit_cnt <= bit_cnt + 1;
|
||||
-- if bit_cnt = 0 then
|
||||
-- miso_buffer <= BUF_IN;
|
||||
-- else
|
||||
-- miso_buffer <= miso_buffer(W-2 downto 0) & '0';
|
||||
-- end if;
|
||||
-- else
|
||||
-- bit_cnt <= 0;
|
||||
-- --miso_buffer <= BUF_IN;
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
end Behavioral;
|
||||
BIN
FPGA/VNA/top.bin
BIN
FPGA/VNA/top.bin
Binary file not shown.
|
|
@ -1,9 +1,23 @@
|
|||
CONFIG VCCAUX = 3.3;
|
||||
# Global FPGA clock
|
||||
NET "CLK" PERIOD = 62.5 ns HIGH 50%;
|
||||
|
||||
# Constraints for SPI interface to MCU
|
||||
NET "MCU_SCK" PERIOD = 23.52941176ns HIGH 50%;
|
||||
NET "MCU_MOSI" OFFSET = IN 2ns VALID 3ns BEFORE "MCU_SCK";
|
||||
NET "MCU_MISO" OFFSET = OUT 18.529ns VALID 10ns AFTER "MCU_SCK";
|
||||
NET "MCU_MISO" SLEW = FAST;
|
||||
|
||||
# ADC constraints
|
||||
NET "REF_SCLK" PERIOD = 19.5ns HIGH 50%;
|
||||
NET "REF_SDO" OFFSET = IN 9ns VALID 9ns BEFORE "REF_SCLK";
|
||||
NET "PORT1_SCLK" PERIOD = 19.5ns HIGH 50%;
|
||||
NET "PORT1_SDO" OFFSET = IN 9ns VALID 9ns BEFORE "PORT1_SCLK";
|
||||
NET "PORT2_SCLK" PERIOD = 19.5ns HIGH 50%;
|
||||
NET "PORT2_SDO" OFFSET = IN 9ns VALID 9ns BEFORE "PORT2_SCLK";
|
||||
NET "PORT1_SCLK" SLEW = FAST;
|
||||
NET "PORT2_SCLK" SLEW = FAST;
|
||||
NET "REF_SCLK" SLEW = FAST;
|
||||
|
||||
NET "ATTENUATION[6]" IOSTANDARD = LVCMOS33;
|
||||
NET "ATTENUATION[5]" IOSTANDARD = LVCMOS33;
|
||||
|
|
@ -63,10 +77,6 @@ NET "MCU_AUX3" IOSTANDARD = LVCMOS33;
|
|||
NET "TRIGGER_IN" IOSTANDARD = LVCMOS33;
|
||||
NET "TRIGGER_OUT" IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET "PORT1_SCLK" SLEW = FAST;
|
||||
NET "PORT2_SCLK" SLEW = FAST;
|
||||
NET "REF_SCLK" SLEW = FAST;
|
||||
|
||||
NET "ATTENUATION[6]" LOC = P9;
|
||||
NET "ATTENUATION[5]" LOC = P10;
|
||||
NET "ATTENUATION[4]" LOC = P11;
|
||||
|
|
|
|||
|
|
@ -562,7 +562,7 @@ begin
|
|||
|
||||
|
||||
Source: MAX2871
|
||||
GENERIC MAP(CLK_DIV => 10)
|
||||
GENERIC MAP(CLK_DIV => 6)
|
||||
PORT MAP(
|
||||
CLK => clk_pll,
|
||||
RESET => int_reset,
|
||||
|
|
@ -577,7 +577,7 @@ begin
|
|||
DONE => source_reloaded
|
||||
);
|
||||
LO1: MAX2871
|
||||
GENERIC MAP(CLK_DIV => 10)
|
||||
GENERIC MAP(CLK_DIV => 6)
|
||||
PORT MAP(
|
||||
CLK => clk_pll,
|
||||
RESET => int_reset,
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue