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wait for lock on Si5351C

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This commit is contained in:
Jan Käberich 2022-11-17 12:05:52 +01:00
parent aeaf9340d3
commit a4b1978098
4 changed files with 20 additions and 4 deletions
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4
Software/VNA_embedded/Application/Hardware.cpp
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@ -133,7 +133,9 @@ bool HW::Init() {
// PLL reset appears to realign phases of clock signals
Si5351.ResetPLL(Si5351C::PLL::B);
LOG_DEBUG("Si5351 locked");
if(Si5351.WaitForLock(Si5351C::PLL::B, 10)) {
LOG_DEBUG("Si5351 locked");
}
// FPGA clock is now present, can initialize
if (!FPGA::Init(HaltedCallback)) {