WIP: rework 2.LO + add dwell time

Documentation/DeveloperInfo/FPGA_protocol.tex

@@ -13,6 +13,7 @@
 {geometry}
 \usepackage{tikz}
 \usepackage{siunitx} 
+\usepackage{minibox}
 \DeclareSIUnit{\belmilliwatt}{Bm}
 \DeclareSIUnit{\dBm}{\deci\belmilliwatt}
 
@@ -534,6 +535,26 @@ $$ f_{firstBin} =  \frac{SR_{ADC} * DFT\_FIRST\_BIN}{2^{16}}$$
 $$ \Delta f =  \frac{SR_{ADC} * DFT\_FREQ\_SPACING}{2^{24}}$$
 \end{itemize}
 
+\subsection{SETTLING\_TIME: 0x14}
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{16}{SETTLING\_TIME[15:0]}
+\end{tikzpicture}
+\end{center}
+\begin{itemize}
+\item \textbf{SETTLING\_TIME[19:0]:} This value determines the time delay between applying the stimulus signal and the beginning of the ADC sampling.
+$$ t_{delay} =  \frac{1}{\SI{102.4}{\mega\hertz}} SETTLING\_TIME $$
+\end{itemize}
+\subsection{SETTLING\_TIME: 0x15}
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\robits{0}{12}{reserved}
+\rwbits{12}{4}{SETTLING\_TIME[19:16]}
+\end{tikzpicture}
+\end{center}
+
 \section{SweepConfig}
 \label{sweepconfig}
 The SweepConfig contains data for the source and LO1 PLL as well as the attenuator and source filter. Each point in the sweep, needs a valid SweepConfig before the sweep is started.
@@ -542,7 +563,9 @@ The SweepConfig contains data for the source and LO1 PLL as well as the attenuat
 \begin{tikzpicture}
 \bitrect{16}{96-\bit}
 \rwbits{0}{1}{HS}
-\rwbits{1}{2}{SettlingTime}
+%\rwbits{1}{2}{SettlingTime}
+\rwbits{1}{1}{\tiny LO N[6]}
+\rwbits{2}{1}{\minibox{\tiny Source\\N[6]}}
 \rwbits{3}{3}{Samples}
 \rwbits{6}{2}{SourceFilter}
 \rwbits{8}{8}{LO M[11:4]}
@@ -580,17 +603,17 @@ The SweepConfig contains data for the source and LO1 PLL as well as the attenuat
 \end{center}
 \begin{itemize}
 \item \textbf{HS: Halt sweep.} If set, settling and sampling of this sweep point will be postponed until the sweep resume command is issued.
-\item \textbf{SettlingTime:} Amount of time between locking of PLLs and beginning of ADC sampling
+%\item \textbf{SettlingTime:} Amount of time between locking of PLLs and beginning of ADC sampling
-\begin{center}
+%\begin{center}
-\begin{tabular}{ c|c }
+%\begin{tabular}{ c|c }
-Setting & Time\\
+%Setting & Time\\
- \hline
+ %\hline
-00 & \SI{20}{\micro\second}\\
+%00 & \SI{20}{\micro\second}\\
-01 & \SI{60}{\micro\second}\\
+%01 & \SI{60}{\micro\second}\\
-10 & \SI{180}{\micro\second}\\
+%10 & \SI{180}{\micro\second}\\
-11 & \SI{540}{\micro\second}\\
+%11 & \SI{540}{\micro\second}\\
-\end{tabular}
+%\end{tabular}
-\end{center}
+%\end{center}
 \item \textbf{Samples:} Number of ADC samples to take
 \begin{center}
 \begin{tabular}{ c|c|c }

FPGA/VNA/MCP33131.vhd

@@ -53,6 +53,8 @@ architecture Behavioral of MCP33131 is
 	signal adc_data : std_logic_vector(15 downto 0);
 	type States is (Idle, Conversion, WAIT_tEN, Transmission, Done);
 	signal state : States;
+	signal ready_int : std_logic;
+	signal ready_delay : integer range 0 to 30;
 	signal min_int, max_int, data_int : signed(15 downto 0);
 begin
 
@@ -61,7 +63,7 @@ begin
 	DATA <= std_logic_vector(data_int);
 	SCLK <= sclk_phase;
 
-	process(SCLK)
+	process(SCLK, START)
 	begin
 		if(falling_edge(SCLK)) then
 			adc_data <= adc_data(14 downto 0) & SDO;
@@ -74,6 +76,7 @@ begin
 			if(RESET = '1') then
 				state <= Idle;
 				READY <= '0';
+				ready_int <= '0';
 				CONVSTART <= '0';
 				sclk_phase <= '0';
 				CONVSTART <= '0';
@@ -94,16 +97,30 @@ begin
 						max_int <= data_int;
 					end if;
 				end if;
+				
+				READY <= '0';
+				if ready_int = '1' then
+					ready_delay <= 3;
+				else
+					if ready_delay > 0 then
+						ready_delay <= ready_delay - 1;
+					end if;
+					if ready_delay = 1 then
+						READY <= '1';
+						data_int <= signed(adc_data);
+					end if;
+				end if;
+				
 				case state is
 					when Idle =>
-						READY <= '0';
+						ready_int <= '0';
-						bit_cnt <= 0;
 						if START = '1' then
 							state <= Conversion;
 							conv_cnt <= 0;
 							CONVSTART <= '1';
 						end if;
 					when Conversion =>
+						ready_int <= '0';
 						if(conv_cnt < CONVCYCLES-1) then
 							conv_cnt <= conv_cnt + 1;
 						else
@@ -112,8 +129,10 @@ begin
 							state <= WAIT_tEN;
 						end if;
 					when WAIT_tEN =>
+						ready_int <= '0';
 						state <= Transmission;
 					when Transmission =>
+						ready_int <= '0';
 						if(div_cnt < (CLK_DIV/2)-1) then
 							div_cnt <= div_cnt + 1;
 						else
@@ -123,6 +142,7 @@ begin
 								sclk_phase <= '0';
 								if bit_cnt = 15 then
 									state <= Done;
+									bit_cnt <= 0;
 								else
 									bit_cnt <= bit_cnt + 1;
 								end if;
@@ -130,8 +150,7 @@ begin
 							div_cnt <= 0;
 						end if;
 					when Done =>
-						data_int <= signed(adc_data);
+						ready_int <= '1';
-						READY <= '1';
 						state <= Idle;
 				end case;
 			end if;

FPGA/VNA/SPIConfig.vhd

@@ -51,6 +51,7 @@ entity SPICommands is
            SWEEP_POINTS : out  STD_LOGIC_VECTOR (12 downto 0);
            NSAMPLES : out  STD_LOGIC_VECTOR (12 downto 0);
 			  STAGES : out STD_LOGIC_VECTOR (2 downto 0);
+			  SETTLING_TIME : out STD_LOGIC_VECTOR (19 downto 0);
 			  SYNC_ENABLED : out STD_LOGIC;
 			  SYNC_MASTER : out STD_LOGIC;
 			  PORT1_STAGE : out STD_LOGIC_VECTOR (2 downto 0);
@@ -270,6 +271,8 @@ begin
 							when 15 => MAX2871_DEF_4(31 downto 16) <= spi_buf_out;
 							when 18 => DFT_BIN1_PHASEINC <= spi_buf_out;
 							when 19 => DFT_DIFFBIN_PHASEINC <= spi_buf_out;
+							when 20 => SETTLING_TIME(15 downto 0) <= spi_buf_out;
+							when 21 => SETTLING_TIME(19 downto 16) <= spi_buf_out(3 downto 0);
 							when others => 
 						end case;
 						selected_register <= selected_register + 1;

FPGA/VNA/Sweep.vhd

@@ -37,6 +37,7 @@ entity Sweep is
            CONFIG_DATA : in  STD_LOGIC_VECTOR (95 downto 0);
 			  USER_NSAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
 			  NSAMPLES : out STD_LOGIC_VECTOR (12 downto 0);
+			  SETTLING_TIME : in STD_LOGIC_VECTOR (19 downto 0);
            SAMPLING_BUSY : in STD_LOGIC;
 			  SAMPLING_DONE : in  STD_LOGIC;
 			  START_SAMPLING : out STD_LOGIC;
@@ -92,8 +93,7 @@ architecture Behavioral of Sweep is
 	signal point_cnt : unsigned(12 downto 0);
 	type Point_states is (WaitInitialLow, TriggerSetup, SettingUp, Settling, WaitTriggerHigh, Exciting, WaitTriggerLow, SamplingDone, NextPoint, Done);
 	signal state : Point_states;
-	signal settling_cnt : unsigned(15 downto 0);
+	signal settling_cnt : unsigned(19 downto 0);
-	signal settling_time : unsigned(15 downto 0);
 	signal stage_cnt : unsigned (2 downto 0);
 	signal config_reg : std_logic_vector(95 downto 0);
 	signal source_active : std_logic;
@@ -103,7 +103,7 @@ begin
 	
 	-- assemble registers
 	-- source register 0: N divider and fractional division value
-	SOURCE_REG_0 <= MAX2871_DEF_0(31) & "0000000000" & config_reg(5 downto 0) & config_reg(26 downto 15) & "000";
+	SOURCE_REG_0 <= MAX2871_DEF_0(31) & "000000000" & config_reg(93) & config_reg(5 downto 0) & config_reg(26 downto 15) & "000";
 	-- source register 1: Modulus value
 	SOURCE_REG_1 <= MAX2871_DEF_1(31 downto 15) & config_reg(38 downto 27) & "001";
 	-- source register 3: VCO selection
@@ -112,7 +112,7 @@ begin
 	SOURCE_REG_4 <= MAX2871_DEF_4(31 downto 23) & config_reg(14 downto 12) & MAX2871_DEF_4(19 downto 9) & "000" & MAX2871_DEF_4(5) & config_reg(47 downto 46) & "100";
 	
 	-- LO register 0: N divider and fractional division value
-	LO_REG_0 <= MAX2871_DEF_0(31) & "0000000000" & config_reg(54 downto 49) & config_reg(75 downto 64) & "000";
+	LO_REG_0 <= MAX2871_DEF_0(31) & "000000000" & config_reg(94) & config_reg(54 downto 49) & config_reg(75 downto 64) & "000";
 	-- LO register 1: Modulus value
 	LO_REG_1 <= MAX2871_DEF_1(31 downto 15) & config_reg(87 downto 76) & "001";
 	-- LO register 3: VCO selection
@@ -184,13 +184,7 @@ begin
 						-- highest bit in config_reg determines whether the sweep should be halted prior to sampling
 						SWEEP_HALTED <= config_reg(95);
 						RELOAD_PLL_REGS <= '0';
-						case config_reg(94 downto 93) is 
+						settling_cnt <= unsigned(SETTLING_TIME);
-							when "00" => settling_time <= to_unsigned(2048, 16); -- 20us
-							when "01" => settling_time <= to_unsigned(6144, 16); -- 60us
-							when "10" => settling_time <= to_unsigned(18432, 16); -- 180us
-							when others => settling_time <= to_unsigned(55296, 16); -- 540us
-						end case;
-						settling_cnt <= settling_time;
 						if PLL_RELOAD_DONE = '1' and PLL_LOCKED = '1' then
 							-- check if halted sweep is resumed
 							if config_reg(95) = '0' or SWEEP_RESUME = '1' then
@@ -257,7 +251,7 @@ begin
 						else
 							state <= NextPoint;
 						end if;
-						settling_cnt <= settling_time;
+						settling_cnt <= unsigned(SETTLING_TIME);
 					when NextPoint =>
 						NEW_DATA <= '0';
 						if point_cnt < unsigned(NPOINTS) then

FPGA/VNA/Test_SPI.vhd

@@ -67,8 +67,8 @@ ARCHITECTURE behavior OF Test_SPI IS
    signal COMPLETE : std_logic;
 
    -- Clock period definitions
-   constant CLK_period : time := 10 ns;
+   constant CLK_period : time := 9.765625 ns;
-   constant SPI_CLK_period : time := 100 ns;
+   constant SPI_CLK_period : time := 25 ns;
  
  	signal data_signal : std_logic_vector(15 downto 0);
 

FPGA/VNA/Test_SPICommands.vhd

@@ -41,33 +41,63 @@ ARCHITECTURE behavior OF Test_SPICommands IS
  
     COMPONENT SPICommands
     PORT(
-         CLK : IN  std_logic;
+         CLK : in  STD_LOGIC;
-         RESET : IN  std_logic;
+           RESET : in  STD_LOGIC;
-         SCLK : IN  std_logic;
+           SCLK : in  STD_LOGIC;
-         MOSI : IN  std_logic;
+           MOSI : in  STD_LOGIC;
-         MISO : OUT  std_logic;
+           MISO : out  STD_LOGIC;
-         NSS : IN  std_logic;
+           NSS : in  STD_LOGIC;
-         NEW_SAMPLING_DATA : IN  std_logic;
+           NEW_SAMPLING_DATA : in  STD_LOGIC;
-         SAMPLING_RESULT : IN  std_logic_vector(303 downto 0);
+           SAMPLING_RESULT : in  STD_LOGIC_VECTOR (303 downto 0);
-         SOURCE_UNLOCKED : IN  std_logic;
+			  ADC_MINMAX : in STD_LOGIC_VECTOR(95 downto 0);
-         LO_UNLOCKED : IN  std_logic;
+           SOURCE_UNLOCKED : in  STD_LOGIC;
-         MAX2871_DEF_4 : OUT  std_logic_vector(31 downto 0);
+           LO_UNLOCKED : in  STD_LOGIC;
-         MAX2871_DEF_3 : OUT  std_logic_vector(31 downto 0);
+           MAX2871_DEF_4 : out  STD_LOGIC_VECTOR (31 downto 0);
-         MAX2871_DEF_1 : OUT  std_logic_vector(31 downto 0);
+           MAX2871_DEF_3 : out  STD_LOGIC_VECTOR (31 downto 0);
-         MAX2871_DEF_0 : OUT  std_logic_vector(31 downto 0);
+           MAX2871_DEF_1 : out  STD_LOGIC_VECTOR (31 downto 0);
-         SWEEP_DATA : OUT  std_logic_vector(95 downto 0);
+           MAX2871_DEF_0 : out  STD_LOGIC_VECTOR (31 downto 0);
-         SWEEP_ADDRESS : OUT  std_logic_vector(12 downto 0);
+           SWEEP_DATA : out  STD_LOGIC_VECTOR (95 downto 0);
-         SWEEP_WRITE : OUT  std_logic_vector(0 downto 0);
+           SWEEP_ADDRESS : out  STD_LOGIC_VECTOR (12 downto 0);
-         SWEEP_POINTS : OUT  std_logic_vector(12 downto 0);
+           SWEEP_WRITE : out  STD_LOGIC_VECTOR (0 downto 0);
-         NSAMPLES : OUT  std_logic_vector(12 downto 0);
+           SWEEP_POINTS : out  STD_LOGIC_VECTOR (12 downto 0);
-         PORT1_EN : OUT  std_logic;
+           NSAMPLES : out  STD_LOGIC_VECTOR (12 downto 0);
-         PORT2_EN : OUT  std_logic;
+			  STAGES : out STD_LOGIC_VECTOR (2 downto 0);
-         REF_EN : OUT  std_logic;
+			  SETTLING_TIME : out STD_LOGIC_VECTOR (19 downto 0);
-         AMP_SHDN : OUT  std_logic;
+			  SYNC_ENABLED : out STD_LOGIC;
-         SOURCE_RF_EN : OUT  std_logic;
+			  SYNC_MASTER : out STD_LOGIC;
-         LO_RF_EN : OUT  std_logic;
+			  PORT1_STAGE : out STD_LOGIC_VECTOR (2 downto 0);
-         LEDS : OUT  std_logic_vector(2 downto 0);
+			  PORT2_STAGE : out STD_LOGIC_VECTOR (2 downto 0);
-         INTERRUPT_ASSERTED : OUT  std_logic
+			  PORT1_EN : out STD_LOGIC;
+			  PORT2_EN : out STD_LOGIC;
+			  REF_EN : out STD_LOGIC;
+			  AMP_SHDN : out STD_LOGIC;
+			  SOURCE_RF_EN : out STD_LOGIC;
+			  LO_RF_EN : out STD_LOGIC;
+			  SOURCE_CE_EN : out STD_LOGIC;
+			  LO_CE_EN : out STD_LOGIC;
+			  PORTSWITCH_EN : out STD_LOGIC;
+			  LEDS : out STD_LOGIC_VECTOR(2 downto 0);
+			  WINDOW_SETTING : out STD_LOGIC_VECTOR(1 downto 0);
+			  ADC_PRESCALER : out STD_LOGIC_VECTOR(7 downto 0);
+			  ADC_PHASEINC : out STD_LOGIC_VECTOR(11 downto 0);
+			  INTERRUPT_ASSERTED : out STD_LOGIC;
+			  RESET_MINMAX : out STD_LOGIC;
+			  SWEEP_HALTED : in STD_LOGIC;
+			  SWEEP_RESUME : out STD_LOGIC;
+			  
+			  -- hardware overwrite signals
+			  SPI_OVERWRITE_ENABLED : out STD_LOGIC;
+			  SPI_OVERWRITE_DATA : out STD_LOGIC_VECTOR(14 downto 0);
+			  
+			  -- DFT signals
+			  DFT_BIN1_PHASEINC : out  STD_LOGIC_VECTOR (15 downto 0);
+           DFT_DIFFBIN_PHASEINC : out  STD_LOGIC_VECTOR (15 downto 0);
+			  DFT_RESULT_READY : in  STD_LOGIC;
+           DFT_OUTPUT : in  STD_LOGIC_VECTOR (191 downto 0);
+           DFT_NEXT_OUTPUT : out  STD_LOGIC;
+			  DFT_ENABLE : out STD_LOGIC;
+			  			  
+			  DEBUG_STATUS : in STD_LOGIC_VECTOR(10 downto 0)
         );
     END COMPONENT;
     
@@ -104,8 +134,8 @@ ARCHITECTURE behavior OF Test_SPICommands IS
    signal INTERRUPT_ASSERTED : std_logic;
 
    -- Clock period definitions
-   constant CLK_period : time := 6.25 ns;
+   constant CLK_period : time := 9.765625 ns;
-	constant SPI_CLK_period : time := 100 ns;
+	constant SPI_CLK_period : time := 23.52941176 ns;
 	
 	signal data_signal : std_logic_vector(15 downto 0);
 BEGIN
@@ -120,6 +150,7 @@ BEGIN
           NSS => NSS,
           NEW_SAMPLING_DATA => NEW_SAMPLING_DATA,
           SAMPLING_RESULT => SAMPLING_RESULT,
+			 ADC_MINMAX => (others => '0'),
           SOURCE_UNLOCKED => SOURCE_UNLOCKED,
           LO_UNLOCKED => LO_UNLOCKED,
           MAX2871_DEF_4 => MAX2871_DEF_4,
@@ -138,7 +169,11 @@ BEGIN
           SOURCE_RF_EN => SOURCE_RF_EN,
           LO_RF_EN => LO_RF_EN,
           LEDS => LEDS,
-          INTERRUPT_ASSERTED => INTERRUPT_ASSERTED
+          INTERRUPT_ASSERTED => INTERRUPT_ASSERTED,
+			 SWEEP_HALTED => '0',
+			 DFT_RESULT_READY => '0',
+			 DFT_OUTPUT => (others => '0'),
+			 DEBUG_STATUS => (others => '0')
         );
 
    -- Clock process definitions
@@ -259,7 +294,7 @@ BEGIN
 		RESET <= '0';
       wait for CLK_period*10;
 		NSS <= '0';
-		SPI("1100000000000000");
+		SPI("0100000000000000");
 		SPI("0000000000000000");
 		NSS <= '1';
 		

FPGA/VNA/VNA.gise

@@ -41,11 +41,11 @@
     <file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Synchronizer.vhi"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_DFT_isim_beh.exe"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MAX2871_isim_beh.exe"/>
-    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_MCP33131_beh.prj"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MCP33131_isim_beh.exe"/>
-    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_MCP33131_isim_beh.wdb"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_PLL_isim_beh.exe"/>
+    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_SPICommands_beh.prj"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPICommands_isim_beh.exe"/>
+    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_SPICommands_isim_beh.wdb"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPI_isim_beh.exe"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sampling_isim_beh.exe"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SinCos_isim_beh.exe"/>
@@ -137,7 +137,7 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1708955295" xil_pn:in_ck="-3235419683908193302" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1708955295">
+    <transform xil_pn:end_ts="1735841254" xil_pn:in_ck="-3235419683908193302" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1735841254">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
@@ -167,15 +167,15 @@
       <outfile xil_pn:name="top.vhd"/>
       <outfile xil_pn:name="window.vhd"/>
     </transform>
-    <transform xil_pn:end_ts="1708955295" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-1206566934435318832" xil_pn:start_ts="1708955295">
+    <transform xil_pn:end_ts="1735841278" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="9011583378592605907" xil_pn:start_ts="1735841278">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1708955295" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-273551377395144626" xil_pn:start_ts="1708955295">
+    <transform xil_pn:end_ts="1735841278" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="2919554697640690001" xil_pn:start_ts="1735841278">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1708955295" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1708955295">
+    <transform xil_pn:end_ts="1735834278" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1735834278">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
@@ -188,7 +188,7 @@
       <outfile xil_pn:name="ipcore_dir/result_bram.ngc"/>
       <outfile xil_pn:name="ipcore_dir/result_bram.vhd"/>
     </transform>
-    <transform xil_pn:end_ts="1708955295" xil_pn:in_ck="-9185925483828391381" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1708955295">
+    <transform xil_pn:end_ts="1735841254" xil_pn:in_ck="-9185925483828391381" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1735841254">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
@@ -224,7 +224,7 @@
       <outfile xil_pn:name="top.vhd"/>
       <outfile xil_pn:name="window.vhd"/>
     </transform>
-    <transform xil_pn:end_ts="1708955298" xil_pn:in_ck="-9185925483828391381" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-3530939538078141760" xil_pn:start_ts="1708955295">
+    <transform xil_pn:end_ts="1735841280" xil_pn:in_ck="-9185925483828391381" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8439971377188504826" xil_pn:start_ts="1735841278">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
@@ -232,32 +232,32 @@
       <status xil_pn:value="OutOfDateForOutputs"/>
       <status xil_pn:value="InputChanged"/>
       <status xil_pn:value="OutputChanged"/>
-      <outfile xil_pn:name="Test_MCP33131_beh.prj"/>
+      <outfile xil_pn:name="Test_SPICommands_beh.prj"/>
-      <outfile xil_pn:name="Test_MCP33131_isim_beh.exe"/>
+      <outfile xil_pn:name="Test_SPICommands_isim_beh.exe"/>
       <outfile xil_pn:name="fuse.log"/>
       <outfile xil_pn:name="isim"/>
       <outfile xil_pn:name="isim.log"/>
       <outfile xil_pn:name="xilinxsim.ini"/>
     </transform>
-    <transform xil_pn:end_ts="1708955298" xil_pn:in_ck="4191604156099045257" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="6352116336892055917" xil_pn:start_ts="1708955298">
+    <transform xil_pn:end_ts="1735841280" xil_pn:in_ck="4191604156099045257" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-6574364550222252173" xil_pn:start_ts="1735841280">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForPredecessor"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
       <status xil_pn:value="OutputChanged"/>
-      <outfile xil_pn:name="Test_MCP33131_isim_beh.wdb"/>
+      <outfile xil_pn:name="Test_SPICommands_isim_beh.wdb"/>
       <outfile xil_pn:name="isim.cmd"/>
       <outfile xil_pn:name="isim.log"/>
     </transform>
-    <transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1600270761">
+    <transform xil_pn:end_ts="1735835257" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1735835257">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6623951845608321876" xil_pn:start_ts="1600270761">
+    <transform xil_pn:end_ts="1735835257" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6623951845608321876" xil_pn:start_ts="1735835257">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1708953094" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1708953094">
+    <transform xil_pn:end_ts="1735835257" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1735835257">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
@@ -270,27 +270,29 @@
       <outfile xil_pn:name="ipcore_dir/result_bram.ngc"/>
       <outfile xil_pn:name="ipcore_dir/result_bram.vhd"/>
     </transform>
-    <transform xil_pn:end_ts="1600270761" xil_pn:in_ck="277585929807082169" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1600270761">
+    <transform xil_pn:end_ts="1735835257" xil_pn:in_ck="-2664127494180108140" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1735835257">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-9042377951913232490" xil_pn:start_ts="1600270761">
+    <transform xil_pn:end_ts="1735835257" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-9042377951913232490" xil_pn:start_ts="1735835257">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1600270761" xil_pn:in_ck="277585929807082169" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1600270761">
+    <transform xil_pn:end_ts="1735835257" xil_pn:in_ck="-2664127494180108140" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1735835257">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="6527189854873920525" xil_pn:start_ts="1600270761">
+    <transform xil_pn:end_ts="1735835257" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="6527189854873920525" xil_pn:start_ts="1735835257">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1708958126" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1708958116">
+    <transform xil_pn:end_ts="1735840845" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1735840834">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="InputChanged"/>
       <status xil_pn:value="OutputChanged"/>
       <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
       <outfile xil_pn:name="top.lso"/>
@@ -304,23 +306,33 @@
       <outfile xil_pn:name="webtalk_pn.xml"/>
       <outfile xil_pn:name="xst"/>
     </transform>
-    <transform xil_pn:end_ts="1708952937" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1708952937">
+    <transform xil_pn:end_ts="1735839469" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1735839469">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="InputChanged"/>
     </transform>
-    <transform xil_pn:end_ts="1708958131" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1708958126">
+    <transform xil_pn:end_ts="1735840849" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1735840845">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
+      <status xil_pn:value="InputChanged"/>
       <outfile xil_pn:name="_ngo"/>
       <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
       <outfile xil_pn:name="top.bld"/>
       <outfile xil_pn:name="top.ngd"/>
       <outfile xil_pn:name="top_ngdbuild.xrpt"/>
     </transform>
-    <transform xil_pn:end_ts="1708958154" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1708958131">
+    <transform xil_pn:end_ts="1735840960" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1735840849">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="InputChanged"/>
+      <status xil_pn:value="OutputChanged"/>
       <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
       <outfile xil_pn:name="top.pcf"/>
       <outfile xil_pn:name="top_map.map"/>
@@ -331,9 +343,12 @@
       <outfile xil_pn:name="top_summary.xml"/>
       <outfile xil_pn:name="top_usage.xml"/>
     </transform>
-    <transform xil_pn:end_ts="1708958170" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1708958154">
+    <transform xil_pn:end_ts="1735840975" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1735840960">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
+      <status xil_pn:value="InputChanged"/>
       <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
       <outfile xil_pn:name="top.ncd"/>
       <outfile xil_pn:name="top.pad"/>
@@ -345,9 +360,10 @@
       <outfile xil_pn:name="top_pad.txt"/>
       <outfile xil_pn:name="top_par.xrpt"/>
     </transform>
-    <transform xil_pn:end_ts="1708958180" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1708958170">
+    <transform xil_pn:end_ts="1735840985" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1735840975">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
       <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
       <outfile xil_pn:name="top.bgn"/>
       <outfile xil_pn:name="top.bin"/>
@@ -362,6 +378,7 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
       <status xil_pn:value="InputAdded"/>
       <status xil_pn:value="InputChanged"/>
@@ -372,6 +389,7 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
       <status xil_pn:value="InputAdded"/>
       <status xil_pn:value="InputChanged"/>
@@ -383,6 +401,7 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
       <status xil_pn:value="InputAdded"/>
       <status xil_pn:value="InputChanged"/>
@@ -394,13 +413,17 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
       <status xil_pn:value="InputAdded"/>
       <status xil_pn:value="InputChanged"/>
       <status xil_pn:value="InputRemoved"/>
     </transform>
-    <transform xil_pn:end_ts="1708958170" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1708958166">
+    <transform xil_pn:end_ts="1735840975" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1735840971">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
+      <status xil_pn:value="InputChanged"/>
       <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
       <outfile xil_pn:name="top.twr"/>
       <outfile xil_pn:name="top.twx"/>

FPGA/VNA/VNA.xise

@@ -23,11 +23,11 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="MCP33131.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
     <file xil_pn:name="Test_MCP33131.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
@@ -55,11 +55,11 @@
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="49"/>
     </file>
     <file xil_pn:name="spi_slave.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
     <file xil_pn:name="SPIConfig.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
     </file>
     <file xil_pn:name="Sweep.vhd" xil_pn:type="FILE_VHDL">
@@ -77,7 +77,7 @@
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="77"/>
     </file>
     <file xil_pn:name="Test_SPICommands.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="115"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="115"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="115"/>
@@ -405,8 +405,8 @@
     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_MCP33131" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_SPICommands" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_MCP33131" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_SPICommands" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -424,7 +424,7 @@
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Test_MCP33131" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Test_SPICommands" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -476,7 +476,7 @@
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_MCP33131|behavior" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_SPICommands|behavior" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="VNA" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

FPGA/VNA/top.ucf

@@ -1,6 +1,9 @@
 CONFIG VCCAUX  = 3.3;
 NET "CLK" PERIOD = 62.5 ns HIGH 50%;
-NET "MCU_SCK" PERIOD = 25ns HIGH 50%;
+NET "MCU_SCK" PERIOD = 23.52941176ns HIGH 50%;
+NET "REF_SCLK" PERIOD = 19.5ns HIGH 50%;
+NET "PORT1_SCLK" PERIOD = 19.5ns HIGH 50%;
+NET "PORT2_SCLK" PERIOD = 19.5ns HIGH 50%;
 
 NET "ATTENUATION[6]" IOSTANDARD = LVCMOS33;
 NET "ATTENUATION[5]" IOSTANDARD = LVCMOS33;

FPGA/VNA/top.vhd

@@ -116,6 +116,7 @@ architecture Behavioral of top is
 		CONFIG_DATA : IN std_logic_vector(95 downto 0);
 		USER_NSAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
 		NSAMPLES : out STD_LOGIC_VECTOR (12 downto 0);
+		SETTLING_TIME : in STD_LOGIC_VECTOR (19 downto 0);
 		SAMPLING_BUSY : in STD_LOGIC;
 		SAMPLING_DONE : IN std_logic;
 		MAX2871_DEF_4 : IN std_logic_vector(31 downto 0);
@@ -255,6 +256,7 @@ architecture Behavioral of top is
 		SWEEP_POINTS : OUT std_logic_vector(12 downto 0);
 		NSAMPLES : OUT std_logic_vector(12 downto 0);
 	   STAGES : out STD_LOGIC_VECTOR (2 downto 0);
+		SETTLING_TIME : out STD_LOGIC_VECTOR (19 downto 0);
 	   SYNC_ENABLED : out STD_LOGIC;
 		SYNC_MASTER : out STD_LOGIC;
 	   PORT1_STAGE : out STD_LOGIC_VECTOR (2 downto 0);
@@ -406,7 +408,7 @@ architecture Behavioral of top is
 	signal sweep_trigger_out : std_logic;
 	
 	-- Configuration signals
-	signal settling_time : std_logic_vector(15 downto 0);
+	signal settling_time : std_logic_vector(19 downto 0);
 	signal def_reg_4 : std_logic_vector(31 downto 0);
 	signal def_reg_3 : std_logic_vector(31 downto 0);
 	signal def_reg_1 : std_logic_vector(31 downto 0);
@@ -692,6 +694,7 @@ begin
 		CONFIG_DATA => sweep_config_data,
 		USER_NSAMPLES => sampling_user_samples,
 		NSAMPLES => sampling_samples,
+		SETTLING_TIME => settling_time,
 		SAMPLING_BUSY => sampling_busy,
 		SAMPLING_DONE => sampling_done,
 		START_SAMPLING => sampling_start,
@@ -801,6 +804,7 @@ begin
 		SWEEP_HALTED => sweep_halted,
 		SWEEP_RESUME => sweep_resume,
 		STAGES => sweep_stages,
+		SETTLING_TIME => settling_time,
 		SYNC_ENABLED => sweep_sync_enabled,
 		SYNC_MASTER => sweep_sync_master,
 		PORT1_STAGE => sweep_port1_stage,

Software/PC_Application/LibreVNA-GUI/Device/LibreVNA/deviceconfigurationdialogv1.ui

@@ -6,8 +6,8 @@
    <rect>
     <x>0</x>
     <y>0</y>
-    <width>488</width>
+    <width>487</width>
-    <height>364</height>
+    <height>356</height>
    </rect>
   </property>
   <property name="windowTitle">
@@ -33,7 +33,7 @@
       <item>
        <spacer name="verticalSpacer">
         <property name="orientation">
-         <enum>Qt::Vertical</enum>
+         <enum>Qt::Orientation::Vertical</enum>
         </property>
         <property name="sizeHint" stdset="0">
          <size>
@@ -141,7 +141,7 @@
    <item>
     <widget class="QDialogButtonBox" name="buttonBox">
      <property name="standardButtons">
-      <set>QDialogButtonBox::Cancel|QDialogButtonBox::Ok</set>
+      <set>QDialogButtonBox::StandardButton::Cancel|QDialogButtonBox::StandardButton::Ok</set>
      </property>
     </widget>
    </item>

Software/PC_Application/LibreVNA-GUI/Device/LibreVNA/librevnadriver.cpp

@@ -428,6 +428,13 @@ bool LibreVNADriver::setVNA(const DeviceDriver::VNASettings &s, std::function<vo
     p.settings.cdbm_excitation_start = s.dBmStart * 100;
     p.settings.cdbm_excitation_stop = s.dBmStop * 100;
     p.settings.stages = s.excitedPorts.size() - 1;
+    auto dwell_us = s.dwellTime * 1e6;
+    if(dwell_us < 0) {
+        dwell_us = 0;
+    } else if(dwell_us > UINT16_MAX) {
+        dwell_us = UINT16_MAX;
+    }
+    p.settings.dwell_time = dwell_us;
     p.settings.suppressPeaks = VNASuppressInvalidPeaks ? 1 : 0;
     p.settings.fixedPowerSetting = VNAAdjustPowerLevel || s.dBmStart != s.dBmStop ? 0 : 1;
     p.settings.logSweep = s.logSweep ? 1 : 0;
@@ -664,7 +671,7 @@ void LibreVNADriver::handleReceivedPacket(const Protocol::PacketInfo &packet)
         info.firmware_version = QString::number(packet.info.FW_major)+"."+QString::number(packet.info.FW_minor)+"."+QString::number(packet.info.FW_patch);
         info.hardware_version = hardwareVersionToString(packet.info.hardware_version)+" Rev."+QString(packet.info.HW_Revision);
         info.supportedFeatures = {
-            Feature::VNA, Feature::VNAFrequencySweep, Feature::VNALogSweep, Feature::VNAPowerSweep, Feature::VNAZeroSpan,
+            Feature::VNA, Feature::VNAFrequencySweep, Feature::VNALogSweep, Feature::VNAPowerSweep, Feature::VNAZeroSpan, Feature::VNADwellTime,
             Feature::Generator,
             Feature::SA, Feature::SATrackingGenerator, Feature::SATrackingOffset,
             Feature::ExtRefIn, Feature::ExtRefOut,
@@ -677,6 +684,8 @@ void LibreVNADriver::handleReceivedPacket(const Protocol::PacketInfo &packet)
         info.Limits.VNA.maxIFBW = packet.info.limits_maxIFBW;
         info.Limits.VNA.mindBm = (double) packet.info.limits_cdbm_min / 100;
         info.Limits.VNA.maxdBm = (double) packet.info.limits_cdbm_max / 100;
+        info.Limits.VNA.minDwellTime = (double) packet.info.limits_minDwellTime * 1e-6;
+        info.Limits.VNA.maxDwellTime = (double) packet.info.limits_maxDwellTime * 1e-6;
 
         info.Limits.Generator.ports = packet.info.num_ports;
         info.Limits.Generator.minFreq = packet.info.limits_minFreq;

Software/PC_Application/LibreVNA-GUI/Device/devicedriver.cpp

@@ -118,6 +118,8 @@ DeviceDriver::Info::Info()
     Limits.VNA.minIFBW = 1;
     Limits.VNA.maxIFBW = 100000000;
     Limits.VNA.maxPoints = 65535;
+    Limits.VNA.minDwellTime = 0;
+    Limits.VNA.maxDwellTime = 1;
 
     Limits.Generator.ports = 2;
     Limits.Generator.minFreq = 0;

Software/PC_Application/LibreVNA-GUI/Device/devicedriver.h

@@ -72,6 +72,7 @@ public:
         VNAPowerSweep,
         VNAZeroSpan,
         VNALogSweep,
+        VNADwellTime,
         // Generator features
         Generator,
         // Spectrum analyzer features
@@ -101,6 +102,8 @@ public:
                 unsigned int maxPoints;
                 // Stimulus level limits in dBm
                 double mindBm, maxdBm;
+                // dwell time limts
+                double minDwellTime, maxDwellTime;
             } VNA;
             struct {
                 // Number of ports
@@ -264,6 +267,8 @@ public:
         bool logSweep;
         // List of ports that should be excited during the sweep (port count starts at 1)
         std::vector<int> excitedPorts;
+        // amount of time the source stays at each point before taking measurements. Ignore if not supported
+        double dwellTime;
     };
 
     class VNAMeasurement {

Software/PC_Application/LibreVNA-GUI/Util/util.h

@@ -72,6 +72,14 @@ namespace Util {
         return brightness > 0.6 ? Qt::black : Qt::white;
     }
 
+    template<typename T> void constrain(T &value, const T &min, const T &max) {
+        if(value > max) {
+            value = max;
+        } else if(value < min) {
+            value = min;
+        }
+    }
+
     /*
      * Performs interpolation of a list of sorted values.
      * T: type of the elements in the list. Must contain a value by which these elements are sorted in the list.

Software/PC_Application/LibreVNA-GUI/VNA/vna.cpp

@@ -454,6 +454,14 @@ VNA::VNA(AppWindow *window, QString name)
     tb_acq->addWidget(new QLabel("IF BW:"));
     tb_acq->addWidget(eBandwidth);
 
+    tb_acq->addWidget(new QLabel("Dwell time:"));
+    acquisitionDwellTime = new SIUnitEdit("s", "um ", 3);
+    width = QFontMetrics(dbm->font()).horizontalAdvance("100ms") + 20;
+    acquisitionDwellTime->setFixedWidth(width);
+    connect(acquisitionDwellTime, &SIUnitEdit::valueChanged, this, &VNA::SetDwellTime);
+    connect(this, &VNA::dwellTimeChanged, acquisitionDwellTime, &SIUnitEdit::setValueQuiet);
+    tb_acq->addWidget(acquisitionDwellTime);
+
     tb_acq->addWidget(new QLabel("Averaging:"));
     lAverages = new QLabel("0/");
     tb_acq->addWidget(lAverages);
@@ -1235,6 +1243,17 @@ void VNA::SetSourceLevel(double level)
     SettingsChanged();
 }
 
+void VNA::SetDwellTime(double time) {
+    if(time > DeviceDriver::getInfo(window->getDevice()).Limits.VNA.maxDwellTime) {
+        time = DeviceDriver::getInfo(window->getDevice()).Limits.VNA.maxDwellTime;
+    } else if(time < DeviceDriver::getInfo(window->getDevice()).Limits.VNA.minDwellTime) {
+        time = DeviceDriver::getInfo(window->getDevice()).Limits.VNA.minDwellTime;
+    }
+    emit dwellTimeChanged(time);
+    settings.dwellTime = time;
+    SettingsChanged();
+}
+
 void VNA::SetStartPower(double level)
 {
     settings.Power.start = level;
@@ -1652,6 +1671,37 @@ void VNA::UpdateCalWidget()
     calLabel->setToolTip(getCalToolTip());
 }
 
+void VNA::ConstrainAllSettings()
+{
+    auto maxFreq = DeviceDriver::getInfo(window->getDevice()).Limits.VNA.maxFreq;
+    auto minFreq = DeviceDriver::getInfo(window->getDevice()).Limits.VNA.minFreq;
+    auto maxPower = DeviceDriver::getInfo(window->getDevice()).Limits.VNA.maxdBm;
+    auto minPower = DeviceDriver::getInfo(window->getDevice()).Limits.VNA.mindBm;
+    auto maxIFBW = DeviceDriver::getInfo(window->getDevice()).Limits.VNA.maxIFBW;
+    auto minIFBW = DeviceDriver::getInfo(window->getDevice()).Limits.VNA.minIFBW;
+    auto maxDwell = DeviceDriver::getInfo(window->getDevice()).Limits.VNA.maxDwellTime;
+    auto minDwell = DeviceDriver::getInfo(window->getDevice()).Limits.VNA.minDwellTime;
+    auto maxPoints = DeviceDriver::getInfo(window->getDevice()).Limits.VNA.maxPoints;
+    Util::constrain(settings.Freq.start, minFreq, maxFreq);
+    Util::constrain(settings.Freq.stop, minFreq, maxFreq);
+    Util::constrain(settings.Freq.excitation_power, minPower, maxPower);
+    Util::constrain(settings.bandwidth, minIFBW, maxIFBW);
+    Util::constrain(settings.dwellTime, minDwell, maxDwell);
+    Util::constrain(settings.npoints, (unsigned int) 0, maxPoints);
+    Util::constrain(settings.Power.frequency, minFreq, maxFreq);
+    Util::constrain(settings.Power.start, minPower, maxPower);
+    Util::constrain(settings.Power.stop, minPower, maxPower);
+    emit startFreqChanged(settings.Freq.start);
+    emit stopFreqChanged(settings.Freq.stop);
+    emit sourceLevelChanged(settings.Freq.excitation_power);
+    emit IFBandwidthChanged(settings.bandwidth);
+    emit dwellTimeChanged(settings.dwellTime);
+    emit pointsChanged(settings.npoints);
+    emit powerSweepFrequencyChanged(settings.Power.frequency);
+    emit startPowerChanged(settings.Power.start);
+    emit stopPowerChanged(settings.Power.stop);
+}
+
 void VNA::createDefaultTracesAndGraphs(int ports)
 {
     auto getDefaultColor = [](int ports, int i, int j)->QColor {
@@ -1780,6 +1830,16 @@ void VNA::preset()
     createDefaultTracesAndGraphs(DeviceDriver::getInfo(window->getDevice()).Limits.VNA.ports);
 }
 
+void VNA::deviceInfoUpdated()
+{
+    if(DeviceDriver::getInfo(window->getDevice()).supportedFeatures.count(DeviceDriver::Feature::VNADwellTime)) {
+        acquisitionDwellTime->setEnabled(true);
+    } else {
+        acquisitionDwellTime->setEnabled(false);
+    }
+    ConstrainAllSettings();
+}
+
 QString VNA::SweepTypeToString(VNA::SweepType sw)
 {
     switch(sw) {
@@ -1904,6 +1964,7 @@ void VNA::ConfigureDevice(bool resetTraces, std::function<void(bool)> cb)
             s.dBmStop = stop;
             s.logSweep = false;
         }
+        s.dwellTime = settings.dwellTime;
         if(window->getDevice() && isActive) {
             window->getDevice()->setVNA(s, [=](bool res){
                 // device received command, reset traces now

Software/PC_Application/LibreVNA-GUI/VNA/vna.h

@@ -38,6 +38,8 @@ public:
 
     void preset() override;
 
+    virtual void deviceInfoUpdated() override;
+
     QList<QAction*> getImportOptions() override { return importActions;}
     QList<QAction*> getExportOptions() override { return exportActions;}
 
@@ -72,6 +74,7 @@ public:
         } Power;
         unsigned int npoints;
         double bandwidth;
+        double dwellTime;
         std::vector<int> excitedPorts;
         // if the number of points is higher than supported by the hardware, the sweep has to be segmented into multiple parts
         int segments;
@@ -109,6 +112,7 @@ private slots:
     void SetLogSweep(bool log);
     // Acquisition control
     void SetSourceLevel(double level);
+    void SetDwellTime(double time);
     // Power sweep settings
     void SetStartPower(double level);
     void SetStopPower(double level);
@@ -135,6 +139,7 @@ private:
     void LoadSweepSettings();
     void StoreSweepSettings();
     void UpdateCalWidget();
+    void ConstrainAllSettings();
 
     void createDefaultTracesAndGraphs(int ports);
 private slots:
@@ -155,6 +160,9 @@ private:
     QTimer configurationTimer;
     bool configurationTimerResetTraces;
 
+    // Toolbar elements
+    SIUnitEdit *acquisitionDwellTime;
+
     // Calibration
     Calibration cal;
     bool changingSettings;
@@ -205,6 +213,7 @@ signals:
     void pointsChanged(unsigned int points);
     void IFBandwidthChanged(double bandwidth);
     void averagingChanged(unsigned int averages);
+    void dwellTimeChanged(double time);
 
     void startPowerChanged(double level);
     void stopPowerChanged(double level);

Software/VNA_embedded/Application/App.cpp

@@ -268,9 +268,7 @@ inline void App_Process() {
 					{
 						Protocol::PacketInfo send;
 						send.type = Protocol::PacketType::DeviceConfiguration;
-						send.deviceConfig.V1.IF1 = HW::getIF1();
+						send.deviceConfig = HW::getDeviceConfig();
-						send.deviceConfig.V1.ADCprescaler = HW::getADCPrescaler();
-						send.deviceConfig.V1.DFTphaseInc = HW::getDFTPhaseInc();
 						Communication::Send(send);
 					}
 					break;
@@ -334,7 +332,50 @@ inline void App_Process() {
 	}
 }
 
+#include "HW_HAL.hpp"
+
 void App_Start() {
 	App_Init();
+
+//	uint32_t LO2_1 = 61750000;
+//	uint32_t LO2_2 = 61752000;
+//
+//	HWHAL::Si5351.Enable(HWHAL::SiChannel::Port1LO2);
+//	HWHAL::Si5351.Enable(HWHAL::SiChannel::Port2LO2);
+//	HWHAL::Si5351.Enable(HWHAL::SiChannel::RefLO2);
+//
+////	HWHAL::Si5351.Disable(HWHAL::SiChannel::Port1LO2);
+////	HWHAL::Si5351.Disable(HWHAL::SiChannel::Port2LO2);
+////	HWHAL::Si5351.Disable(HWHAL::SiChannel::RefLO2);
+//
+////	FPGA::Enable(FPGA::Periphery::Port1Mixer);
+////	FPGA::Enable(FPGA::Periphery::Port2Mixer);
+////	FPGA::Enable(FPGA::Periphery::RefMixer);
+//
+//	uint32_t i=64000000;
+//	HWHAL::Si5351.SetCLK(HWHAL::SiChannel::Port1LO2, i, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
+//	HWHAL::Si5351.SetCLK(HWHAL::SiChannel::Port2LO2, i, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
+//	HWHAL::Si5351.SetCLK(HWHAL::SiChannel::RefLO2, i, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
+//	HWHAL::Si5351.ResetPLL(Si5351C::PLL::B);
+//	while(1) {
+//		for(i=61000000;i<62000000;i++) {
+//			LOG_INFO("Setting LO2=%lu", i);
+//			HWHAL::Si5351.SetPLL(Si5351C::PLL::B, i*13, Si5351C::PLLSource::XTAL);
+////			HWHAL::Si5351.Disable(HWHAL::SiChannel::Port1LO2);
+////			HWHAL::Si5351.Disable(HWHAL::SiChannel::Port2LO2);
+////			HWHAL::Si5351.Disable(HWHAL::SiChannel::RefLO2);
+////			HWHAL::Si5351.SetCLK(HWHAL::SiChannel::Port1LO2, i, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
+////			HWHAL::Si5351.SetCLK(HWHAL::SiChannel::Port2LO2, i, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
+////			HWHAL::Si5351.SetCLK(HWHAL::SiChannel::RefLO2, i, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
+//
+////			HWHAL::Si5351.Enable(HWHAL::SiChannel::Port1LO2);
+////			HWHAL::Si5351.Enable(HWHAL::SiChannel::Port2LO2);
+////			HWHAL::Si5351.Enable(HWHAL::SiChannel::RefLO2);
+////			HWHAL::Si5351.ResetPLL(Si5351C::PLL::B);
+////			HWHAL::Si5351.WaitForLock(Si5351C::PLL::B, 10);
+//			vTaskDelay(1);
+//		}
+//	}
+
 	App_Process();
 }

Software/VNA_embedded/Application/Communication/Protocol.hpp

@@ -10,7 +10,7 @@ using namespace PacketConstants;
 
 namespace Protocol {
 
-static constexpr uint16_t Version = 13;
+static constexpr uint16_t Version = 14;
 
 #pragma pack(push, 1)
 
@@ -180,6 +180,7 @@ using SweepSettings = struct _sweepSettings {
 	uint16_t unused2:1;
 
     int16_t cdbm_excitation_stop; // in 1/100 dbm
+    uint16_t dwell_time; // in us
 };
 
 using ReferenceSettings = struct _referenceSettings {
@@ -215,6 +216,8 @@ using DeviceInfo = struct _deviceInfo {
     uint8_t limits_maxAmplitudePoints;
     uint64_t limits_maxFreqHarmonic;
     uint8_t num_ports;
+    uint16_t limits_minDwellTime;
+    uint16_t limits_maxDwellTime;
 };
 
 using DeviceStatus = struct _deviceStatus {

Software/VNA_embedded/Application/Drivers/FPGA/FPGA.cpp

@@ -132,6 +132,17 @@ void FPGA::SetSamplesPerPoint(uint32_t nsamples) {
 	WriteRegister(Reg::SamplesPerPoint, nsamples);
 }
 
+void FPGA::SetSettlingTime(uint16_t us) {
+	// register is in multiples of 1/102.4 MHz
+	uint32_t value = (uint32_t) us * 512 / 5;
+	constexpr uint32_t maxval = 0xFFFFF;
+	if(value > maxval) {
+		value = maxval;
+	}
+	WriteRegister(Reg::SettlingTimeLow, value & 0xFFFF);
+	WriteRegister(Reg::SettlingTimeHigh, value >> 16);
+}
+
 void FPGA::SetupSweep(uint8_t stages, uint8_t port1_stage, uint8_t port2_stage, bool synchronize, bool syncMaster) {
 	uint16_t value = 0x0000;
 	value |= (uint16_t) (stages & 0x07) << 13;
@@ -199,7 +210,7 @@ void FPGA::WriteMAX2871Default(uint32_t *DefaultRegs) {
 }
 
 void FPGA::WriteSweepConfig(uint16_t pointnum, bool lowband, uint32_t *SourceRegs, uint32_t *LORegs,
-		uint8_t attenuation, uint64_t frequency, SettlingTime settling, Samples samples, bool halt, LowpassFilter filter) {
+		uint8_t attenuation, uint64_t frequency, Samples samples, bool halt, LowpassFilter filter) {
 	uint16_t send[7];
 	// select which point this sweep config is for
 	send[0] = pointnum & 0x1FFF;
@@ -222,7 +233,12 @@ void FPGA::WriteSweepConfig(uint16_t pointnum, bool lowband, uint32_t *SourceReg
 	if (halt) {
 		send[1] |= 0x8000;
 	}
-	send[1] |= (int) settling << 13;
+	if(LO_N & 0x40) {
+		send[1] |= 0x4000;
+	}
+	if(Source_N & 0x40) {
+		send[1] |= 0x2000;
+	}
 	send[1] |= (int) samples << 10;
 	if(filter == LowpassFilter::Auto) {
 		// Select source LP filter
@@ -239,13 +255,13 @@ void FPGA::WriteSweepConfig(uint16_t pointnum, bool lowband, uint32_t *SourceReg
 		send[1] |= (int) filter << 8;
 	}
 	send[2] = (LO_M & 0x000F) << 12 | LO_FRAC;
-	send[3] = LO_DIV_A << 13 | LO_VCO << 7 | LO_N << 1;
+	send[3] = LO_DIV_A << 13 | LO_VCO << 7 | (LO_N & 0x3F) << 1;
 	if (lowband) {
 		send[3] |= 0x0001;
 	}
 	send[4] = Source_Power << 14 | (uint16_t) attenuation << 7 | Source_M >> 5;
 	send[5] = (Source_M & 0x001F) << 11 | Source_FRAC >> 1;
-	send[6] = (Source_FRAC & 0x0001) << 15 | Source_DIV_A << 12 | Source_VCO << 6 | Source_N;
+	send[6] = (Source_FRAC & 0x0001) << 15 | Source_DIV_A << 12 | Source_VCO << 6 | (Source_N & 0x3F);
 	SwitchBytes(send[0]);
 	SwitchBytes(send[1]);
 	SwitchBytes(send[2]);

Software/VNA_embedded/Application/Drivers/FPGA/FPGA.hpp

@@ -29,6 +29,8 @@ enum class Reg {
 	MAX2871Def4MSB = 0x0F,
 	DFTFirstBin = 0x12,
 	DFTFreqSpacing = 0x13,
+	SettlingTimeLow = 0x14,
+	SettlingTimeHigh = 0x15,
 };
 
 using SamplingResult = struct _samplingresult {
@@ -82,13 +84,6 @@ enum class LowpassFilter {
 	Auto = 0xFF,
 };
 
-enum class SettlingTime {
-	us20 = 0x00,
-	us60 = 0x01,
-	us180 = 0x02,
-	us540 = 0x03,
-};
-
 enum class Samples {
 	SPPRegister = 0x00,
     S96 = 0x01,
@@ -114,6 +109,7 @@ bool Init(HaltedCallback cb = nullptr);
 void WriteRegister(FPGA::Reg reg, uint16_t value);
 void SetNumberOfPoints(uint16_t npoints);
 void SetSamplesPerPoint(uint32_t nsamples);
+void SetSettlingTime(uint16_t us);
 void SetupSweep(uint8_t stages, uint8_t port1_stage, uint8_t port2_stage, bool synchronize = false, bool syncMaster = false);
 void Enable(Periphery p, bool enable = true);
 void Disable(Periphery p);
@@ -124,7 +120,7 @@ void DisableInterrupt(Interrupt i);
 void DisableAllInterrupts();
 void WriteMAX2871Default(uint32_t *DefaultRegs);
 void WriteSweepConfig(uint16_t pointnum, bool lowband, uint32_t *SourceRegs, uint32_t *LORegs,
-		uint8_t attenuation, uint64_t frequency, SettlingTime settling, Samples samples, bool halt = false, LowpassFilter filter = LowpassFilter::Auto);
+		uint8_t attenuation, uint64_t frequency, Samples samples, bool halt = false, LowpassFilter filter = LowpassFilter::Auto);
 using ReadCallback = void(*)(const SamplingResult &result);
 bool InitiateSampleRead(ReadCallback cb);
 void SetupDFT(uint32_t f_firstBin, uint32_t f_binSpacing);

Software/VNA_embedded/Application/Drivers/Si5351C.cpp

@@ -70,7 +70,7 @@ bool Si5351C::SetPLL(PLL pll, uint32_t frequency, PLLSource src) {
 	FindOptimalDivider(frequency, srcFreq, c.P1, c.P2, c.P3);
 
 	FreqPLL[(int) pll] = frequency;
-	LOG_INFO("Setting PLL %c to %luHz", pll==PLL::A ? 'A' : 'B', frequency);
+	LOG_DEBUG("Setting PLL %c to %luHz", pll==PLL::A ? 'A' : 'B', frequency);
 	return WritePLLConfig(c, pll);
 }
 

Software/VNA_embedded/Application/Generator.cpp

@@ -9,6 +9,11 @@
 using namespace HWHAL;
 
 void Generator::Setup(Protocol::GeneratorSettings g) {
+	// Disable 2.LO
+	Si5351.Disable(SiChannel::Port1LO2);
+	Si5351.Disable(SiChannel::Port2LO2);
+	Si5351.Disable(SiChannel::RefLO2);
+
 	HW::SetMode(HW::Mode::Generator);
 	if(g.activePort == 0) {
 		// both ports disabled, no need to configure PLLs

Software/VNA_embedded/Application/Hardware.cpp

@@ -115,21 +115,25 @@ bool HW::Init() {
 
 	// Both MAX2871 get a 100MHz reference
 //	Si5351.SetBypass(SiChannel::Source, Si5351C::PLLSource::XTAL);
-	Si5351.SetCLK(SiChannel::Source, HW::PLLRef, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
+	Si5351.SetCLK(SiChannel::Source, HW::PLLRef, Si5351C::PLL::A, Si5351C::DriveStrength::mA8);
 	Si5351.Enable(SiChannel::Source);
 //	Si5351.SetBypass(SiChannel::LO1, Si5351C::PLLSource::XTAL);
-	Si5351.SetCLK(SiChannel::LO1, HW::PLLRef, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
+	Si5351.SetCLK(SiChannel::LO1, HW::PLLRef, Si5351C::PLL::A, Si5351C::DriveStrength::mA8);
 	Si5351.Enable(SiChannel::LO1);
 	// 16MHz FPGA clock
-	Si5351.SetCLK(SiChannel::FPGA, HW::FPGAClkInFrequency, Si5351C::PLL::A, Si5351C::DriveStrength::mA2);
+	Si5351.SetCLK(SiChannel::FPGA, HW::FPGAClkInFrequency, Si5351C::PLL::A, Si5351C::DriveStrength::mA8);
 	Si5351.Enable(SiChannel::FPGA);
 
 	// Generate second LO with Si5351
-	Si5351.SetCLK(SiChannel::Port1LO2, IF1 - IF2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
+	// The 2.LO frequency is only set up here once. The frequencies chosen for DefaultLO2 and PLL B must
+	// have an integer divisor. When changing the 2.LO frequency after this point, the PLL B frequency is
+	// changed instead of modifying the clock output dividers. Otherwise, phase reversal may happen
+	// intermittently at one or multiple 2.LO outputs. See also https://github.com/jankae/LibreVNA/issues/280
+	Si5351.SetCLK(SiChannel::Port1LO2, DefaultLO2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
 	Si5351.Enable(SiChannel::Port1LO2);
-	Si5351.SetCLK(SiChannel::Port2LO2, IF1 - IF2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
+	Si5351.SetCLK(SiChannel::Port2LO2, DefaultLO2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
 	Si5351.Enable(SiChannel::Port2LO2);
-	Si5351.SetCLK(SiChannel::RefLO2, IF1 - IF2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
+	Si5351.SetCLK(SiChannel::RefLO2, DefaultLO2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
 	Si5351.Enable(SiChannel::RefLO2);
 
 	// PLL reset appears to realign phases of clock signals
@@ -152,6 +156,9 @@ bool HW::Init() {
 	// Set phase increment according to
 	FPGA::WriteRegister(FPGA::Reg::PhaseIncrement, DFTphaseInc);
 
+	// Set default settling time
+	FPGA::SetSettlingTime(HW::DefaultDwellTime);
+
 	Exti::SetCallback(FPGA_INTR_GPIO_Port, FPGA_INTR_Pin, Exti::EdgeType::Rising, Exti::Pull::Down, FPGA_Interrupt);
 
 	// Initialize PLLs and build VCO maps
@@ -413,6 +420,14 @@ void HW::Ref::update() {
 	}
 }
 
+Si5351C::PLLSource HW::Ref::getSource() {
+	if(extRefInUse) {
+		return Si5351C::PLLSource::CLKIN;
+	} else {
+		return Si5351C::PLLSource::XTAL;
+	}
+}
+
 void HW::setAcquisitionFrequencies(Protocol::DeviceConfig s) {
 	IF1 = s.V1.IF1;
 	ADCprescaler = s.V1.ADCprescaler;
@@ -422,6 +437,14 @@ void HW::setAcquisitionFrequencies(Protocol::DeviceConfig s) {
 	ADCsamplerate = ADCrate;
 }
 
+Protocol::DeviceConfig HW::getDeviceConfig() {
+	Protocol::DeviceConfig s;
+	s.V1.ADCprescaler = ADCprescaler;
+	s.V1.DFTphaseInc = DFTphaseInc;
+	s.V1.IF1 = IF1;
+	return s;
+}
+
 uint32_t HW::getIF1() {
 	return IF1;
 }

Software/VNA_embedded/Application/Hardware.hpp

@@ -32,7 +32,6 @@ static constexpr uint32_t TCXOFrequency = 26000000;
 static constexpr uint32_t ExtRefInFrequency = 10000000;
 static constexpr uint32_t ExtRefOut1Frequency = 10000000;
 static constexpr uint32_t ExtRefOut2Frequency = 10000000;
-static constexpr uint32_t SI5351CPLLAlignedFrequency = 832000000;
 static constexpr uint32_t SI5351CPLLConstantFrequency = 800000000;
 static constexpr uint32_t FPGAClkInFrequency = 16000000;
 static constexpr uint32_t DefaultADCSamplerate = 800000;
@@ -41,8 +40,12 @@ static constexpr uint32_t DefaultIF2 = 250000;
 static constexpr uint32_t LO1_minFreq = 25000000;
 static constexpr uint32_t MaxSamples = 130944;
 static constexpr uint32_t MinSamples = 16;
-static constexpr uint32_t PLLRef = 104000000;
+static constexpr uint32_t PLLRef = 100000000;
 static constexpr uint32_t BandSwitchFrequency = 25000000;
+static constexpr uint32_t DefaultLO2 = DefaultIF1 - DefaultIF2;
+static constexpr uint8_t LO2Multiplier = 13;
+static constexpr uint32_t SI5351CPLLAlignedFrequency = DefaultLO2 * LO2Multiplier;
+static constexpr uint16_t DefaultDwellTime = 60;
 
 static constexpr uint8_t DefaultADCprescaler = FPGA::Clockrate / DefaultADCSamplerate;
 static_assert(DefaultADCprescaler * DefaultADCSamplerate == FPGA::Clockrate, "ADCSamplerate can not be reached exactly");
@@ -84,6 +87,8 @@ static constexpr Protocol::DeviceInfo Info = {
 		.limits_maxAmplitudePoints = Cal::maxPoints,
 		.limits_maxFreqHarmonic = 18000000000,
 		.num_ports = 2,
+		.limits_minDwellTime = 0,
+		.limits_maxDwellTime = 10239,
 };
 
 enum class Mode {
@@ -127,10 +132,12 @@ namespace Ref {
 	// reference won't change until update is called
 	void set(Protocol::ReferenceSettings s);
 	void update();
+	Si5351C::PLLSource getSource();
 }
 
 // Acquisition frequency settings
 void setAcquisitionFrequencies(Protocol::DeviceConfig s);
+Protocol::DeviceConfig getDeviceConfig();
 uint32_t getIF1();
 uint32_t getIF2();
 uint32_t getADCRate();

Software/VNA_embedded/Application/Manual.cpp

@@ -32,13 +32,12 @@ void Manual::Setup(Protocol::ManualControl m) {
 	// Configure LO2
 	if(m.V1.LO2EN) {
 		// Generate second LO with Si5351
-		Si5351.SetCLK(SiChannel::Port1LO2, m.V1.LO2Frequency, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
 		Si5351.Enable(SiChannel::Port1LO2);
-		Si5351.SetCLK(SiChannel::Port2LO2, m.V1.LO2Frequency, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
 		Si5351.Enable(SiChannel::Port2LO2);
-		Si5351.SetCLK(SiChannel::RefLO2, m.V1.LO2Frequency, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
 		Si5351.Enable(SiChannel::RefLO2);
 
+		Si5351.SetPLL(Si5351C::PLL::B, m.V1.LO2Frequency*HW::LO2Multiplier, HW::Ref::getSource());
+
 		// PLL reset appears to realign phases of clock signals
 		Si5351.ResetPLL(Si5351C::PLL::B);
 	} else {
@@ -54,8 +53,7 @@ void Manual::Setup(Protocol::ManualControl m) {
 
 	// Configure single sweep point
 	FPGA::WriteSweepConfig(0, !m.V1.SourceHighband, Source.GetRegisters(),
-			LO1.GetRegisters(), m.V1.attenuator, 0, FPGA::SettlingTime::us60,
+			LO1.GetRegisters(), m.V1.attenuator, 0, FPGA::Samples::SPPRegister, 0,
-			FPGA::Samples::SPPRegister, 0,
 			(FPGA::LowpassFilter) m.V1.SourceHighLowpass);
 
 	FPGA::SetWindow((FPGA::Window) m.V1.WindowType);

Software/VNA_embedded/Application/SpectrumAnalyzer.cpp

@@ -158,8 +158,7 @@ static void StartNextSample() {
 
 	// only adjust LO2 PLL if necessary (if the deviation is significantly less than the RBW it does not matter)
 	if((uint32_t) abs(LO2freq - lastLO2) > actualRBW / 100) {
-		Si5351.SetCLK(SiChannel::Port1LO2, LO2freq, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
+		Si5351.SetPLL(Si5351C::PLL::B, LO2freq*HW::LO2Multiplier, HW::Ref::getSource());
-		Si5351.SetCLK(SiChannel::Port2LO2, LO2freq, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
 		lastLO2 = LO2freq;
 	}
 	if (s.UseDFT) {
@@ -175,7 +174,7 @@ static void StartNextSample() {
 
 	// Configure the sampling in the FPGA
 	FPGA::WriteSweepConfig(0, trackingLowband, Source.GetRegisters(), LO1.GetRegisters(), attenuator,
-			trackingFreq, FPGA::SettlingTime::us60, FPGA::Samples::SPPRegister, 0,
+			trackingFreq, FPGA::Samples::SPPRegister, 0,
 			FPGA::LowpassFilter::Auto);
 
 	if(firstSample && (signalIDstep == 0)) {

Software/VNA_embedded/Application/VNA.cpp

@@ -132,6 +132,8 @@ bool VNA::Setup(Protocol::SweepSettings s) {
 	// has to be one less than actual number of samples
 	FPGA::SetSamplesPerPoint(samplesPerPoint);
 
+	FPGA::SetSettlingTime(s.dwell_time);
+
 	// reset unlevel flag if it was set from a previous sweep/mode
 	HW::SetOutputUnlevel(false);
 	// Start with average level
@@ -161,9 +163,10 @@ bool VNA::Setup(Protocol::SweepSettings s) {
 	FPGA::WriteMAX2871Default(Source.GetRegisters());
 
 	last_LO2 = HW::getIF1() - HW::getIF2();
-	Si5351.SetCLK(SiChannel::Port1LO2, last_LO2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
+	Si5351.Enable(SiChannel::Port1LO2);
-	Si5351.SetCLK(SiChannel::Port2LO2, last_LO2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
+	Si5351.Enable(SiChannel::Port2LO2);
-	Si5351.SetCLK(SiChannel::RefLO2, last_LO2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
+	Si5351.Enable(SiChannel::RefLO2);
+	Si5351.SetPLL(Si5351C::PLL::B, last_LO2*HW::LO2Multiplier, HW::Ref::getSource());
 	Si5351.ResetPLL(Si5351C::PLL::B);
 	Si5351.WaitForLock(Si5351C::PLL::B, 10);
 
@@ -193,9 +196,14 @@ bool VNA::Setup(Protocol::SweepSettings s) {
 		// SetFrequency only manipulates the register content in RAM, no SPI communication is done.
 		// No mode-switch of FPGA necessary here.
 		setPLLFrequencies(freq);
-		if(s.suppressPeaks) {
+		uint32_t new_LO2;
-			if(needs2LOshift(freq, last_LO2, actualBandwidth, &last_LO2)) {
+		auto needs_shift = needs2LOshift(freq, last_LO2, actualBandwidth, &new_LO2);
+		if(needs_shift) {
+			if(s.suppressPeaks) {
 				needs_halt = true;
+				last_LO2 = new_LO2;
+			} else {
+				LOG_WARN("Point at f=%lu%06lu needs an LO shift but the feature is disabled. This will cause a peak.", (uint32_t) (freq/1000000), (uint32_t) (freq%1000000));
 			}
 		}
 		if (last_lowband && !lowband) {
@@ -232,7 +240,7 @@ bool VNA::Setup(Protocol::SweepSettings s) {
 		}
 
 		FPGA::WriteSweepConfig(i, lowband, Source.GetRegisters(),
-				LO1.GetRegisters(), attenuator, freq, FPGA::SettlingTime::us60,
+				LO1.GetRegisters(), attenuator, freq,
 				FPGA::Samples::SPPRegister, needs_halt);
 		last_lowband = lowband;
 	}
@@ -428,9 +436,7 @@ void VNA::SweepHalted() {
 			// is required to determine the need for a 2.LO shift
 			setPLLFrequencies(frequency);
 			if(needs2LOshift(frequency, last_LO2, actualBandwidth, &last_LO2)) {
-				Si5351.SetCLK(SiChannel::Port1LO2, last_LO2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
+				Si5351.SetPLL(Si5351C::PLL::B, last_LO2*HW::LO2Multiplier, HW::Ref::getSource());
-				Si5351.SetCLK(SiChannel::Port2LO2, last_LO2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
-				Si5351.SetCLK(SiChannel::RefLO2, last_LO2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
 				Si5351.ResetPLL(Si5351C::PLL::B);
 				Si5351.WaitForLock(Si5351C::PLL::B, 10);
 				// PLL reset causes the 2.LO to turn off briefly and then ramp on back, needs delay before next point

Software/VNA_embedded/Src/main.c

@@ -118,6 +118,7 @@ int main(void)
   /* Initialize all configured peripherals */
   MX_GPIO_Init();
   MX_DMA_Init();
+  MX_I2C2_Init();
   MX_SPI1_Init();
   MX_SPI2_Init();
   MX_UCPD1_Init();
@@ -192,7 +193,7 @@ void SystemClock_Config(void)
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
   RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
-  RCC_OscInitStruct.PLL.PLLN = 80;
+  RCC_OscInitStruct.PLL.PLLN = 85;
   RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
   RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
   RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
@@ -296,7 +297,7 @@ static void MX_I2C2_Init(void)
 
   /* USER CODE END I2C2_Init 1 */
   hi2c2.Instance = I2C2;
-  hi2c2.Init.Timing = 0x00F07BFF;
+  hi2c2.Init.Timing = 0x10802D9B;
   hi2c2.Init.OwnAddress1 = 0;
   hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
   hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;

Software/VNA_embedded/Src/stm32g4xx_it.c

@@ -73,7 +73,7 @@ extern TIM_HandleTypeDef htim17;
 void NMI_Handler(void)
 {
   /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
-
+#define void __weak void
   /* USER CODE END NonMaskableInt_IRQn 0 */
   /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
   while (1)
@@ -85,17 +85,17 @@ void NMI_Handler(void)
 /**
   * @brief This function handles Hard fault interrupt.
   */
-//void HardFault_Handler(void)
+void HardFault_Handler(void)
-//{
+{
-//  /* USER CODE BEGIN HardFault_IRQn 0 */
+  /* USER CODE BEGIN HardFault_IRQn 0 */
-//
+#undef void
-//  /* USER CODE END HardFault_IRQn 0 */
+  /* USER CODE END HardFault_IRQn 0 */
-//  while (1)
+  while (1)
-//  {
+  {
-//    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
-//    /* USER CODE END W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
-//  }
+  }
-//}
+}
 
 /**
   * @brief This function handles Memory management fault.

Software/VNA_embedded/VNA_embedded.ioc

@@ -98,7 +98,7 @@ File.Version=6
 GPIO.groupedBy=Group By Peripherals
 I2C2.I2C_Speed_Mode=I2C_Fast
 I2C2.IPParameters=Timing,I2C_Speed_Mode
-I2C2.Timing=0x00F07BFF
+I2C2.Timing=0x10802D9B
 KeepUserPlacement=false
 Mcu.Family=STM32G4
 Mcu.IP0=ADC1
@@ -338,65 +338,65 @@ ProjectManager.TargetToolchain=STM32CubeIDE
 ProjectManager.ToolChainLocation=
 ProjectManager.UnderRoot=true
 ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_I2C2_Init-I2C2-false-HAL-true,5-MX_SPI1_Init-SPI1-false-HAL-true,6-MX_SPI2_Init-SPI2-false-HAL-true,7-MX_UCPD1_Init-UCPD1-false-LL-true,8-MX_USART3_UART_Init-USART3-false-HAL-true,9-MX_USB_PCD_Init-USB-false-HAL-true,10-MX_TIM1_Init-TIM1-false-HAL-true,11-MX_TIM2_Init-TIM2-false-HAL-true,12-MX_ADC1_Init-ADC1-false-HAL-true
-RCC.ADC12Freq_Value=160000000
+RCC.ADC12Freq_Value=170000000
-RCC.AHBFreq_Value=160000000
+RCC.AHBFreq_Value=170000000
-RCC.APB1Freq_Value=160000000
+RCC.APB1Freq_Value=170000000
-RCC.APB1TimFreq_Value=160000000
+RCC.APB1TimFreq_Value=170000000
-RCC.APB2Freq_Value=160000000
+RCC.APB2Freq_Value=170000000
-RCC.APB2TimFreq_Value=160000000
+RCC.APB2TimFreq_Value=170000000
 RCC.CK48CLockSelection=RCC_USBCLKSOURCE_HSI48
 RCC.CRSFreq_Value=48000000
-RCC.CortexFreq_Value=160000000
+RCC.CortexFreq_Value=170000000
 RCC.EXTERNAL_CLOCK_VALUE=12288000
-RCC.FCLKCortexFreq_Value=160000000
+RCC.FCLKCortexFreq_Value=170000000
-RCC.FDCANFreq_Value=160000000
+RCC.FDCANFreq_Value=170000000
 RCC.FamilyName=M
-RCC.HCLKFreq_Value=160000000
+RCC.HCLKFreq_Value=170000000
 RCC.HSE_VALUE=8000000
 RCC.HSI48_VALUE=48000000
 RCC.HSI_VALUE=16000000
-RCC.I2C1Freq_Value=160000000
+RCC.I2C1Freq_Value=170000000
-RCC.I2C2Freq_Value=160000000
+RCC.I2C2Freq_Value=170000000
-RCC.I2C3Freq_Value=160000000
+RCC.I2C3Freq_Value=170000000
-RCC.I2SFreq_Value=160000000
+RCC.I2SFreq_Value=170000000
 RCC.IPParameters=ADC12Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CK48CLockSelection,CRSFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2SFreq_Value,LPTIM1Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLM,PLLN,PLLPoutputFreq_Value,PLLQ,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
-RCC.LPTIM1Freq_Value=160000000
+RCC.LPTIM1Freq_Value=170000000
-RCC.LPUART1Freq_Value=160000000
+RCC.LPUART1Freq_Value=170000000
 RCC.LSCOPinFreq_Value=32000
 RCC.LSE_VALUE=32768
 RCC.LSI_VALUE=32000
 RCC.MCO1PinFreq_Value=16000000
 RCC.PLLM=RCC_PLLM_DIV4
-RCC.PLLN=80
+RCC.PLLN=85
-RCC.PLLPoutputFreq_Value=160000000
+RCC.PLLPoutputFreq_Value=170000000
 RCC.PLLQ=RCC_PLLQ_DIV4
-RCC.PLLQoutputFreq_Value=80000000
+RCC.PLLQoutputFreq_Value=85000000
-RCC.PLLRCLKFreq_Value=160000000
+RCC.PLLRCLKFreq_Value=170000000
-RCC.PWRFreq_Value=160000000
+RCC.PWRFreq_Value=170000000
 RCC.RNGFreq_Value=48000000
-RCC.SAI1Freq_Value=160000000
+RCC.SAI1Freq_Value=170000000
-RCC.SYSCLKFreq_VALUE=160000000
+RCC.SYSCLKFreq_VALUE=170000000
 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
 RCC.UART4Freq_Value=160000000
-RCC.USART1Freq_Value=160000000
+RCC.USART1Freq_Value=170000000
-RCC.USART2Freq_Value=160000000
+RCC.USART2Freq_Value=170000000
-RCC.USART3Freq_Value=160000000
+RCC.USART3Freq_Value=170000000
 RCC.USBFreq_Value=48000000
 RCC.VCOInputFreq_Value=4000000
-RCC.VCOOutputFreq_Value=320000000
+RCC.VCOOutputFreq_Value=340000000
 SH.GPXTI1.0=GPIO_EXTI1
 SH.GPXTI1.ConfNb=1
 SH.S_TIM2_CH1.0=TIM2_CH1,PWM Generation1 CH1
 SH.S_TIM2_CH1.ConfNb=1
 SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_4
-SPI1.CalculateBaudRate=40.0 MBits/s
+SPI1.CalculateBaudRate=42.5 MBits/s
 SPI1.DataSize=SPI_DATASIZE_8BIT
 SPI1.Direction=SPI_DIRECTION_2LINES
 SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler,DataSize
 SPI1.Mode=SPI_MODE_MASTER
 SPI1.VirtualType=VM_MASTER
 SPI2.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_4
-SPI2.CalculateBaudRate=40.0 MBits/s
+SPI2.CalculateBaudRate=42.5 MBits/s
 SPI2.DataSize=SPI_DATASIZE_8BIT
 SPI2.Direction=SPI_DIRECTION_2LINES
 SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler,DataSize