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WIP: rework 2.LO + add dwell time

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This commit is contained in:
Jan Käberich 2025-01-02 19:16:53 +01:00
parent a2abc0c2af
commit 24314e2361
33 changed files with 483 additions and 190 deletions
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5
Software/VNA_embedded/Application/SpectrumAnalyzer.cpp
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@ -158,8 +158,7 @@ static void StartNextSample() {
// only adjust LO2 PLL if necessary (if the deviation is significantly less than the RBW it does not matter)
if((uint32_t) abs(LO2freq - lastLO2) > actualRBW / 100) {
Si5351.SetCLK(SiChannel::Port1LO2, LO2freq, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
Si5351.SetCLK(SiChannel::Port2LO2, LO2freq, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
Si5351.SetPLL(Si5351C::PLL::B, LO2freq*HW::LO2Multiplier, HW::Ref::getSource());
lastLO2 = LO2freq;
}
if (s.UseDFT) {
@ -175,7 +174,7 @@ static void StartNextSample() {
// Configure the sampling in the FPGA
FPGA::WriteSweepConfig(0, trackingLowband, Source.GetRegisters(), LO1.GetRegisters(), attenuator,
trackingFreq, FPGA::SettlingTime::us60, FPGA::Samples::SPPRegister, 0,
trackingFreq, FPGA::Samples::SPPRegister, 0,
FPGA::LowpassFilter::Auto);
if(firstSample && (signalIDstep == 0)) {