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WIP: rework 2.LO + add dwell time
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33 changed files with 483 additions and 190 deletions
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@ -32,7 +32,6 @@ static constexpr uint32_t TCXOFrequency = 26000000;
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static constexpr uint32_t ExtRefInFrequency = 10000000;
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static constexpr uint32_t ExtRefOut1Frequency = 10000000;
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static constexpr uint32_t ExtRefOut2Frequency = 10000000;
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static constexpr uint32_t SI5351CPLLAlignedFrequency = 832000000;
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static constexpr uint32_t SI5351CPLLConstantFrequency = 800000000;
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static constexpr uint32_t FPGAClkInFrequency = 16000000;
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static constexpr uint32_t DefaultADCSamplerate = 800000;
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@ -41,8 +40,12 @@ static constexpr uint32_t DefaultIF2 = 250000;
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static constexpr uint32_t LO1_minFreq = 25000000;
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static constexpr uint32_t MaxSamples = 130944;
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static constexpr uint32_t MinSamples = 16;
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static constexpr uint32_t PLLRef = 104000000;
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static constexpr uint32_t PLLRef = 100000000;
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static constexpr uint32_t BandSwitchFrequency = 25000000;
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static constexpr uint32_t DefaultLO2 = DefaultIF1 - DefaultIF2;
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static constexpr uint8_t LO2Multiplier = 13;
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static constexpr uint32_t SI5351CPLLAlignedFrequency = DefaultLO2 * LO2Multiplier;
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static constexpr uint16_t DefaultDwellTime = 60;
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static constexpr uint8_t DefaultADCprescaler = FPGA::Clockrate / DefaultADCSamplerate;
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static_assert(DefaultADCprescaler * DefaultADCSamplerate == FPGA::Clockrate, "ADCSamplerate can not be reached exactly");
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@ -84,6 +87,8 @@ static constexpr Protocol::DeviceInfo Info = {
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.limits_maxAmplitudePoints = Cal::maxPoints,
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.limits_maxFreqHarmonic = 18000000000,
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.num_ports = 2,
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.limits_minDwellTime = 0,
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.limits_maxDwellTime = 10239,
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};
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enum class Mode {
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@ -127,10 +132,12 @@ namespace Ref {
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// reference won't change until update is called
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void set(Protocol::ReferenceSettings s);
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void update();
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Si5351C::PLLSource getSource();
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}
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// Acquisition frequency settings
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void setAcquisitionFrequencies(Protocol::DeviceConfig s);
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Protocol::DeviceConfig getDeviceConfig();
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uint32_t getIF1();
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uint32_t getIF2();
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uint32_t getADCRate();
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