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WIP: rework 2.LO + add dwell time

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This commit is contained in:
Jan Käberich 2025-01-02 19:16:53 +01:00
parent a2abc0c2af
commit 24314e2361
33 changed files with 483 additions and 190 deletions
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29
FPGA/VNA/MCP33131.vhd
View file

@ -53,6 +53,8 @@ architecture Behavioral of MCP33131 is
signal adc_data : std_logic_vector(15 downto 0);
type States is (Idle, Conversion, WAIT_tEN, Transmission, Done);
signal state : States;
signal ready_int : std_logic;
signal ready_delay : integer range 0 to 30;
signal min_int, max_int, data_int : signed(15 downto 0);
begin
@ -61,7 +63,7 @@ begin
DATA <= std_logic_vector(data_int);
SCLK <= sclk_phase;
process(SCLK)
process(SCLK, START)
begin
if(falling_edge(SCLK)) then
adc_data <= adc_data(14 downto 0) & SDO;
@ -74,6 +76,7 @@ begin
if(RESET = '1') then
state <= Idle;
READY <= '0';
ready_int <= '0';
CONVSTART <= '0';
sclk_phase <= '0';
CONVSTART <= '0';
@ -94,16 +97,30 @@ begin
max_int <= data_int;
end if;
end if;
READY <= '0';
if ready_int = '1' then
ready_delay <= 3;
else
if ready_delay > 0 then
ready_delay <= ready_delay - 1;
end if;
if ready_delay = 1 then
READY <= '1';
data_int <= signed(adc_data);
end if;
end if;
case state is
when Idle =>
READY <= '0';
bit_cnt <= 0;
ready_int <= '0';
if START = '1' then
state <= Conversion;
conv_cnt <= 0;
CONVSTART <= '1';
end if;
when Conversion =>
ready_int <= '0';
if(conv_cnt < CONVCYCLES-1) then
conv_cnt <= conv_cnt + 1;
else
@ -112,8 +129,10 @@ begin
state <= WAIT_tEN;
end if;
when WAIT_tEN =>
ready_int <= '0';
state <= Transmission;
when Transmission =>
ready_int <= '0';
if(div_cnt < (CLK_DIV/2)-1) then
div_cnt <= div_cnt + 1;
else
@ -123,6 +142,7 @@ begin
sclk_phase <= '0';
if bit_cnt = 15 then
state <= Done;
bit_cnt <= 0;
else
bit_cnt <= bit_cnt + 1;
end if;
@ -130,8 +150,7 @@ begin
div_cnt <= 0;
end if;
when Done =>
data_int <= signed(adc_data);
READY <= '1';
ready_int <= '1';
state <= Idle;
end case;
end if;

3
FPGA/VNA/SPIConfig.vhd
View file

@ -51,6 +51,7 @@ entity SPICommands is
SWEEP_POINTS : out STD_LOGIC_VECTOR (12 downto 0);
NSAMPLES : out STD_LOGIC_VECTOR (12 downto 0);
STAGES : out STD_LOGIC_VECTOR (2 downto 0);
SETTLING_TIME : out STD_LOGIC_VECTOR (19 downto 0);
SYNC_ENABLED : out STD_LOGIC;
SYNC_MASTER : out STD_LOGIC;
PORT1_STAGE : out STD_LOGIC_VECTOR (2 downto 0);
@ -270,6 +271,8 @@ begin
when 15 => MAX2871_DEF_4(31 downto 16) <= spi_buf_out;
when 18 => DFT_BIN1_PHASEINC <= spi_buf_out;
when 19 => DFT_DIFFBIN_PHASEINC <= spi_buf_out;
when 20 => SETTLING_TIME(15 downto 0) <= spi_buf_out;
when 21 => SETTLING_TIME(19 downto 16) <= spi_buf_out(3 downto 0);
when others =>
end case;
selected_register <= selected_register + 1;

18
FPGA/VNA/Sweep.vhd
View file

@ -37,6 +37,7 @@ entity Sweep is
CONFIG_DATA : in STD_LOGIC_VECTOR (95 downto 0);
USER_NSAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
NSAMPLES : out STD_LOGIC_VECTOR (12 downto 0);
SETTLING_TIME : in STD_LOGIC_VECTOR (19 downto 0);
SAMPLING_BUSY : in STD_LOGIC;
SAMPLING_DONE : in STD_LOGIC;
START_SAMPLING : out STD_LOGIC;
@ -92,8 +93,7 @@ architecture Behavioral of Sweep is
signal point_cnt : unsigned(12 downto 0);
type Point_states is (WaitInitialLow, TriggerSetup, SettingUp, Settling, WaitTriggerHigh, Exciting, WaitTriggerLow, SamplingDone, NextPoint, Done);
signal state : Point_states;
signal settling_cnt : unsigned(15 downto 0);
signal settling_time : unsigned(15 downto 0);
signal settling_cnt : unsigned(19 downto 0);
signal stage_cnt : unsigned (2 downto 0);
signal config_reg : std_logic_vector(95 downto 0);
signal source_active : std_logic;
@ -103,7 +103,7 @@ begin
-- assemble registers
-- source register 0: N divider and fractional division value
SOURCE_REG_0 <= MAX2871_DEF_0(31) & "0000000000" & config_reg(5 downto 0) & config_reg(26 downto 15) & "000";
SOURCE_REG_0 <= MAX2871_DEF_0(31) & "000000000" & config_reg(93) & config_reg(5 downto 0) & config_reg(26 downto 15) & "000";
-- source register 1: Modulus value
SOURCE_REG_1 <= MAX2871_DEF_1(31 downto 15) & config_reg(38 downto 27) & "001";
-- source register 3: VCO selection
@ -112,7 +112,7 @@ begin
SOURCE_REG_4 <= MAX2871_DEF_4(31 downto 23) & config_reg(14 downto 12) & MAX2871_DEF_4(19 downto 9) & "000" & MAX2871_DEF_4(5) & config_reg(47 downto 46) & "100";
-- LO register 0: N divider and fractional division value
LO_REG_0 <= MAX2871_DEF_0(31) & "0000000000" & config_reg(54 downto 49) & config_reg(75 downto 64) & "000";
LO_REG_0 <= MAX2871_DEF_0(31) & "000000000" & config_reg(94) & config_reg(54 downto 49) & config_reg(75 downto 64) & "000";
-- LO register 1: Modulus value
LO_REG_1 <= MAX2871_DEF_1(31 downto 15) & config_reg(87 downto 76) & "001";
-- LO register 3: VCO selection
@ -184,13 +184,7 @@ begin
-- highest bit in config_reg determines whether the sweep should be halted prior to sampling
SWEEP_HALTED <= config_reg(95);
RELOAD_PLL_REGS <= '0';
case config_reg(94 downto 93) is
when "00" => settling_time <= to_unsigned(2048, 16); -- 20us
when "01" => settling_time <= to_unsigned(6144, 16); -- 60us
when "10" => settling_time <= to_unsigned(18432, 16); -- 180us
when others => settling_time <= to_unsigned(55296, 16); -- 540us
end case;
settling_cnt <= settling_time;
settling_cnt <= unsigned(SETTLING_TIME);
if PLL_RELOAD_DONE = '1' and PLL_LOCKED = '1' then
-- check if halted sweep is resumed
if config_reg(95) = '0' or SWEEP_RESUME = '1' then
@ -257,7 +251,7 @@ begin
else
state <= NextPoint;
end if;
settling_cnt <= settling_time;
settling_cnt <= unsigned(SETTLING_TIME);
when NextPoint =>
NEW_DATA <= '0';
if point_cnt < unsigned(NPOINTS) then

4
FPGA/VNA/Test_SPI.vhd
View file

@ -67,8 +67,8 @@ ARCHITECTURE behavior OF Test_SPI IS
signal COMPLETE : std_logic;
-- Clock period definitions
constant CLK_period : time := 10 ns;
constant SPI_CLK_period : time := 100 ns;
constant CLK_period : time := 9.765625 ns;
constant SPI_CLK_period : time := 25 ns;
signal data_signal : std_logic_vector(15 downto 0);

97
FPGA/VNA/Test_SPICommands.vhd
View file

@ -41,33 +41,63 @@ ARCHITECTURE behavior OF Test_SPICommands IS
COMPONENT SPICommands
PORT(
CLK : IN std_logic;
RESET : IN std_logic;
SCLK : IN std_logic;
MOSI : IN std_logic;
MISO : OUT std_logic;
NSS : IN std_logic;
NEW_SAMPLING_DATA : IN std_logic;
SAMPLING_RESULT : IN std_logic_vector(303 downto 0);
SOURCE_UNLOCKED : IN std_logic;
LO_UNLOCKED : IN std_logic;
MAX2871_DEF_4 : OUT std_logic_vector(31 downto 0);
MAX2871_DEF_3 : OUT std_logic_vector(31 downto 0);
MAX2871_DEF_1 : OUT std_logic_vector(31 downto 0);
MAX2871_DEF_0 : OUT std_logic_vector(31 downto 0);
SWEEP_DATA : OUT std_logic_vector(95 downto 0);
SWEEP_ADDRESS : OUT std_logic_vector(12 downto 0);
SWEEP_WRITE : OUT std_logic_vector(0 downto 0);
SWEEP_POINTS : OUT std_logic_vector(12 downto 0);
NSAMPLES : OUT std_logic_vector(12 downto 0);
PORT1_EN : OUT std_logic;
PORT2_EN : OUT std_logic;
REF_EN : OUT std_logic;
AMP_SHDN : OUT std_logic;
SOURCE_RF_EN : OUT std_logic;
LO_RF_EN : OUT std_logic;
LEDS : OUT std_logic_vector(2 downto 0);
INTERRUPT_ASSERTED : OUT std_logic
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
SCLK : in STD_LOGIC;
MOSI : in STD_LOGIC;
MISO : out STD_LOGIC;
NSS : in STD_LOGIC;
NEW_SAMPLING_DATA : in STD_LOGIC;
SAMPLING_RESULT : in STD_LOGIC_VECTOR (303 downto 0);
ADC_MINMAX : in STD_LOGIC_VECTOR(95 downto 0);
SOURCE_UNLOCKED : in STD_LOGIC;
LO_UNLOCKED : in STD_LOGIC;
MAX2871_DEF_4 : out STD_LOGIC_VECTOR (31 downto 0);
MAX2871_DEF_3 : out STD_LOGIC_VECTOR (31 downto 0);
MAX2871_DEF_1 : out STD_LOGIC_VECTOR (31 downto 0);
MAX2871_DEF_0 : out STD_LOGIC_VECTOR (31 downto 0);
SWEEP_DATA : out STD_LOGIC_VECTOR (95 downto 0);
SWEEP_ADDRESS : out STD_LOGIC_VECTOR (12 downto 0);
SWEEP_WRITE : out STD_LOGIC_VECTOR (0 downto 0);
SWEEP_POINTS : out STD_LOGIC_VECTOR (12 downto 0);
NSAMPLES : out STD_LOGIC_VECTOR (12 downto 0);
STAGES : out STD_LOGIC_VECTOR (2 downto 0);
SETTLING_TIME : out STD_LOGIC_VECTOR (19 downto 0);
SYNC_ENABLED : out STD_LOGIC;
SYNC_MASTER : out STD_LOGIC;
PORT1_STAGE : out STD_LOGIC_VECTOR (2 downto 0);
PORT2_STAGE : out STD_LOGIC_VECTOR (2 downto 0);
PORT1_EN : out STD_LOGIC;
PORT2_EN : out STD_LOGIC;
REF_EN : out STD_LOGIC;
AMP_SHDN : out STD_LOGIC;
SOURCE_RF_EN : out STD_LOGIC;
LO_RF_EN : out STD_LOGIC;
SOURCE_CE_EN : out STD_LOGIC;
LO_CE_EN : out STD_LOGIC;
PORTSWITCH_EN : out STD_LOGIC;
LEDS : out STD_LOGIC_VECTOR(2 downto 0);
WINDOW_SETTING : out STD_LOGIC_VECTOR(1 downto 0);
ADC_PRESCALER : out STD_LOGIC_VECTOR(7 downto 0);
ADC_PHASEINC : out STD_LOGIC_VECTOR(11 downto 0);
INTERRUPT_ASSERTED : out STD_LOGIC;
RESET_MINMAX : out STD_LOGIC;
SWEEP_HALTED : in STD_LOGIC;
SWEEP_RESUME : out STD_LOGIC;
-- hardware overwrite signals
SPI_OVERWRITE_ENABLED : out STD_LOGIC;
SPI_OVERWRITE_DATA : out STD_LOGIC_VECTOR(14 downto 0);
-- DFT signals
DFT_BIN1_PHASEINC : out STD_LOGIC_VECTOR (15 downto 0);
DFT_DIFFBIN_PHASEINC : out STD_LOGIC_VECTOR (15 downto 0);
DFT_RESULT_READY : in STD_LOGIC;
DFT_OUTPUT : in STD_LOGIC_VECTOR (191 downto 0);
DFT_NEXT_OUTPUT : out STD_LOGIC;
DFT_ENABLE : out STD_LOGIC;
DEBUG_STATUS : in STD_LOGIC_VECTOR(10 downto 0)
);
END COMPONENT;
@ -104,8 +134,8 @@ ARCHITECTURE behavior OF Test_SPICommands IS
signal INTERRUPT_ASSERTED : std_logic;
-- Clock period definitions
constant CLK_period : time := 6.25 ns;
constant SPI_CLK_period : time := 100 ns;
constant CLK_period : time := 9.765625 ns;
constant SPI_CLK_period : time := 23.52941176 ns;
signal data_signal : std_logic_vector(15 downto 0);
BEGIN
@ -120,6 +150,7 @@ BEGIN
NSS => NSS,
NEW_SAMPLING_DATA => NEW_SAMPLING_DATA,
SAMPLING_RESULT => SAMPLING_RESULT,
ADC_MINMAX => (others => '0'),
SOURCE_UNLOCKED => SOURCE_UNLOCKED,
LO_UNLOCKED => LO_UNLOCKED,
MAX2871_DEF_4 => MAX2871_DEF_4,
@ -138,7 +169,11 @@ BEGIN
SOURCE_RF_EN => SOURCE_RF_EN,
LO_RF_EN => LO_RF_EN,
LEDS => LEDS,
INTERRUPT_ASSERTED => INTERRUPT_ASSERTED
INTERRUPT_ASSERTED => INTERRUPT_ASSERTED,
SWEEP_HALTED => '0',
DFT_RESULT_READY => '0',
DFT_OUTPUT => (others => '0'),
DEBUG_STATUS => (others => '0')
);
-- Clock process definitions
@ -259,7 +294,7 @@ BEGIN
RESET <= '0';
wait for CLK_period*10;
NSS <= '0';
SPI("1100000000000000");
SPI("0100000000000000");
SPI("0000000000000000");
NSS <= '1';

75
FPGA/VNA/VNA.gise
View file

@ -41,11 +41,11 @@
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Synchronizer.vhi"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_DFT_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MAX2871_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_MCP33131_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MCP33131_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_MCP33131_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_PLL_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_SPICommands_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPICommands_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_SPICommands_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPI_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sampling_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SinCos_isim_beh.exe"/>
@ -137,7 +137,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1708955295" xil_pn:in_ck="-3235419683908193302" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1708955295">
<transform xil_pn:end_ts="1735841254" xil_pn:in_ck="-3235419683908193302" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1735841254">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
@ -167,15 +167,15 @@
<outfile xil_pn:name="top.vhd"/>
<outfile xil_pn:name="window.vhd"/>
</transform>
<transform xil_pn:end_ts="1708955295" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-1206566934435318832" xil_pn:start_ts="1708955295">
<transform xil_pn:end_ts="1735841278" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="9011583378592605907" xil_pn:start_ts="1735841278">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1708955295" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-273551377395144626" xil_pn:start_ts="1708955295">
<transform xil_pn:end_ts="1735841278" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="2919554697640690001" xil_pn:start_ts="1735841278">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1708955295" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1708955295">
<transform xil_pn:end_ts="1735834278" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1735834278">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
@ -188,7 +188,7 @@
<outfile xil_pn:name="ipcore_dir/result_bram.ngc"/>
<outfile xil_pn:name="ipcore_dir/result_bram.vhd"/>
</transform>
<transform xil_pn:end_ts="1708955295" xil_pn:in_ck="-9185925483828391381" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1708955295">
<transform xil_pn:end_ts="1735841254" xil_pn:in_ck="-9185925483828391381" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1735841254">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
@ -224,7 +224,7 @@
<outfile xil_pn:name="top.vhd"/>
<outfile xil_pn:name="window.vhd"/>
</transform>
<transform xil_pn:end_ts="1708955298" xil_pn:in_ck="-9185925483828391381" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-3530939538078141760" xil_pn:start_ts="1708955295">
<transform xil_pn:end_ts="1735841280" xil_pn:in_ck="-9185925483828391381" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8439971377188504826" xil_pn:start_ts="1735841278">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
@ -232,32 +232,32 @@
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="Test_MCP33131_beh.prj"/>
<outfile xil_pn:name="Test_MCP33131_isim_beh.exe"/>
<outfile xil_pn:name="Test_SPICommands_beh.prj"/>
<outfile xil_pn:name="Test_SPICommands_isim_beh.exe"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1708955298" xil_pn:in_ck="4191604156099045257" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="6352116336892055917" xil_pn:start_ts="1708955298">
<transform xil_pn:end_ts="1735841280" xil_pn:in_ck="4191604156099045257" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-6574364550222252173" xil_pn:start_ts="1735841280">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="Test_MCP33131_isim_beh.wdb"/>
<outfile xil_pn:name="Test_SPICommands_isim_beh.wdb"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
</transform>
<transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1600270761">
<transform xil_pn:end_ts="1735835257" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1735835257">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6623951845608321876" xil_pn:start_ts="1600270761">
<transform xil_pn:end_ts="1735835257" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6623951845608321876" xil_pn:start_ts="1735835257">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1708953094" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1708953094">
<transform xil_pn:end_ts="1735835257" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1735835257">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
@ -270,27 +270,29 @@
<outfile xil_pn:name="ipcore_dir/result_bram.ngc"/>
<outfile xil_pn:name="ipcore_dir/result_bram.vhd"/>
</transform>
<transform xil_pn:end_ts="1600270761" xil_pn:in_ck="277585929807082169" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1600270761">
<transform xil_pn:end_ts="1735835257" xil_pn:in_ck="-2664127494180108140" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1735835257">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-9042377951913232490" xil_pn:start_ts="1600270761">
<transform xil_pn:end_ts="1735835257" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-9042377951913232490" xil_pn:start_ts="1735835257">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1600270761" xil_pn:in_ck="277585929807082169" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1600270761">
<transform xil_pn:end_ts="1735835257" xil_pn:in_ck="-2664127494180108140" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1735835257">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="6527189854873920525" xil_pn:start_ts="1600270761">
<transform xil_pn:end_ts="1735835257" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="6527189854873920525" xil_pn:start_ts="1735835257">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1708958126" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1708958116">
<transform xil_pn:end_ts="1735840845" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1735840834">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="top.lso"/>
@ -304,23 +306,33 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1708952937" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1708952937">
<transform xil_pn:end_ts="1735839469" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1735839469">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1708958131" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1708958126">
<transform xil_pn:end_ts="1735840849" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1735840845">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="top.bld"/>
<outfile xil_pn:name="top.ngd"/>
<outfile xil_pn:name="top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1708958154" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1708958131">
<transform xil_pn:end_ts="1735840960" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1735840849">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="top.pcf"/>
<outfile xil_pn:name="top_map.map"/>
@ -331,9 +343,12 @@
<outfile xil_pn:name="top_summary.xml"/>
<outfile xil_pn:name="top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1708958170" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1708958154">
<transform xil_pn:end_ts="1735840975" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1735840960">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="top.ncd"/>
<outfile xil_pn:name="top.pad"/>
@ -345,9 +360,10 @@
<outfile xil_pn:name="top_pad.txt"/>
<outfile xil_pn:name="top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1708958180" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1708958170">
<transform xil_pn:end_ts="1735840985" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1735840975">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="top.bgn"/>
<outfile xil_pn:name="top.bin"/>
@ -362,6 +378,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
@ -372,6 +389,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
@ -383,6 +401,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
@ -394,13 +413,17 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform>
<transform xil_pn:end_ts="1708958170" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1708958166">
<transform xil_pn:end_ts="1735840975" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1735840971">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="top.twr"/>
<outfile xil_pn:name="top.twx"/>

18
FPGA/VNA/VNA.xise
View file

@ -23,11 +23,11 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="MCP33131.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="Test_MCP33131.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
@ -55,11 +55,11 @@
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="spi_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="SPIConfig.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="Sweep.vhd" xil_pn:type="FILE_VHDL">
@ -77,7 +77,7 @@
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="77"/>
</file>
<file xil_pn:name="Test_SPICommands.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="115"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="115"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="115"/>
@ -405,8 +405,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_MCP33131" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_MCP33131" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_SPICommands" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_SPICommands" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@ -424,7 +424,7 @@
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Test_MCP33131" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Test_SPICommands" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@ -476,7 +476,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_MCP33131|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_SPICommands|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="VNA" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

BIN
FPGA/VNA/top.bin
View file

Binary file not shown.

5
FPGA/VNA/top.ucf
View file

@ -1,6 +1,9 @@
CONFIG VCCAUX = 3.3;
NET "CLK" PERIOD = 62.5 ns HIGH 50%;
NET "MCU_SCK" PERIOD = 25ns HIGH 50%;
NET "MCU_SCK" PERIOD = 23.52941176ns HIGH 50%;
NET "REF_SCLK" PERIOD = 19.5ns HIGH 50%;
NET "PORT1_SCLK" PERIOD = 19.5ns HIGH 50%;
NET "PORT2_SCLK" PERIOD = 19.5ns HIGH 50%;
NET "ATTENUATION[6]" IOSTANDARD = LVCMOS33;
NET "ATTENUATION[5]" IOSTANDARD = LVCMOS33;

6
FPGA/VNA/top.vhd
View file

@ -116,6 +116,7 @@ architecture Behavioral of top is
CONFIG_DATA : IN std_logic_vector(95 downto 0);
USER_NSAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
NSAMPLES : out STD_LOGIC_VECTOR (12 downto 0);
SETTLING_TIME : in STD_LOGIC_VECTOR (19 downto 0);
SAMPLING_BUSY : in STD_LOGIC;
SAMPLING_DONE : IN std_logic;
MAX2871_DEF_4 : IN std_logic_vector(31 downto 0);
@ -255,6 +256,7 @@ architecture Behavioral of top is
SWEEP_POINTS : OUT std_logic_vector(12 downto 0);
NSAMPLES : OUT std_logic_vector(12 downto 0);
STAGES : out STD_LOGIC_VECTOR (2 downto 0);
SETTLING_TIME : out STD_LOGIC_VECTOR (19 downto 0);
SYNC_ENABLED : out STD_LOGIC;
SYNC_MASTER : out STD_LOGIC;
PORT1_STAGE : out STD_LOGIC_VECTOR (2 downto 0);
@ -406,7 +408,7 @@ architecture Behavioral of top is
signal sweep_trigger_out : std_logic;
-- Configuration signals
signal settling_time : std_logic_vector(15 downto 0);
signal settling_time : std_logic_vector(19 downto 0);
signal def_reg_4 : std_logic_vector(31 downto 0);
signal def_reg_3 : std_logic_vector(31 downto 0);
signal def_reg_1 : std_logic_vector(31 downto 0);
@ -692,6 +694,7 @@ begin
CONFIG_DATA => sweep_config_data,
USER_NSAMPLES => sampling_user_samples,
NSAMPLES => sampling_samples,
SETTLING_TIME => settling_time,
SAMPLING_BUSY => sampling_busy,
SAMPLING_DONE => sampling_done,
START_SAMPLING => sampling_start,
@ -801,6 +804,7 @@ begin
SWEEP_HALTED => sweep_halted,
SWEEP_RESUME => sweep_resume,
STAGES => sweep_stages,
SETTLING_TIME => settling_time,
SYNC_ENABLED => sweep_sync_enabled,
SYNC_MASTER => sweep_sync_master,
PORT1_STAGE => sweep_port1_stage,