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Some contextual cleanups.

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This commit is contained in:
Jonathan Naylor 2021-09-14 20:53:41 +01:00
parent 023462a86d
commit 92597e0d00
1 changed files with 41 additions and 56 deletions
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53
ADF7021.cpp
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@ -54,9 +54,7 @@ uint16_t m_pocsagDev;
static void Send_AD7021_control_shift()
{
int AD7021_counter;
for(AD7021_counter = 31; AD7021_counter >= 0; AD7021_counter--) {
for (int AD7021_counter = 31; AD7021_counter >= 0; AD7021_counter--) {
if (bitRead(AD7021_control_word, AD7021_counter) == HIGH)
io.SDATA_pin(HIGH);
else
@ -67,6 +65,7 @@ static void Send_AD7021_control_shift()
io.dlybit();
io.SCLK_pin(LOW);
}
// to keep SDATA signal at defined level when idle (not required)
io.SDATA_pin(LOW);
}
@ -82,10 +81,9 @@ void Send_AD7021_control(bool doSle)
{
Send_AD7021_control_shift();
if (doSle) {
if (doSle)
Send_AD7021_control_slePulse();
}
}
#if defined(DUPLEX)
static void Send_AD7021_control_sle2Pulse()
@ -99,10 +97,9 @@ void Send_AD7021_control2(bool doSle)
{
Send_AD7021_control_shift();
if (doSle) {
if (doSle)
Send_AD7021_control_sle2Pulse();
}
}
#endif
#if defined(SEND_RSSI_DATA)
@ -110,14 +107,13 @@ uint16_t CIO::readRSSI()
{
uint32_t AD7021_RB;
uint16_t RB_word = 0U;
int AD7021_counter;
uint8_t RB_code, gain_code, gain_corr;
// Register 7, readback enable, ADC RSSI mode
AD7021_RB = 0x0147;
// Send control register
for(AD7021_counter = 8; AD7021_counter >= 0; AD7021_counter--) {
for (int AD7021_counter = 8; AD7021_counter >= 0; AD7021_counter--) {
if (bitRead(AD7021_RB, AD7021_counter) == HIGH)
SDATA_pin(HIGH);
else
@ -143,7 +139,7 @@ uint16_t CIO::readRSSI()
dlybit();
// Read SREAD pin
for(AD7021_counter = 17; AD7021_counter >= 0; AD7021_counter--) {
for (int AD7021_counter = 17; AD7021_counter >= 0; AD7021_counter--) {
SCLK_pin(HIGH);
dlybit();
@ -152,7 +148,6 @@ uint16_t CIO::readRSSI()
SCLK_pin(LOW);
dlybit();
}
#if defined(DUPLEX)
@ -234,20 +229,16 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
if ((m_frequency_tx >= VHF1_MIN) && (m_frequency_tx < VHF1_MAX)) {
ADF7021_REG1 = ADF7021_REG1_VHF1; // VHF1, external VCO
div2 = 1U;
}
else if( (m_frequency_tx >= VHF2_MIN) && (m_frequency_tx < VHF2_MAX) ) {
} else if ((m_frequency_tx >= VHF2_MIN) && (m_frequency_tx < VHF2_MAX)) {
ADF7021_REG1 = ADF7021_REG1_VHF2; // VHF1, external VCO
div2 = 1U;
}
else if( (m_frequency_tx >= UHF1_MIN)&&(m_frequency_tx < UHF1_MAX) ) {
} else if ((m_frequency_tx >= UHF1_MIN)&&(m_frequency_tx < UHF1_MAX)) {
ADF7021_REG1 = ADF7021_REG1_UHF1; // UHF1, internal VCO
div2 = 1U;
}
else if( (m_frequency_tx >= UHF2_MIN)&&(m_frequency_tx < UHF2_MAX) ) {
} else if ((m_frequency_tx >= UHF2_MIN)&&(m_frequency_tx < UHF2_MAX)) {
ADF7021_REG1 = ADF7021_REG1_UHF2; // UHF2, internal VCO
div2 = 2U;
}
else {
} else {
ADF7021_REG1 = ADF7021_REG1_UHF1; // UHF1, internal VCO
div2 = 1U;
}
@ -424,7 +415,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
break;
case STATE_YSF:
// Dev: +1 symb 900 Hz, symb rate = 4800
// Dev: +1 symb 900/450 Hz, symb rate = 4800
ADF7021_REG3 = (m_LoDevYSF ? ADF7021_REG3_YSF_L : ADF7021_REG3_YSF_H);
ADF7021_REG10 = ADF7021_REG10_YSF;
@ -685,7 +676,7 @@ void CIO::ifConf2(MMDVM_STATE modemState)
break;
case STATE_YSF:
// Dev: +1 symb 2700/900 Hz, symb rate = 4800
// Dev: +1 symb 900/450 Hz, symb rate = 4800
ADF7021_REG3 = (m_LoDevYSF ? ADF7021_REG3_YSF_L : ADF7021_REG3_YSF_H);
ADF7021_REG10 = ADF7021_REG10_YSF;
@ -862,15 +853,13 @@ void CIO::interrupt()
// possibly this is a design problem of the RF7021 board or too long wires
// on the breadboard build
// but normally this will not hurt too much
if (clk == last_clk) {
if (clk == last_clk)
return;
} else {
else
last_clk = clk;
}
// we set the TX bit at TXD low, sampling of ADF7021 happens at rising clock
if (m_tx && clk == 0U) {
m_txBuffer.get(bit, m_control);
even = !even;
@ -920,7 +909,7 @@ void CIO::interrupt()
m_rxBuffer.put(bit, m_control);
}
if (torx_request == true && even == ADF7021_EVEN_BIT && m_tx && clk == 0U) {
if (torx_request && even == ADF7021_EVEN_BIT && m_tx && clk == 0U) {
// that is absolutely crucial in 4FSK, see datasheet:
// enable sle after 1/4 tBit == 26uS when sending MSB (even == false) and clock is low
delay_us(26U);
@ -1039,20 +1028,16 @@ void CIO::updateCal()
if ((m_frequency_tx >= VHF1_MIN) && (m_frequency_tx < VHF1_MAX)) {
ADF7021_REG1 = ADF7021_REG1_VHF1; // VHF1, external VCO
div2 = 1U;
}
else if( (m_frequency_tx >= VHF2_MIN) && (m_frequency_tx < VHF2_MAX) ) {
} else if ((m_frequency_tx >= VHF2_MIN) && (m_frequency_tx < VHF2_MAX)) {
ADF7021_REG1 = ADF7021_REG1_VHF2; // VHF1, external VCO
div2 = 1U;
}
else if( (m_frequency_tx >= UHF1_MIN)&&(m_frequency_tx < UHF1_MAX) ) {
} else if ((m_frequency_tx >= UHF1_MIN)&&(m_frequency_tx < UHF1_MAX)) {
ADF7021_REG1 = ADF7021_REG1_UHF1; // UHF1, internal VCO
div2 = 1U;
}
else if( (m_frequency_tx >= UHF2_MIN)&&(m_frequency_tx < UHF2_MAX) ) {
} else if ((m_frequency_tx >= UHF2_MIN)&&(m_frequency_tx < UHF2_MAX)) {
ADF7021_REG1 = ADF7021_REG1_UHF2; // UHF2, internal VCO
div2 = 2U;
}
else {
} else {
ADF7021_REG1 = ADF7021_REG1_UHF1; // UHF1, internal VCO
div2 = 1U;
}