diff --git a/ADF7021.cpp b/ADF7021.cpp
index 500720b..8ec86de 100644
--- a/ADF7021.cpp
+++ b/ADF7021.cpp
@@ -54,10 +54,8 @@ uint16_t           m_pocsagDev;
 
 static void Send_AD7021_control_shift()
 {
-  int AD7021_counter;
-
-  for(AD7021_counter = 31; AD7021_counter >= 0; AD7021_counter--) {
-    if(bitRead(AD7021_control_word, AD7021_counter) == HIGH)
+  for (int AD7021_counter = 31; AD7021_counter >= 0; AD7021_counter--) {
+    if (bitRead(AD7021_control_word, AD7021_counter) == HIGH)
       io.SDATA_pin(HIGH);
     else
       io.SDATA_pin(LOW);
@@ -67,6 +65,7 @@ static void Send_AD7021_control_shift()
     io.dlybit();
     io.SCLK_pin(LOW);
   }
+
   // to keep SDATA signal at defined level when idle (not required)
   io.SDATA_pin(LOW);
 }
@@ -82,9 +81,8 @@ void Send_AD7021_control(bool doSle)
 {
   Send_AD7021_control_shift();
 
-  if (doSle) {
+  if (doSle)
     Send_AD7021_control_slePulse();
-  }
 }
 
 #if defined(DUPLEX)
@@ -99,9 +97,8 @@ void Send_AD7021_control2(bool doSle)
 {
   Send_AD7021_control_shift();
 
-  if (doSle) {
+  if (doSle)
     Send_AD7021_control_sle2Pulse();
-  }
 }
 #endif
 
@@ -110,15 +107,14 @@ uint16_t CIO::readRSSI()
 {
   uint32_t AD7021_RB;
   uint16_t RB_word = 0U;
-  int AD7021_counter;
   uint8_t RB_code, gain_code, gain_corr;
 
   // Register 7, readback enable, ADC RSSI mode
   AD7021_RB = 0x0147;
 
   // Send control register
-  for(AD7021_counter = 8; AD7021_counter >= 0; AD7021_counter--) {
-    if(bitRead(AD7021_RB, AD7021_counter) == HIGH)
+  for (int AD7021_counter = 8; AD7021_counter >= 0; AD7021_counter--) {
+    if (bitRead(AD7021_RB, AD7021_counter) == HIGH)
       SDATA_pin(HIGH);
     else
       SDATA_pin(LOW);
@@ -143,16 +139,15 @@ uint16_t CIO::readRSSI()
   dlybit();
 
   // Read SREAD pin
-  for(AD7021_counter = 17; AD7021_counter >= 0; AD7021_counter--) {
+  for (int AD7021_counter = 17; AD7021_counter >= 0; AD7021_counter--) {
     SCLK_pin(HIGH);
     dlybit();
 
-    if( (AD7021_counter != 17) && (AD7021_counter != 0) )
-      RB_word |= ( (SREAD_pin() & 0x01) << (AD7021_counter-1) );
+    if ((AD7021_counter != 17) && (AD7021_counter != 0))
+      RB_word |= ((SREAD_pin() & 0x01) << (AD7021_counter - 1));
 
     SCLK_pin(LOW);
     dlybit();
-
   }
 
 #if defined(DUPLEX)
@@ -223,7 +218,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
   #endif
 
   // Toggle CE pin for ADF7021 reset
-  if(reset) {
+  if (reset) {
     CE_pin(LOW);
     delay_reset();
     CE_pin(HIGH);
@@ -231,28 +226,24 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
   }
 
   // Check frequency band
-  if( (m_frequency_tx >= VHF1_MIN) && (m_frequency_tx < VHF1_MAX) ) {
+  if ((m_frequency_tx >= VHF1_MIN) && (m_frequency_tx < VHF1_MAX)) {
     ADF7021_REG1 = ADF7021_REG1_VHF1;         // VHF1, external VCO
     div2 = 1U;
-  }
-  else if( (m_frequency_tx >= VHF2_MIN) && (m_frequency_tx < VHF2_MAX) ) {
+  } else if ((m_frequency_tx >= VHF2_MIN) && (m_frequency_tx < VHF2_MAX)) {
     ADF7021_REG1 = ADF7021_REG1_VHF2;         // VHF1, external VCO
     div2 = 1U;
-  }
-  else if( (m_frequency_tx >= UHF1_MIN)&&(m_frequency_tx < UHF1_MAX) ) {
+  } else if ((m_frequency_tx >= UHF1_MIN)&&(m_frequency_tx < UHF1_MAX)) {
     ADF7021_REG1 = ADF7021_REG1_UHF1;         // UHF1, internal VCO
     div2 = 1U;
-  }
-  else if( (m_frequency_tx >= UHF2_MIN)&&(m_frequency_tx < UHF2_MAX) ) {
+  } else if ((m_frequency_tx >= UHF2_MIN)&&(m_frequency_tx < UHF2_MAX)) {
     ADF7021_REG1 = ADF7021_REG1_UHF2;         // UHF2, internal VCO
     div2 = 2U;
-  }
-  else {
+  } else {
     ADF7021_REG1 = ADF7021_REG1_UHF1;         // UHF1, internal VCO
     div2 = 1U;
   }
 
-  if(div2 == 1U)
+  if (div2 == 1U)
     f_div = 2U;
   else
     f_div = 1U;
@@ -282,10 +273,10 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
       break;
   }
 
-  if( div2 == 1U )
+  if (div2 == 1U)
     divider = (m_frequency_rx - 100000 + AFC_OFFSET) / (ADF7021_PFD / 2U);
   else
-    divider = (m_frequency_rx - 100000 + (2*AFC_OFFSET)) / ADF7021_PFD;
+    divider = (m_frequency_rx - 100000 + (2 * AFC_OFFSET)) / ADF7021_PFD;
 
   m_RX_N_divider = floor(divider);
   divider = (divider - m_RX_N_divider) * 32768;
@@ -302,7 +293,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
   ADF7021_RX_REG0 |= (uint32_t) m_RX_N_divider << 19;   // frequency;
   ADF7021_RX_REG0 |= (uint32_t) m_RX_F_divider << 4;    // frequency;
 
-  if( div2 == 1U )
+  if (div2 == 1U)
     divider = m_frequency_tx / (ADF7021_PFD / 2U);
   else
     divider = m_frequency_tx / ADF7021_PFD;
@@ -424,7 +415,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
       break;
 
     case STATE_YSF:
-      // Dev: +1 symb 900 Hz, symb rate = 4800
+      // Dev: +1 symb 900/450 Hz, symb rate = 4800
 
       ADF7021_REG3 = (m_LoDevYSF ? ADF7021_REG3_YSF_L : ADF7021_REG3_YSF_H);
       ADF7021_REG10 = ADF7021_REG10_YSF;
@@ -623,7 +614,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
   }
 
 #if defined(DUPLEX)
-if(m_duplex && (modemState != STATE_CWID && modemState != STATE_POCSAG))
+if (m_duplex && (modemState != STATE_CWID && modemState != STATE_POCSAG))
   ifConf2(modemState);
 #endif
 }
@@ -685,7 +676,7 @@ void CIO::ifConf2(MMDVM_STATE modemState)
       break;
 
     case STATE_YSF:
-      // Dev: +1 symb 2700/900 Hz, symb rate = 4800
+      // Dev: +1 symb 900/450 Hz, symb rate = 4800
 
       ADF7021_REG3 = (m_LoDevYSF ? ADF7021_REG3_YSF_L : ADF7021_REG3_YSF_H);
       ADF7021_REG10 = ADF7021_REG10_YSF;
@@ -862,25 +853,23 @@ void CIO::interrupt()
   // possibly this is a design problem of the RF7021 board or too long wires
   // on the breadboard build
   // but normally this will not hurt too much
-  if (clk == last_clk) {
+  if (clk == last_clk)
     return;
-  } else {
+  else
     last_clk = clk;
-  }
 
   // we set the TX bit at TXD low, sampling of ADF7021 happens at rising clock
   if (m_tx && clk == 0U) {
-
     m_txBuffer.get(bit, m_control);
     even = !even;
 
 #if defined(BIDIR_DATA_PIN)
-    if(bit)
+    if (bit)
       RXD_pin_write(HIGH);
     else
       RXD_pin_write(LOW);
 #else
-    if(bit)
+    if (bit)
       TXD_pin(HIGH);
     else
       TXD_pin(LOW);
@@ -912,7 +901,7 @@ void CIO::interrupt()
 
   // we sample the RX bit at rising TXD clock edge, so TXD must be 1 and we are not in tx mode
   if (!m_tx && clk == 1U && !m_duplex) {
-    if(RXD_pin())
+    if (RXD_pin())
       bit = 1U;
     else
       bit = 0U;
@@ -920,7 +909,7 @@ void CIO::interrupt()
     m_rxBuffer.put(bit, m_control);
   }
 
-  if (torx_request == true && even == ADF7021_EVEN_BIT && m_tx && clk == 0U) {
+  if (torx_request && even == ADF7021_EVEN_BIT && m_tx && clk == 0U) {
       // that is absolutely crucial in 4FSK, see datasheet:
       // enable sle after 1/4 tBit == 26uS when sending MSB (even == false) and clock is low
       delay_us(26U);
@@ -946,10 +935,10 @@ void CIO::interrupt()
   m_modeTimerCnt++;
   m_int1counter++;
 
-  if(m_scanPauseCnt >= SCAN_PAUSE)
+  if (m_scanPauseCnt >= SCAN_PAUSE)
     m_scanPauseCnt = 0U;
 
-  if(m_scanPauseCnt != 0U)
+  if (m_scanPauseCnt != 0U)
     m_scanPauseCnt++;
 }
 
@@ -958,8 +947,8 @@ void CIO::interrupt2()
 {
   uint8_t bit = 0U;
 
-  if(m_duplex) {
-    if(RXD2_pin())
+  if (m_duplex) {
+    if (RXD2_pin())
       bit = 1U;
     else
       bit = 0U;
@@ -1003,7 +992,7 @@ void CIO::setRX(bool doSle)
   Data_dir_out(false);  // Data pin input mode
 #endif
 
-  if(!doSle) {
+  if (!doSle) {
     torx_request = true;
     while(torx_request) { asm volatile ("nop"); }
   }
@@ -1036,28 +1025,24 @@ void CIO::updateCal()
   float    divider;
 
   // Check frequency band
-  if( (m_frequency_tx >= VHF1_MIN) && (m_frequency_tx < VHF1_MAX) ) {
+  if ((m_frequency_tx >= VHF1_MIN) && (m_frequency_tx < VHF1_MAX)) {
     ADF7021_REG1 = ADF7021_REG1_VHF1;         // VHF1, external VCO
     div2 = 1U;
-  }
-  else if( (m_frequency_tx >= VHF2_MIN) && (m_frequency_tx < VHF2_MAX) ) {
+  } else if ((m_frequency_tx >= VHF2_MIN) && (m_frequency_tx < VHF2_MAX)) {
     ADF7021_REG1 = ADF7021_REG1_VHF2;         // VHF1, external VCO
     div2 = 1U;
-  }
-  else if( (m_frequency_tx >= UHF1_MIN)&&(m_frequency_tx < UHF1_MAX) ) {
+  } else if ((m_frequency_tx >= UHF1_MIN)&&(m_frequency_tx < UHF1_MAX)) {
     ADF7021_REG1 = ADF7021_REG1_UHF1;         // UHF1, internal VCO
     div2 = 1U;
-  }
-  else if( (m_frequency_tx >= UHF2_MIN)&&(m_frequency_tx < UHF2_MAX) ) {
+  } else if ((m_frequency_tx >= UHF2_MIN)&&(m_frequency_tx < UHF2_MAX)) {
     ADF7021_REG1 = ADF7021_REG1_UHF2;         // UHF2, internal VCO
     div2 = 2U;
-  }
-  else {
+  } else {
     ADF7021_REG1 = ADF7021_REG1_UHF1;         // UHF1, internal VCO
     div2 = 1U;
   }
 
-  if(div2 == 1U)
+  if (div2 == 1U)
     f_div = 2U;
   else
     f_div = 1U;
@@ -1083,7 +1068,7 @@ void CIO::updateCal()
   AD7021_control_word = ADF7021_REG2;
   Send_AD7021_control();
 
-  if( div2 == 1U )
+  if (div2 == 1U)
     divider = m_frequency_tx / (ADF7021_PFD / 2U);
   else
     divider = m_frequency_tx / ADF7021_PFD;