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165 lines
3.2 KiB
C++
165 lines
3.2 KiB
C++
#pragma once
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namespace shader::ir::vop2 {
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enum Op {
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CNDMASK_B32,
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READLANE_B32,
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WRITELANE_B32,
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ADD_F32,
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SUB_F32,
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SUBREV_F32,
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MAC_LEGACY_F32,
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MUL_LEGACY_F32,
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MUL_F32,
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MUL_I32_I24,
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MUL_HI_I32_I24,
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MUL_U32_U24,
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MUL_HI_U32_U24,
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MIN_LEGACY_F32,
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MAX_LEGACY_F32,
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MIN_F32,
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MAX_F32,
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MIN_I32,
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MAX_I32,
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MIN_U32,
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MAX_U32,
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LSHR_B32,
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LSHRREV_B32,
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ASHR_I32,
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ASHRREV_I32,
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LSHL_B32,
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LSHLREV_B32,
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AND_B32,
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OR_B32,
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XOR_B32,
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BFM_B32,
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MAC_F32,
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MADMK_F32,
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MADAK_F32,
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BCNT_U32_B32,
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MBCNT_LO_U32_B32,
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MBCNT_HI_U32_B32,
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ADD_I32,
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SUB_I32,
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SUBREV_I32,
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ADDC_U32,
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SUBB_U32,
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SUBBREV_U32,
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LDEXP_F32,
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CVT_PKACCUM_U8_F32,
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CVT_PKNORM_I16_F32,
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CVT_PKNORM_U16_F32,
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CVT_PKRTZ_F16_F32,
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CVT_PK_U16_U32,
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CVT_PK_I16_I32,
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OpCount
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};
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inline const char *getInstructionName(unsigned id) {
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switch (id) {
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case CNDMASK_B32:
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return "v_cndmask_b32";
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case READLANE_B32:
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return "v_readlane_b32";
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case WRITELANE_B32:
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return "v_writelane_b32";
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case ADD_F32:
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return "v_add_f32";
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case SUB_F32:
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return "v_sub_f32";
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case SUBREV_F32:
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return "v_subrev_f32";
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case MAC_LEGACY_F32:
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return "v_mac_legacy_f32";
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case MUL_LEGACY_F32:
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return "v_mul_legacy_f32";
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case MUL_F32:
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return "v_mul_f32";
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case MUL_I32_I24:
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return "v_mul_i32_i24";
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case MUL_HI_I32_I24:
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return "v_mul_hi_i32_i24";
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case MUL_U32_U24:
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return "v_mul_u32_u24";
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case MUL_HI_U32_U24:
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return "v_mul_hi_u32_u24";
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case MIN_LEGACY_F32:
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return "v_min_legacy_f32";
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case MAX_LEGACY_F32:
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return "v_max_legacy_f32";
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case MIN_F32:
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return "v_min_f32";
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case MAX_F32:
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return "v_max_f32";
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case MIN_I32:
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return "v_min_i32";
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case MAX_I32:
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return "v_max_i32";
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case MIN_U32:
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return "v_min_u32";
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case MAX_U32:
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return "v_max_u32";
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case LSHR_B32:
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return "v_lshr_b32";
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case LSHRREV_B32:
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return "v_lshrrev_b32";
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case ASHR_I32:
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return "v_ashr_i32";
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case ASHRREV_I32:
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return "v_ashrrev_i32";
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case LSHL_B32:
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return "v_lshl_b32";
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case LSHLREV_B32:
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return "v_lshlrev_b32";
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case AND_B32:
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return "v_and_b32";
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case OR_B32:
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return "v_or_b32";
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case XOR_B32:
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return "v_xor_b32";
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case BFM_B32:
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return "v_bfm_b32";
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case MAC_F32:
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return "v_mac_f32";
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case MADMK_F32:
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return "v_madmk_f32";
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case MADAK_F32:
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return "v_madak_f32";
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case BCNT_U32_B32:
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return "v_bcnt_u32_b32";
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case MBCNT_LO_U32_B32:
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return "v_mbcnt_lo_u32_b32";
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case MBCNT_HI_U32_B32:
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return "v_mbcnt_hi_u32_b32";
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case ADD_I32:
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return "v_add_i32";
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case SUB_I32:
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return "v_sub_i32";
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case SUBREV_I32:
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return "v_subrev_i32";
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case ADDC_U32:
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return "v_addc_u32";
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case SUBB_U32:
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return "v_subb_u32";
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case SUBBREV_U32:
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return "v_subbrev_u32";
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case LDEXP_F32:
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return "v_ldexp_f32";
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case CVT_PKACCUM_U8_F32:
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return "v_cvt_pkaccum_u8_f32";
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case CVT_PKNORM_I16_F32:
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return "v_cvt_pknorm_i16_f32";
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case CVT_PKNORM_U16_F32:
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return "v_cvt_pknorm_u16_f32";
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case CVT_PKRTZ_F16_F32:
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return "v_cvt_pkrtz_f16_f32";
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case CVT_PK_U16_U32:
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return "v_cvt_pk_u16_u32";
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case CVT_PK_I16_I32:
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return "v_cvt_pk_i16_i32";
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}
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return nullptr;
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}
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} // namespace shader::ir::vop2
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