elad fc92ae4085 SPU/PPU atomics performance and LR event fixes (#5435) ... * Fix SPU LR event setting in atomic commands according to hw test * MFC: increment timestamp for PUT cmd in non-tsx path * MFC: fix reservation lost test on non-tsx path in regard to the lock bit * Reservation notification moved out of writer_lock scope to reduce its lifetime * Use passive_lock/unlock in ppu atomic inctrustions to reduce redundancy * Lock only once for dma transfers (non-TSX) * Don't use RDTSC in reservation update logic * Remove MFC cmd args passing to process_mfc_cmd * Reorder check_state cpu_flag::memory check for faster unlocking * Specialization for 128-byte data copy in SPU dma transfers * Implement memory range locks and isolate PPU and SPU passive lock logic		2019-01-15 18:31:21 +03:00
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CPUDisAsm.h	SPU ASMJIT v2.0	2018-04-22 00:06:48 +03:00
CPUThread.cpp	SPU/PPU atomics performance and LR event fixes (#5435)	2019-01-15 18:31:21 +03:00
CPUThread.h	Migration to named_thread<>	2018-10-19 22:22:35 +03:00
CPUTranslator.cpp	Update cpu_translator	2018-07-05 22:26:35 +03:00
CPUTranslator.h	cpu: use correct type when defining llvm value is_int constexpr	2018-09-10 19:59:37 +03:00