mirror of
https://github.com/RPCSX/rpcsx.git
synced 2025-12-31 13:50:46 +01:00
861 lines
21 KiB
GLSL
861 lines
21 KiB
GLSL
R"(
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layout(location=0) out vec4 ocol0;
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layout(location=1) out vec4 ocol1;
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layout(location=2) out vec4 ocol2;
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layout(location=3) out vec4 ocol3;
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layout(location=0) in vec4 in_regs[16];
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#define RSX_FP_OPCODE_NOP 0x00 // No-Operation
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#define RSX_FP_OPCODE_MOV 0x01 // Move
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#define RSX_FP_OPCODE_MUL 0x02 // Multiply
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#define RSX_FP_OPCODE_ADD 0x03 // Add
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#define RSX_FP_OPCODE_MAD 0x04 // Multiply-Add
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#define RSX_FP_OPCODE_DP3 0x05 // 3-component Dot Product
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#define RSX_FP_OPCODE_DP4 0x06 // 4-component Dot Product
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#define RSX_FP_OPCODE_DST 0x07 // Distance
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#define RSX_FP_OPCODE_MIN 0x08 // Minimum
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#define RSX_FP_OPCODE_MAX 0x09 // Maximum
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#define RSX_FP_OPCODE_SLT 0x0A // Set-If-LessThan
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#define RSX_FP_OPCODE_SGE 0x0B // Set-If-GreaterEqual
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#define RSX_FP_OPCODE_SLE 0x0C // Set-If-LessEqual
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#define RSX_FP_OPCODE_SGT 0x0D // Set-If-GreaterThan
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#define RSX_FP_OPCODE_SNE 0x0E // Set-If-NotEqual
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#define RSX_FP_OPCODE_SEQ 0x0F // Set-If-Equal
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#define RSX_FP_OPCODE_FRC 0x10 // Fraction (fract)
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#define RSX_FP_OPCODE_FLR 0x11 // Floor
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#define RSX_FP_OPCODE_KIL 0x12 // Kill fragment
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#define RSX_FP_OPCODE_PK4 0x13 // Pack four signed 8-bit values
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#define RSX_FP_OPCODE_UP4 0x14 // Unpack four signed 8-bit values
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#define RSX_FP_OPCODE_DDX 0x15 // Partial-derivative in x (Screen space derivative w.r.t. x)
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#define RSX_FP_OPCODE_DDY 0x16 // Partial-derivative in y (Screen space derivative w.r.t. y)
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#define RSX_FP_OPCODE_TEX 0x17 // Texture lookup
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#define RSX_FP_OPCODE_TXP 0x18 // Texture sample with projection (Projective texture lookup)
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#define RSX_FP_OPCODE_TXD 0x19 // Texture sample with partial differentiation (Texture lookup with derivatives)
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#define RSX_FP_OPCODE_RCP 0x1A // Reciprocal
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#define RSX_FP_OPCODE_RSQ 0x1B // Reciprocal Square Root
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#define RSX_FP_OPCODE_EX2 0x1C // Exponentiation base 2
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#define RSX_FP_OPCODE_LG2 0x1D // Log base 2
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#define RSX_FP_OPCODE_LIT 0x1E // Lighting coefficients
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#define RSX_FP_OPCODE_LRP 0x1F // Linear Interpolation
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#define RSX_FP_OPCODE_STR 0x20 // Set-If-True
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#define RSX_FP_OPCODE_SFL 0x21 // Set-If-False
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#define RSX_FP_OPCODE_COS 0x22 // Cosine
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#define RSX_FP_OPCODE_SIN 0x23 // Sine
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#define RSX_FP_OPCODE_PK2 0x24 // Pack two 16-bit floats
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#define RSX_FP_OPCODE_UP2 0x25 // Unpack two 16-bit floats
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#define RSX_FP_OPCODE_POW 0x26 // Power
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#define RSX_FP_OPCODE_PKB 0x27 // Pack bytes
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#define RSX_FP_OPCODE_UPB 0x28 // Unpack bytes
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#define RSX_FP_OPCODE_PK16 0x29 // Pack 16 bits
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#define RSX_FP_OPCODE_UP16 0x2A // Unpack 16
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#define RSX_FP_OPCODE_BEM 0x2B // Bump-environment map (a.k.a. 2D coordinate transform)
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#define RSX_FP_OPCODE_PKG 0x2C // Pack with sRGB transformation
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#define RSX_FP_OPCODE_UPG 0x2D // Unpack gamma
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#define RSX_FP_OPCODE_DP2A 0x2E // 2-component dot product with scalar addition
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#define RSX_FP_OPCODE_TXL 0x2F // Texture sample with explicit LOD
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#define RSX_FP_OPCODE_TXB 0x31 // Texture sample with bias
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#define RSX_FP_OPCODE_TEXBEM 0x33
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#define RSX_FP_OPCODE_TXPBEM 0x34
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#define RSX_FP_OPCODE_BEMLUM 0x35
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#define RSX_FP_OPCODE_REFL 0x36 // Reflection vector
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#define RSX_FP_OPCODE_TIMESWTEX 0x37
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#define RSX_FP_OPCODE_DP2 0x38 // 2-component dot product
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#define RSX_FP_OPCODE_NRM 0x39 // Normalize
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#define RSX_FP_OPCODE_DIV 0x3A // Division
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#define RSX_FP_OPCODE_DIVSQ 0x3B // Divide by Square Root
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#define RSX_FP_OPCODE_LIF 0x3C // Final part of LIT
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#define RSX_FP_OPCODE_FENCT 0x3D // Fence T?
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#define RSX_FP_OPCODE_FENCB 0x3E // Fence B?
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#define RSX_FP_OPCODE_BRK 0x40 // Break
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#define RSX_FP_OPCODE_CAL 0x41 // Subroutine call
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#define RSX_FP_OPCODE_IFE 0x42 // If
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#define RSX_FP_OPCODE_LOOP 0x43 // Loop
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#define RSX_FP_OPCODE_REP 0x44 // Repeat
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#define RSX_FP_OPCODE_RET 0x45 // Return
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#define EXEC_LT 1
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#define EXEC_EQ 2
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#define EXEC_GT 4
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#define RSX_FP_REGISTER_TYPE_TEMP 0
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#define RSX_FP_REGISTER_TYPE_INPUT 1
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#define RSX_FP_REGISTER_TYPE_CONSTANT 2
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#define RSX_FP_REGISTER_TYPE_UNKNOWN 3
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#define CELL_GCM_SHADER_CONTROL_DEPTH_EXPORT 0xe
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#define CELL_GCM_SHADER_CONTROL_32_BITS_EXPORTS 0x40
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#define GET_BITS(word, offset, count) bitfieldExtract(inst.words[word], offset, count)
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#define TEST_BIT(word, offset) (GET_BITS(word, offset, 1) > 0)
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#define select mix
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#define reg_mov(d, s, m) d = select(d, s, m)
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// GPR set
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vec4 vr0, vr1; // GP vector register
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uint ur0, ur1; // GP unsigned register (scalar)
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uvec4 uvr0; // GP unsigned register (vector)
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bvec4 bvr0, bvr1; // GP boolean register (vector)
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float sr0; // GP scalar register
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vec4 vrr; // value return (dst register)
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vec4 s0, s1, s2; // instruction src (src0, src1, src2)
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vec4 wpos; // window position register WPOS
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vec4 fogc; // Fog coordinate register FOGC
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const vec4 vr_zero = vec4(0.);
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const vec4 vr_one = vec4(1.);
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bool shader_attribute(const in uint mask)
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{
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return (shader_control & mask) != 0;
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}
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vec4 _distance(const in vec4 a, const in vec4 b)
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{
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// Old-school distance vector
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return vec4(1., a.y * b.y, a.z, b.w);
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}
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vec4 shuffle(const in vec4 value, const in uint code)
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{
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switch (code)
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{
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case 0xE4:
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return value;
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case 0x24:
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return value.xyzx;
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case 0xA4:
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return value.xyzz;
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case 0x00:
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return value.xxxx;
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case 0x55:
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return value.yyyy;
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case 0xAA:
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return value.zzzz;
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case 0xFF:
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return value.wwww;
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case 0x04:
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return value.xyxx;
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default:
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uint x = bitfieldExtract(code, 0, 2);
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uint y = bitfieldExtract(code, 2, 2);
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uint z = bitfieldExtract(code, 4, 2);
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uint w = bitfieldExtract(code, 6, 2);
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return vec4(value[x], value[y], value[z], value[w]);
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}
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}
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struct instruction_t
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{
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uvec4 words;
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uint opcode;
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bool end;
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};
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const float modifier_scale[] = {1.f, 2.f, 4.f, 8.f, 1.f, 0.5f, 0.25f, 0.125f};
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vec4 regs16[48];
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vec4 regs32[48];
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vec4 cc[2];
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int inst_length = 1;
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int ip = -1;
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instruction_t inst;
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#ifdef WITH_FLOW_CTRL
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int test_addr = -1;
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int jump_addr = -1;
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int loop_start_addr = -1;
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int loop_end_addr = -1;
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int counter = 0;
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#endif
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vec4 read_src(const in int index)
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{
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ur0 = GET_BITS(index + 1, 0, 2);
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switch (ur0)
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{
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case RSX_FP_REGISTER_TYPE_TEMP:
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{
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switch(index)
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{
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case 0:
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ur1 = GET_BITS(1, 2, 6); break;
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case 1:
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ur1 = GET_BITS(2, 2, 6); break;
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case 2:
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ur1 = GET_BITS(3, 2, 6); break;
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}
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if (TEST_BIT(index + 1, 8))
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{
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vr0 = regs16[ur1];
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}
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else
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{
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vr0 = regs32[ur1];
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}
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break;
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}
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case RSX_FP_REGISTER_TYPE_INPUT:
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{
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ur1 = GET_BITS(0, 13, 4);
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switch (ur1)
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{
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case 0:
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vr0 = wpos; break;
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case 1:
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vr0 = gl_FrontFacing? in_regs[3] : in_regs[1]; break;
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case 2:
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vr0 = gl_FrontFacing? in_regs[4] : in_regs[2]; break;
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case 3:
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vr0 = fogc; break;
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case 13:
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vr0 = in_regs[6]; break;
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case 14:
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vr0 = gl_FrontFacing? vr_one : -vr_one; break;
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default:
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ur1 += 3;
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vr0 = in_regs[ur1]; break;
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}
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break;
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}
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case RSX_FP_REGISTER_TYPE_CONSTANT:
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{
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inst_length = 2;
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uvr0 =
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((fp_instructions[ip + 1] << 8) & uvec4(0xFF00FF00)) |
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((fp_instructions[ip + 1] >> 8) & uvec4(0x00FF00FF));
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vr0 = uintBitsToFloat(uvr0);
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break;
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}
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}
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ur1 = GET_BITS(index + 1, 9, 8);
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vr0 = shuffle(vr0, ur1);
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// abs
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if (index == 0)
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{
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if (TEST_BIT(1, 29)) vr0 = abs(vr0);
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}
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else
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{
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ur1 = index + 1;
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if (TEST_BIT(ur1, 18)) vr0 = abs(vr0);
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}
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// neg
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return (TEST_BIT(index + 1, 17))? -vr0 : vr0;
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}
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vec4 read_cond()
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{
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return shuffle(cc[GET_BITS(1, 31, 1)], GET_BITS(1, 21, 8));
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}
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bvec4 decode_cond(const in uint mode, const in vec4 cond)
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{
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switch (mode)
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{
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case EXEC_GT | EXEC_EQ:
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return greaterThanEqual(cond, vr_zero);
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case EXEC_LT | EXEC_EQ:
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return lessThanEqual(cond, vr_zero);
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case EXEC_LT | EXEC_GT:
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return notEqual(cond, vr_zero);
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case EXEC_GT:
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return greaterThan(cond, vr_zero);
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case EXEC_LT:
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return lessThan(cond, vr_zero);
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case EXEC_EQ:
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return equal(cond, vr_zero);
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default:
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return bvec4(vr_zero);
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}
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}
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#if defined(WITH_FLOW_CTRL) || defined(WITH_KIL)
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bool check_cond()
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{
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ur0 = GET_BITS(1, 18, 3);
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if (ur0 == 0x7)
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{
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return true;
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}
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vr0 = read_cond();
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bvr0 = decode_cond(ur0, vr0);
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return any(bvr0);
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}
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#endif
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#ifdef WITH_TEXTURES
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#define RSX_SAMPLE_TEXTURE_1D 0
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#define RSX_SAMPLE_TEXTURE_2D 1
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#define RSX_SAMPLE_TEXTURE_CUBE 2
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#define RSX_SAMPLE_TEXTURE_3D 3
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// FIXME: Remove when codegen is unified
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#define CLAMP_COORDS_BIT 17
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float _texcoord_xform(const in float coord, const in sampler_info params)
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{
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float result = fma(coord, params.scale_x, params.bias_x);
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if (TEST_BIT(params.flags, CLAMP_COORDS_BIT))
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{
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result = clamp(result, params.clamp_min_x, params.clamp_max_x);
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}
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return result;
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}
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vec2 _texcoord_xform(const in vec2 coord, const in sampler_info params)
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{
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vec2 result = fma(
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coord,
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vec2(params.scale_x, params.scale_y),
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vec2(params.bias_x, params.bias_y)
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);
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if (TEST_BIT(params.flags, CLAMP_COORDS_BIT))
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{
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result = clamp(
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result,
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vec2(params.clamp_min_x, params.clamp_min_y),
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vec2(params.clamp_max_x, params.clamp_max_y)
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);
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}
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return result;
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}
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vec3 _texcoord_xform(const in vec3 coord, const in sampler_info params)
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{
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vec3 result = fma(
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coord,
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vec3(params.scale_x, params.scale_y, params.scale_z),
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vec3(params.bias_x, params.bias_y, params.bias_z)
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);
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// NOTE: Coordinate clamping not supported for CUBE and 3D textures
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return result;
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}
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vec4 _texture(in vec4 coord, float bias)
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{
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ur0 = GET_BITS(0, 17, 4);
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if (!IS_TEXTURE_RESIDENT(ur0))
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{
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return vr_zero;
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}
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ur1 = ur0 + ur0;
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const uint type = bitfieldExtract(texture_control, int(ur1), 2);
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switch (type)
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{
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case RSX_SAMPLE_TEXTURE_1D:
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coord.x = _texcoord_xform(coord.x, texture_parameters[ur0]);
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vr0 = texture(SAMPLER1D(ur0), coord.x, bias);
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break;
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case RSX_SAMPLE_TEXTURE_2D:
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coord.xy = _texcoord_xform(coord.xy, texture_parameters[ur0]);
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vr0 = texture(SAMPLER2D(ur0), coord.xy, bias);
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break;
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case RSX_SAMPLE_TEXTURE_CUBE:
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coord.xyz = _texcoord_xform(coord.xyz, texture_parameters[ur0]);
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vr0 = texture(SAMPLERCUBE(ur0), coord.xyz, bias);
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break;
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case RSX_SAMPLE_TEXTURE_3D:
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coord.xyz = _texcoord_xform(coord.xyz, texture_parameters[ur0]);
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vr0 = texture(SAMPLER3D(ur0), coord.xyz, bias);
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break;
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}
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if (TEST_BIT(0, 21))
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{
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vr0 = vr0 * 2. - 1.;
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}
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return vr0;
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}
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vec4 _textureLod(in vec4 coord, float lod)
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{
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ur0 = GET_BITS(0, 17, 4);
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if (!IS_TEXTURE_RESIDENT(ur0))
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{
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return vr_zero;
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}
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ur1 = ur0 + ur0;
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const uint type = bitfieldExtract(texture_control, int(ur1), 2);
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switch (type)
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{
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case RSX_SAMPLE_TEXTURE_1D:
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coord.x = _texcoord_xform(coord.x, texture_parameters[ur0]);
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vr0 = textureLod(SAMPLER1D(ur0), coord.x, lod);
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break;
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case RSX_SAMPLE_TEXTURE_2D:
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coord.xy = _texcoord_xform(coord.xy, texture_parameters[ur0]);
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vr0 = textureLod(SAMPLER2D(ur0), coord.xy, lod);
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break;
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case RSX_SAMPLE_TEXTURE_CUBE:
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coord.xyz = _texcoord_xform(coord.xyz, texture_parameters[ur0]);
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vr0 = textureLod(SAMPLERCUBE(ur0), coord.xyz, lod);
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break;
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case RSX_SAMPLE_TEXTURE_3D:
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coord.xyz = _texcoord_xform(coord.xyz, texture_parameters[ur0]);
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vr0 = textureLod(SAMPLER3D(ur0), coord.xyz, lod);
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break;
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}
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if (TEST_BIT(0, 21))
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{
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// Normal-expand, v = 2v - 1
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vr0 += vr0;
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vr0 -= 1.;
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}
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return vr0;
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}
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#endif
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void write_dst(const in vec4 value)
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{
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uvr0 = uvec4(uint(1 << 9), uint(1 << 10), uint(1 << 11), uint(1 << 12));
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bvr0 = bvec4(uvr0 & inst.words.xxxx);
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if (TEST_BIT(0, 8)) // SET COND
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{
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ur0 = GET_BITS(1, 30, 1);
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reg_mov(cc[ur0], value, bvr0);
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}
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if (TEST_BIT(0, 30)) // NO DEST
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{
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return;
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}
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ur1 = GET_BITS(2, 28, 3);
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sr0 = modifier_scale[ur1];
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vr0 = value * sr0;
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if (TEST_BIT(0, 31)) // SAT
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{
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vr0 = clamp(vr0, 0, 1);
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}
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ur0 = GET_BITS(1, 18, 3);
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if (ur0 != 0x7)
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{
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vr1 = read_cond();
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bvr1 = decode_cond(ur0, vr1);
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bvr0 = bvec4(uvec4(bvr0) & uvec4(bvr1));
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}
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ur1 = GET_BITS(0, 1, 6);
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if (TEST_BIT(0, 7))
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{
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reg_mov(regs16[ur1], vr0, bvr0);
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}
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else
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{
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reg_mov(regs32[ur1], vr0, bvr0);
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}
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}
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void initialize()
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{
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// Initialize registers
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// NOTE: Register count is the number of 'full' registers that will be consumed. Hardware seems to do some renaming.
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// NOTE: Attempting to zero-initialize all the registers will slow things to a crawl!
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uint register_count = bitfieldExtract(shader_control, 24, 6);
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ur0 = 0, ur1 = 0;
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while (register_count > 0)
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{
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regs32[ur0++] = vr_zero;
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regs16[ur1++] = vr_zero;
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regs16[ur1++] = vr_zero;
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register_count--;
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}
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// Fog coord
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fogc = in_regs[5];
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switch(fog_mode)
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{
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case 0:
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//linear
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fogc.y = fog_param1 * fogc.x + (fog_param0 - 1.);
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break;
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case 1:
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//exponential
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fogc.y = exp(11.084 * (fog_param1 * fogc.x + fog_param0 - 1.5));
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break;
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case 2:
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//exponential2
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fogc.y = exp(-pow(4.709 * (fog_param1 * fogc.x + fog_param0 - 1.5), 2.));
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break;
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case 3:
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//exponential_abs
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fogc.y = exp(11.084 * (fog_param1 * abs(fogc.x) + fog_param0 - 1.5));
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break;
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case 4:
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//exponential2_abs
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fogc.y = exp(-pow(4.709 * (fog_param1 * abs(fogc.x) + fog_param0 - 1.5), 2.));
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break;
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case 5:
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//linear_abs
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fogc.y = fog_param1 * abs(fogc.x) + (fog_param0 - 1.);
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break;
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default:
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fogc = in_regs[5];
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}
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fogc.y = clamp(fogc.y, 0., 1.);
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// WPOS
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vr0 = vec4(abs(wpos_scale), wpos_scale, 1., 1.);
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vr1 = vec4(0., wpos_bias, 0., 0.);
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wpos = gl_FragCoord * vr0 + vr1;
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})"
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R"(
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void main()
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{
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initialize();
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inst.end = false;
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bool handled;
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#ifdef WITH_STIPPLING
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uvr0.xy = uvec2(gl_FragCoord.xy) % uvec2(32u); // x,y location
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ur0 = uvr0.y * 32u + uvr0.x; // linear address
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ur1 = ur0 & 31u; // address % 32 -> fetch bit offset
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ur1 = (1u << ur1); // address mask
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uvr0.x = (ur0 >> 7u); // address to uvec4 row (each row has 32x4 bits)
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ur0 = (ur0 >> 5u) & 3u; // address to uvec4 word (address / 32) % 4
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if ((stipple_pattern[uvr0.x][ur0] & ur1) == 0u)
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{
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discard;
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inst.end = true;
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}
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#endif
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while (!inst.end)
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{
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ip += inst_length;
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inst_length = 1;
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#ifdef WITH_FLOW_CTRL
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if (ip == test_addr)
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{
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ip = jump_addr;
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test_addr = -1;
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jump_addr = -1;
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}
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else if (ip == loop_end_addr)
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{
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if (counter > 0)
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{
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counter--;
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ip = loop_start_addr;
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}
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else
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{
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loop_end_addr = -1;
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loop_start_addr = -1;
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}
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}
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#endif
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// Decode instruction
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// endian swap + word swap
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inst.words =
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((fp_instructions[ip] << 8) & uvec4(0xFF00FF00)) |
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((fp_instructions[ip] >> 8) & uvec4(0x00FF00FF));
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inst.opcode = GET_BITS(0, 24, 6);
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inst.end = TEST_BIT(0, 0);
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#ifdef WITH_FLOW_CTRL
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if (TEST_BIT(2, 31))
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{
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// Flow control
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switch (inst.opcode | (1 << 6))
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{
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//case RSX_FP_OPCODE_CAL:
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// Function call not yet found in the wild for this hw class
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case RSX_FP_OPCODE_RET:
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inst.end = true;
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continue;
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case RSX_FP_OPCODE_IFE:
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if (check_cond())
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{
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// Go down IF path
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if (inst.words.z < inst.words.w)
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{
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test_addr = int(inst.words.z >> 2);
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jump_addr = int(inst.words.w >> 2);
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}
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// If simple IF..ENDIF, do nothing
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}
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else
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{
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// Go to ELSE path
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ip = int(inst.words.z >> 2);
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inst_length = 0;
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}
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continue;
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case RSX_FP_OPCODE_LOOP:
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case RSX_FP_OPCODE_REP:
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if (check_cond())
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{
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counter = int(GET_BITS(2, 2, 8) - GET_BITS(2, 10, 8));
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counter /= int(GET_BITS(2, 19, 8));
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loop_start_addr = ip + 1;
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loop_end_addr = int(inst.words.w >> 2);
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}
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else
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{
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ip = int(inst.words.w >> 2);
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inst_length = 0;
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}
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continue;
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case RSX_FP_OPCODE_BRK:
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if (loop_end_addr > 0)
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{
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ip = loop_end_addr;
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inst_length = 0;
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counter = 0;
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}
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continue;
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}
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continue;
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}
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#endif
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// Class 1, no input/output
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switch (inst.opcode)
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{
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case RSX_FP_OPCODE_NOP:
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case RSX_FP_OPCODE_FENCT:
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case RSX_FP_OPCODE_FENCB:
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continue;
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#ifdef WITH_KIL
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case RSX_FP_OPCODE_KIL:
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if (check_cond())
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{
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discard;
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return;
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}
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continue;
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#endif
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}
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// Class 2, 1 input
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s0 = read_src(0);
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handled = true;
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switch (inst.opcode)
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{
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case RSX_FP_OPCODE_MOV:
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vrr = s0; break;
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case RSX_FP_OPCODE_FRC:
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vrr = fract(s0); break;
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case RSX_FP_OPCODE_FLR:
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vrr = floor(s0); break;
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case RSX_FP_OPCODE_DDX:
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vrr = dFdx(s0); break;
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case RSX_FP_OPCODE_DDY:
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vrr = dFdy(s0); break;
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case RSX_FP_OPCODE_RCP:
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vrr = (1.f / s0.xxxx); break;
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case RSX_FP_OPCODE_RSQ:
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vrr = inversesqrt(s0.xxxx); break;
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case RSX_FP_OPCODE_EX2:
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vrr = exp2(s0.xxxx); break;
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case RSX_FP_OPCODE_LG2:
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vrr = log2(s0.xxxx); break;
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case RSX_FP_OPCODE_STR:
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vrr = vr_one; break;
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case RSX_FP_OPCODE_SFL:
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vrr = vr_zero; break;
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case RSX_FP_OPCODE_COS:
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vrr = cos(s0.xxxx); break;
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case RSX_FP_OPCODE_SIN:
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vrr = sin(s0.xxxx); break;
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case RSX_FP_OPCODE_NRM:
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vrr.xyz = normalize(s0.xyz); break;
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#ifdef WITH_TEXTURES
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case RSX_FP_OPCODE_TEX:
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vrr = _texture(s0, 0.f); break;
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case RSX_FP_OPCODE_TXP:
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vrr = _texture(vec4(s0.xyz / s0.w, s0.w), 0.f); break;
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#endif
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#ifdef WITH_PACKING
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case RSX_FP_OPCODE_PK2:
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vrr = vec4(uintBitsToFloat(packHalf2x16(s0.xy))); break;
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case RSX_FP_OPCODE_PK4:
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vrr = vec4(uintBitsToFloat(packSnorm4x8(s0))); break;
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case RSX_FP_OPCODE_PK16:
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vrr = vec4(uintBitsToFloat(packSnorm2x16(s0.xy))); break;
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case RSX_FP_OPCODE_PKG:
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// Should be similar to PKB but with gamma correction, see description of PK4UBG in khronos page
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case RSX_FP_OPCODE_PKB:
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vrr = vec4(uintBitsToFloat(packUnorm4x8(s0))); break;
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case RSX_FP_OPCODE_UP2:
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vrr = unpackHalf2x16(floatBitsToUint(s0.x)).xyxy; break;
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case RSX_FP_OPCODE_UP4:
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vrr = unpackSnorm4x8(floatBitsToUint(s0.x)); break;
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case RSX_FP_OPCODE_UP16:
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vrr = unpackSnorm2x16(floatBitsToUint(s0.x)).xyxy; break;
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case RSX_FP_OPCODE_UPG:
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// Same as UPB with gamma correction
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case RSX_FP_OPCODE_UPB:
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vrr = unpackUnorm4x8(floatBitsToUint(s0.x)); break;
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#endif
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default:
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handled = false;
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}
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if (!handled)
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{
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|
// Class 3, 2 inputs
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s1 = read_src(1);
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handled = true;
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switch (inst.opcode)
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|
{
|
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case RSX_FP_OPCODE_MUL:
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vrr = s0 * s1; break;
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case RSX_FP_OPCODE_ADD:
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vrr = s0 + s1; break;
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case RSX_FP_OPCODE_DP2:
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vrr = dot(s0.xy, s1.xy).xxxx; break;
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case RSX_FP_OPCODE_DP3:
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vrr = dot(s0.xyz, s1.xyz).xxxx; break;
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|
case RSX_FP_OPCODE_DP4:
|
|
vrr = dot(s0, s1).xxxx; break;
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|
case RSX_FP_OPCODE_DST:
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|
vrr = _distance(s0, s1); break;
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|
case RSX_FP_OPCODE_MIN:
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|
vrr = min(s0, s1); break;
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|
case RSX_FP_OPCODE_MAX:
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|
vrr = max(s0, s1); break;
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|
case RSX_FP_OPCODE_SLT:
|
|
vrr = vec4(lessThan(s0, s1)); break;
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|
case RSX_FP_OPCODE_SGE:
|
|
vrr = vec4(greaterThanEqual(s0, s1)); break;
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|
case RSX_FP_OPCODE_SLE:
|
|
vrr = vec4(lessThanEqual(s0, s1)); break;
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|
case RSX_FP_OPCODE_SGT:
|
|
vrr = vec4(greaterThan(s0, s1)); break;
|
|
case RSX_FP_OPCODE_SNE:
|
|
vrr = vec4(notEqual(s0, s1)); break;
|
|
case RSX_FP_OPCODE_SEQ:
|
|
vrr = vec4(equal(s0, s1)); break;
|
|
case RSX_FP_OPCODE_POW:
|
|
vrr = pow(s0, s1).xxxx; break;
|
|
case RSX_FP_OPCODE_DIV:
|
|
vrr = s0 / s1.xxxx; break;
|
|
case RSX_FP_OPCODE_DIVSQ:
|
|
bvr0 = bvec4(s0);
|
|
sr0 = inversesqrt(s1.x);
|
|
vr0 = s0 * sr0;
|
|
vrr = select(s0, vr0, bvr0);
|
|
break;
|
|
case RSX_FP_OPCODE_REFL:
|
|
vrr = reflect(s0, s1); break;
|
|
|
|
#ifdef WITH_TEXTURES
|
|
//case RSX_FP_OPCODE_TXD:
|
|
case RSX_FP_OPCODE_TXL:
|
|
vrr = _textureLod(s0, s1.x); break;
|
|
case RSX_FP_OPCODE_TXB:
|
|
vrr = _texture(s0, s1.x); break;
|
|
//case RSX_FP_OPCODE_TEXBEM:
|
|
//case RSX_FP_OPCODE_TXPBEM:
|
|
#endif
|
|
default:
|
|
handled = false;
|
|
}
|
|
}
|
|
|
|
if (!handled)
|
|
{
|
|
// Class 4, 3 inputs
|
|
s2 = read_src(2);
|
|
switch (inst.opcode)
|
|
{
|
|
case RSX_FP_OPCODE_MAD:
|
|
vrr = fma(s0, s1, s2); break;
|
|
case RSX_FP_OPCODE_LRP:
|
|
vrr = mix(s1, s2, s0); break;
|
|
case RSX_FP_OPCODE_DP2A:
|
|
vrr = dot(s0.xy, s1.xy).xxxx + s2.xxxx; break;
|
|
}
|
|
}
|
|
#if 0
|
|
// Other
|
|
case RSX_FP_OPCODE_BEM:
|
|
case RSX_FP_OPCODE_BEMLUM:
|
|
case RSX_FP_OPCODE_LIT:
|
|
case RSX_FP_OPCODE_LIF:
|
|
case RSX_FP_OPCODE_TIMESWTEX:
|
|
#endif
|
|
write_dst(vrr);
|
|
}
|
|
|
|
#ifdef WITH_HALF_OUTPUT_REGISTER
|
|
ocol0 = regs16[0];
|
|
ocol1 = regs16[4];
|
|
ocol2 = regs16[6];
|
|
ocol3 = regs16[8];
|
|
#else
|
|
ocol0 = regs32[0];
|
|
ocol1 = regs32[2];
|
|
ocol2 = regs32[3];
|
|
ocol3 = regs32[4];
|
|
#endif
|
|
|
|
#ifdef WITH_DEPTH_EXPORT
|
|
gl_FragDepth = regs32[1].z;
|
|
#endif
|
|
|
|
// Typically an application will pick one strategy and stick with it
|
|
#ifdef ALPHA_TEST_GEQUAL
|
|
if (ocol0.a < alpha_ref) discard; // gequal
|
|
#endif
|
|
#ifdef ALPHA_TEST_GREATER
|
|
if (ocol0.a <= alpha_ref) discard; // greater
|
|
#endif
|
|
#ifdef ALPHA_TEST_LESS
|
|
if (ocol0.a >= alpha_ref) discard; // less
|
|
#endif
|
|
#ifdef ALPHA_TEST_LEQUAL
|
|
if (ocol0.a > alpha_ref) discard; // lequal
|
|
#endif
|
|
#ifdef ALPHA_TEST_EQUAL
|
|
if (ocol0.a != alpha_ref) discard; // equal
|
|
#endif
|
|
#ifdef ALPHA_TEST_NEQUAL
|
|
if (ocol0.a == alpha_ref) discard; // nequal
|
|
#endif
|
|
}
|
|
|
|
)"
|