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rpcsx/rpcs3/Emu/RSX/Common/Interpreter
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kd-11 14969cd8d0 rsx: Disable SCA writes to output register if vec result flag is set. 
- Noticed when debugging X-men origins: wolverine which has a bogus SCA op whilst writing vector to output
- It makes no sense for both SCA and VEC to both write to the same register in the same instruction as memory ordering becomes an issue
2020-05-08 14:35:07 +03:00
..
FragmentInterpreter.glsl rsx/interpreter: Fix DIVSQ instruction 2020-05-05 13:18:03 +03:00
VertexInterpreter.glsl rsx: Disable SCA writes to output register if vec result flag is set. 2020-05-08 14:35:07 +03:00