mirror of
https://github.com/RPCSX/rpcsx.git
synced 2026-04-20 22:05:12 +00:00
861 lines
No EOL
32 KiB
C++
861 lines
No EOL
32 KiB
C++
#pragma once
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#define OP_REG u32
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#define OP_sIMM s32
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#define OP_uIMM u32
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#define START_OPCODES_GROUP(x) /*x*/
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#define ADD_OPCODE(name, regs) virtual void(##name##)##regs##=0
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#define ADD_NULL_OPCODE(name) virtual void(##name##)()=0
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#define END_OPCODES_GROUP(x) /*x*/
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namespace PPU_opcodes
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{
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enum PPU_MainOpcodes
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{
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TDI = 0x02, //Trap Doubleword Immediate
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TWI = 0x03, //Trap Word Immediate
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G_04 = 0x04,
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MULLI = 0x07, //Multiply Low Immediate
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SUBFIC = 0x08, //Subtract from Immediate Carrying
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//DOZI = 0x09,
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CMPLI = 0x0a, //Compare Logical Immediate
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CMPI = 0x0b, //Compare Immediate
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ADDIC = 0x0c, //Add Immediate Carrying
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ADDIC_ = 0x0d, //Add Immediate Carrying and Record
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ADDI = 0x0e, //Add Immediate
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ADDIS = 0x0f, //Add Immediate Shifted
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BC = 0x10, //Branch Conditional
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SC = 0x11, //System Call
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B = 0x12, //Branch
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G_13 = 0x13,
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RLWIMI = 0x14, //Rotate Left Word Immediate then Mask Insert
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RLWINM = 0x15, //Rotate Left Word Immediate then AND with Mask
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RLWNM = 0x17, //Rotate Left Word then AND with Mask
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ORI = 0x18, //OR Immediate
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ORIS = 0x19, //OR Immediate Shifted
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XORI = 0x1a, //XOR Immediate
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XORIS = 0x1b, //XOR Immediate Shifted
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ANDI_ = 0x1c, //AND Immediate
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ANDIS_ = 0x1d, //AND Immediate Shifted
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G_1e = 0x1e,
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G_1f = 0x1f,
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LWZ = 0x20, //Load Word and Zero Indexed
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LWZU = 0x21, //Load Word and Zero with Update Indexed
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LBZ = 0x22, //Load Byte and Zero
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LBZU = 0x23, //Load Byte and Zero with Update
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STW = 0x24, //Store Word
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STWU = 0x25, //Store Word with Update
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STB = 0x26, //Store Byte
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STBU = 0x27, //Store Byte with Update
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LHZ = 0x28, //Load Halfword and Zero
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LHZU = 0x29, //Load Halfword and Zero with Update
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LHA = 0x2a, //Load Halfword Algebraic with Update
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LHAU = 0x2b, //Load Halfword Algebraic
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STH = 0x2c, //Store Halfword
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STHU = 0x2d, //Store Halfword with Update
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LMW = 0x2e, //Load Multiple Word
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STMW = 0x2f, //Store Multiple Word
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LFS = 0x30, //Load Floating-Point Single
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LFSU = 0x31, //Load Floating-Point Single with Update
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LFD = 0x32, //Load Floating-Point Double
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LFDU = 0x33, //Load Floating-Point Double with Update
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STFS = 0x34, //Store Floating-Point Single
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STFSU = 0x35, //Store Floating-Point Single with Update
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STFD = 0x36, //Store Floating-Point Double
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STFDU = 0x37, //Store Floating-Point Double with Update
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LFQ = 0x38, //
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LFQU = 0x39, //
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G_3a = 0x3a,
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G_3b = 0x3b,
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G_3e = 0x3e,
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G_3f = 0x3f,
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};
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enum G_04Opcodes
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{
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VADDUBM = 0x0,
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VMAXUB = 0x2,
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VRLB = 0x4,
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VCMPEQUB = 0x6,
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VMULOUB = 0x8,
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VADDFP = 0xa,
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VMRGHB = 0xc,
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VPKUHUM = 0xe,
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VADDUHM = 0x40,
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VMAXUH = 0x42,
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VRLH = 0x44,
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VCMPEQUH = 0x46,
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VMULOUH = 0x48,
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VSUBFP = 0x4a,
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VMRGHH = 0x4c,
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VPKUWUM = 0x4e,
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VADDUWM = 0x80,
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VMAXUW = 0x82,
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VRLW = 0x84,
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VCMPEQUW = 0x86,
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VMRGHW = 0x8c,
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VPKUHUS = 0x8e,
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VCMPEQFP = 0xc6,
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VPKUWUS = 0xce,
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VMAXSB = 0x102,
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VSLB = 0x104,
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VMULOSB = 0x108,
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VREFP = 0x10a,
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VMRGLB = 0x10c,
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VPKSHUS = 0x10e,
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VMAXSH = 0x142,
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VSLH = 0x144,
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VMULOSH = 0x148,
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VRSQRTEFP = 0x14a,
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VMRGLH = 0x14c,
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VPKSWUS = 0x14e,
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VADDCUW = 0x180,
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VMAXSW = 0x182,
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VSLW = 0x184,
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VEXPTEFP = 0x18a,
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VMRGLW = 0x18c,
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VPKSHSS = 0x18e,
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VSL = 0x1c4,
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VCMPGEFP = 0x1c6,
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VLOGEFP = 0x1ca,
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VPKSWSS = 0x1ce,
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VADDUBS = 0x200,
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VMINUB = 0x202,
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VSRB = 0x204,
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VCMPGTUB = 0x206,
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VMULEUB = 0x208,
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VRFIN = 0x20a,
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VSPLTB = 0x20c,
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VUPKHSB = 0x20e,
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VADDUHS = 0x240,
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VMINUH = 0x242,
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VSRH = 0x244,
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VCMPGTUH = 0x246,
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VMULEUH = 0x248,
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VRFIZ = 0x24a,
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VSPLTH = 0x24c,
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VUPKHSH = 0x24e,
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VADDUWS = 0x280,
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VMINUW = 0x282,
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VSRW = 0x284,
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VCMPGTUW = 0x286,
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VRFIP = 0x28a,
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VSPLTW = 0x28c,
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VUPKLSB = 0x28e,
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VSR = 0x2c4,
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VCMPGTFP = 0x2c6,
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VRFIM = 0x2ca,
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VUPKLSH = 0x2ce,
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VADDSBS = 0x300,
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VMINSB = 0x302,
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VSRAB = 0x304,
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VCMPGTSB = 0x306,
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VMULESB = 0x308,
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VCFUX = 0x30a,
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VSPLTISB = 0x30c,
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VPKPX = 0x30e,
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VADDSHS = 0x340,
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VMINSH = 0x342,
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VSRAH = 0x344,
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VCMPGTSH = 0x346,
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VMULESH = 0x348,
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VCFSX = 0x34a,
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VSPLTISH = 0x34c,
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VUPKHPX = 0x34e,
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VADDSWS = 0x380,
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VMINSW = 0x382,
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VSRAW = 0x384,
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VCMPGTSW = 0x386,
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VCTUXS = 0x38a,
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VSPLTISW = 0x38c,
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VCMPBFP = 0x3c6,
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VCTSXS = 0x3ca,
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VUPKLPX = 0x3ce,
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VSUBUBM = 0x400,
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VAVGUB = 0x402,
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VAND = 0x404,
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VCMPEQUB_ = 0x406,
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VMAXFP = 0x40a,
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VSLO = 0x40c,
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VSUBUHM = 0x440,
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VAVGUH = 0x442,
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VANDC = 0x444,
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VCMPEQUH_ = 0x446,
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VMINFP = 0x44a,
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VSRO = 0x44c,
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VSUBUWM = 0x480,
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VAVGUW = 0x482,
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VOR = 0x484,
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VCMPEQUW_ = 0x486,
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VXOR = 0x4c4,
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VCMPEQFP_ = 0x4c6,
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VAVGSB = 0x502,
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VNOR = 0x504,
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VAVGSH = 0x542,
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VSUBCUW = 0x580,
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VAVGSW = 0x582,
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VCMPGEFP_ = 0x5c6,
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VSUBUBS = 0x600,
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MFVSCR = 0x604,
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VCMPGTUB_ = 0x606,
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VSUM4UBS = 0x608,
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VSUBUHS = 0x640,
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MTVSCR = 0x644,
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VCMPGTUH_ = 0x646,
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VSUM4SHS = 0x648,
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VSUBUWS = 0x680,
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VCMPGTUW_ = 0x686,
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VSUM2SWS = 0x688,
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VCMPGTFP_ = 0x6c6,
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VSUBSBS = 0x700,
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VCMPGTSB_ = 0x706,
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VSUM4SBS = 0x708,
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VSUBSHS = 0x740,
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VCMPGTSH_ = 0x746,
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VSUBSWS = 0x780,
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VCMPGTSW_ = 0x786,
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VSUMSWS = 0x788,
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VCMPBFP_ = 0x7c6,
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};
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enum G_04_VA_Opcodes
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{
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VMHADDSHS = 0x20,
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VMHRADDSHS = 0x21,
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VMLADDUHM = 0x22,
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VMSUMUBM = 0x24,
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VMSUMMBM = 0x25,
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VMSUMUHM = 0x26,
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VMSUMUHS = 0x27,
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VMSUMSHM = 0x28,
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VMSUMSHS = 0x29,
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VSEL = 0x2a,
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VPERM = 0x2b,
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VSLDOI = 0x2c,
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VMADDFP = 0x2e,
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VNMSUBFP = 0x2f,
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};
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enum G_13Opcodes //Field 21 - 30
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{
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MCRF = 0x000,
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BCLR = 0x010,
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CRNOR = 0x021,
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CRANDC = 0x081,
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ISYNC = 0x096,
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CRXOR = 0x0c1,
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CRNAND = 0x0e1,
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CRAND = 0x101,
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CREQV = 0x121,
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CRORC = 0x1a1,
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CROR = 0x1c1,
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BCCTR = 0x210,
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};
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enum G_1eOpcodes //Field 27 - 29
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{
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RLDICL = 0x0,
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RLDICR = 0x1,
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RLDIC = 0x2,
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RLDIMI = 0x3,
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};
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enum G_1fOpcodes //Field 21 - 30
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{
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CMP = 0x000,
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TW = 0x004,
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LVSL = 0x006, //Load Vector for Shift Left
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LVEBX = 0x007, //Load Vector Element Byte Indexed
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SUBFC = 0x008, //Subtract from Carrying
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MULHDU = 0x009,
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ADDC = 0x00a,
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MULHWU = 0x00b,
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MFOCRF = 0x013,
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LWARX = 0x014,
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LDX = 0x015,
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LWZX = 0x017,
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SLW = 0x018,
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CNTLZW = 0x01a,
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SLD = 0x01b,
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AND = 0x01c,
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CMPL = 0x020,
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LVSR = 0x026, //Load Vector for Shift Right
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LVEHX = 0x027, //Load Vector Element Halfword Indexed
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SUBF = 0x028,
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LDUX = 0x035, //Load Doubleword with Update Indexed
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DCBST = 0x036,
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CNTLZD = 0x03a,
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ANDC = 0x03c,
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LVEWX = 0x047, //Load Vector Element Word Indexed
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MULHD = 0x049,
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MULHW = 0x04b,
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LDARX = 0x054,
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DCBF = 0x056,
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LBZX = 0x057,
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LVX = 0x067, //Load Vector Indexed
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NEG = 0x068,
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LBZUX = 0x077,
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NOR = 0x07c,
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STVEBX = 0x087, //Store Vector Element Byte Indexed
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SUBFE = 0x088, //Subtract from Extended
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ADDE = 0x08a,
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MTOCRF = 0x090,
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STDX = 0x095,
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STWCX_ = 0x096,
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STWX = 0x097,
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STVEHX = 0x0a7, //Store Vector Element Halfword Indexed
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STDUX = 0x0b5,
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STVEWX = 0x0c7, //Store Vector Element Word Indexed
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ADDZE = 0x0ca,
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STDCX_ = 0x0d6,
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STBX = 0x0d7,
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STVX = 0x0e7,
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MULLD = 0x0e9,
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ADDME = 0x0ea,
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MULLW = 0x0eb,
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DCBTST = 0x0f6,
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DOZ = 0x108,
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ADD = 0x10a,
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DCBT = 0x116,
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LHZX = 0x117,
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EQV = 0x11c,
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ECIWX = 0x136,
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LHZUX = 0x137,
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XOR = 0x13c,
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MFSPR = 0x153,
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DST = 0x156, //Data Stream Touch
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LHAX = 0x157,
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LVXL = 0x167, //Load Vector Indexed Last
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ABS = 0x168,
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MFTB = 0x173,
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DSTST = 0x176, //Data Stream Touch for Store
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LHAUX = 0x177,
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STHX = 0x197, //Store Halfword Indexed
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ORC = 0x19c, //OR with Complement
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ECOWX = 0x1b6,
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OR = 0x1bc,
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DIVDU = 0x1c9,
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DIVWU = 0x1cb,
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MTSPR = 0x1d3,
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DCBI = 0x1d6,
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NAND = 0x1dc,
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STVXL = 0x1e7, //Store Vector Indexed Last
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DIVD = 0x1e9,
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DIVW = 0x1eb,
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LVLX = 0x207, //Load Vector Left Indexed
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LWBRX = 0x216,
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LFSX = 0x217,
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SRW = 0x218,
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SRD = 0x21b,
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LVRX = 0x227, //Load Vector Right Indexed
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LFSUX = 0x237,
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SYNC = 0x256,
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LFDX = 0x257,
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LFDUX = 0x277,
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STVLX = 0x287, //Store Vector Left Indexed
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STFSX = 0x297,
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STVRX = 0x2a7, //Store Vector Right Indexed
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STFDX = 0x2d7, //Store Floating-Point Double Indexed
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LVLXL = 0x307, //Load Vector Left Indexed Last
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LHBRX = 0x316,
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SRAW = 0x318,
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SRAD = 0x31a,
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LVRXL = 0x327, //Load Vector Right Indexed Last
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DSS = 0x336, //Data Stream Stop
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SRAWI = 0x338,
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SRADI1 = 0x33a, //sh_5 == 0
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SRADI2 = 0x33b, //sh_5 != 0
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EIEIO = 0x356,
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STVLXL = 0x387, //Store Vector Left Indexed Last
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EXTSH = 0x39a,
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STVRXL = 0x3a7, //Store Vector Right Indexed Last
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EXTSB = 0x3ba,
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STFIWX = 0x3d7,
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EXTSW = 0x3da,
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ICBI = 0x3d6,
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DCBZ = 0x3f6,
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};
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enum G_3aOpcodes //Field 30 - 31
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{
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LD = 0x0,
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LDU = 0x1,
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};
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enum G_3bOpcodes //Field 26 - 30
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{
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FDIVS = 0x12,
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FSUBS = 0x14,
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FADDS = 0x15,
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FSQRTS = 0x16,
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FRES = 0x18,
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FMULS = 0x19,
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FMSUBS = 0x1c,
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FMADDS = 0x1d,
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FNMSUBS = 0x1e,
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FNMADDS = 0x1f,
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};
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enum G_3eOpcodes //Field 30 - 31
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{
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STD = 0x0,
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STDU = 0x1,
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};
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enum G_3fOpcodes //Field 21 - 30
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{
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MTFSB1 = 0x026,
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MCRFS = 0x040,
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MTFSB0 = 0x046,
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MTFSFI = 0x086,
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MFFS = 0x247,
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MTFSF = 0x2c7,
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FCMPU = 0x000,
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FRSP = 0x00c,
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FCTIW = 0x00e,
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FCTIWZ = 0x00f,
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FDIV = 0x012,
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FSUB = 0x014,
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FADD = 0x015,
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FSQRT = 0x016,
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FSEL = 0x017,
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FMUL = 0x019,
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FRSQRTE = 0x01a,
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FMSUB = 0x01c,
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FMADD = 0x01d,
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FNMSUB = 0x01e,
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FNMADD = 0x01f,
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FCMPO = 0x020,
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FNEG = 0x028,
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FMR = 0x048,
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FNABS = 0x088,
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FABS = 0x108,
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FCTID = 0x32e,
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FCTIDZ = 0x32f,
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FCFID = 0x34e,
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};
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}
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class PPU_Opcodes
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{
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public:
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virtual void Exit()=0;
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static u64 branchTarget(const u64 pc, const u64 imm)
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{
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return pc + (imm & ~0x3);
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}
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ADD_NULL_OPCODE(NULL_OP);
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ADD_NULL_OPCODE(NOP);
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ADD_OPCODE(TDI,(OP_uIMM to, OP_REG ra, OP_sIMM simm16));
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ADD_OPCODE(TWI,(OP_uIMM to, OP_REG ra, OP_sIMM simm16));
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START_OPCODES_GROUP(G_04)
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ADD_OPCODE(MFVSCR,(OP_REG vd));
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ADD_OPCODE(MTVSCR,(OP_REG vb));
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ADD_OPCODE(VADDCUW,(OP_REG vd, OP_REG va, OP_REG vb));
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ADD_OPCODE(VADDFP,(OP_REG vd, OP_REG va, OP_REG vb));
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ADD_OPCODE(VADDSBS,(OP_REG vd, OP_REG va, OP_REG vb));
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ADD_OPCODE(VADDSHS,(OP_REG vd, OP_REG va, OP_REG vb));
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ADD_OPCODE(VADDSWS,(OP_REG vd, OP_REG va, OP_REG vb));
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ADD_OPCODE(VADDUBM,(OP_REG vd, OP_REG va, OP_REG vb));
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ADD_OPCODE(VADDUBS,(OP_REG vd, OP_REG va, OP_REG vb));
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ADD_OPCODE(VADDUHM,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VADDUHS,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VADDUWM,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VADDUWS,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VAND,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VANDC,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VAVGSB,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VAVGSH,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VAVGSW,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VAVGUB,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VAVGUH,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VAVGUW,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCFSX,(OP_REG vd, OP_uIMM uimm5, OP_REG vb));
|
|
ADD_OPCODE(VCFUX,(OP_REG vd, OP_uIMM uimm5, OP_REG vb));
|
|
ADD_OPCODE(VCMPBFP,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPBFP_,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPEQFP,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPEQFP_,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPEQUB,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPEQUB_,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPEQUH,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPEQUH_,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPEQUW,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPEQUW_,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPGEFP,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPGEFP_,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPGTFP,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPGTFP_,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPGTSB,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPGTSB_,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPGTSH,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPGTSH_,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPGTSW,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPGTSW_,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPGTUB,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPGTUB_,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPGTUH,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPGTUH_,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPGTUW,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCMPGTUW_,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VCTSXS,(OP_REG vd, OP_uIMM uimm5, OP_REG vb));
|
|
ADD_OPCODE(VCTUXS,(OP_REG vd, OP_uIMM uimm5, OP_REG vb));
|
|
ADD_OPCODE(VEXPTEFP,(OP_REG vd, OP_REG vb));
|
|
ADD_OPCODE(VLOGEFP,(OP_REG vd, OP_REG vb));
|
|
ADD_OPCODE(VMADDFP,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
|
ADD_OPCODE(VMAXFP,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMAXSB,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMAXSH,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMAXSW,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMAXUB,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMAXUH,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMAXUW,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMHADDSHS,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
|
ADD_OPCODE(VMHRADDSHS,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
|
ADD_OPCODE(VMINFP,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMINSB,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMINSH,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMINSW,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMINUB,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMINUH,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMINUW,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMLADDUHM,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
|
ADD_OPCODE(VMRGHB,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMRGHH,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMRGHW,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMRGLB,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMRGLH,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMRGLW,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMSUMMBM,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
|
ADD_OPCODE(VMSUMSHM,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
|
ADD_OPCODE(VMSUMSHS,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
|
ADD_OPCODE(VMSUMUBM,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
|
ADD_OPCODE(VMSUMUHM,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
|
ADD_OPCODE(VMSUMUHS,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
|
ADD_OPCODE(VMULESB,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMULESH,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMULEUB,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMULEUH,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMULOSB,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMULOSH,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMULOUB,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VMULOUH,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VNMSUBFP,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
|
ADD_OPCODE(VNOR,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VOR,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VPERM,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
|
ADD_OPCODE(VPKPX,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VPKSHSS,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VPKSHUS,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VPKSWSS,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VPKSWUS,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VPKUHUM,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VPKUHUS,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VPKUWUM,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VPKUWUS,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VREFP,(OP_REG vd, OP_REG vb));
|
|
ADD_OPCODE(VRFIM,(OP_REG vd, OP_REG vb));
|
|
ADD_OPCODE(VRFIN,(OP_REG vd, OP_REG vb));
|
|
ADD_OPCODE(VRFIP,(OP_REG vd, OP_REG vb));
|
|
ADD_OPCODE(VRFIZ,(OP_REG vd, OP_REG vb));
|
|
ADD_OPCODE(VRLB,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VRLH,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VRLW,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VRSQRTEFP,(OP_REG vd, OP_REG vb));
|
|
ADD_OPCODE(VSEL,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
|
ADD_OPCODE(VSL,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSLB,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSLDOI,(OP_REG vd, OP_REG va, OP_REG vb, OP_uIMM sh));
|
|
ADD_OPCODE(VSLH,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSLO,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSLW,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSPLTB,(OP_REG vd, OP_uIMM uimm5, OP_REG vb));
|
|
ADD_OPCODE(VSPLTH,(OP_REG vd, OP_uIMM uimm5, OP_REG vb));
|
|
ADD_OPCODE(VSPLTISB,(OP_REG vd, OP_sIMM simm5));
|
|
ADD_OPCODE(VSPLTISH,(OP_REG vd, OP_sIMM simm5));
|
|
ADD_OPCODE(VSPLTISW,(OP_REG vd, OP_sIMM simm5));
|
|
ADD_OPCODE(VSPLTW,(OP_REG vd, OP_uIMM uimm5, OP_REG vb));
|
|
ADD_OPCODE(VSR,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSRAB,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSRAH,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSRAW,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSRB,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSRH,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSRO,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSRW,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSUBCUW,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSUBFP,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSUBSBS,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSUBSHS,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSUBSWS,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSUBUBM,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSUBUBS,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSUBUHM,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSUBUHS,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSUBUWM,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSUBUWS,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSUMSWS,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSUM2SWS,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSUM4SBS,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSUM4SHS,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VSUM4UBS,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
ADD_OPCODE(VUPKHPX,(OP_REG vd, OP_REG vb));
|
|
ADD_OPCODE(VUPKHSB,(OP_REG vd, OP_REG vb));
|
|
ADD_OPCODE(VUPKHSH,(OP_REG vd, OP_REG vb));
|
|
ADD_OPCODE(VUPKLPX,(OP_REG vd, OP_REG vb));
|
|
ADD_OPCODE(VUPKLSB,(OP_REG vd, OP_REG vb));
|
|
ADD_OPCODE(VUPKLSH,(OP_REG vd, OP_REG vb));
|
|
ADD_OPCODE(VXOR,(OP_REG vd, OP_REG va, OP_REG vb));
|
|
END_OPCODES_GROUP(G_04);
|
|
|
|
ADD_OPCODE(MULLI,(OP_REG rd, OP_REG ra, OP_sIMM simm16));
|
|
ADD_OPCODE(SUBFIC,(OP_REG rd, OP_REG ra, OP_sIMM simm16));
|
|
ADD_OPCODE(CMPLI,(OP_REG bf, OP_REG l, OP_REG ra, OP_uIMM uimm16));
|
|
ADD_OPCODE(CMPI,(OP_REG bf, OP_REG l, OP_REG ra, OP_sIMM simm16));
|
|
ADD_OPCODE(ADDIC,(OP_REG rd, OP_REG ra, OP_sIMM simm16));
|
|
ADD_OPCODE(ADDIC_,(OP_REG rd, OP_REG ra, OP_sIMM simm16));
|
|
ADD_OPCODE(ADDI,(OP_REG rd, OP_REG ra, OP_sIMM simm16));
|
|
ADD_OPCODE(ADDIS,(OP_REG rd, OP_REG ra, OP_sIMM simm16));
|
|
ADD_OPCODE(BC,(OP_REG bo, OP_REG bi, OP_sIMM bd, OP_REG aa, OP_REG lk));
|
|
ADD_OPCODE(SC,(OP_sIMM sc_code));
|
|
ADD_OPCODE(B,(OP_sIMM ll, OP_REG aa, OP_REG lk));
|
|
|
|
START_OPCODES_GROUP(G_13)
|
|
ADD_OPCODE(MCRF,(OP_REG crfd, OP_REG crfs));
|
|
ADD_OPCODE(BCLR,(OP_REG bo, OP_REG bi, OP_REG bh, OP_REG lk));
|
|
ADD_OPCODE(CRNOR,(OP_REG bt, OP_REG ba, OP_REG bb));
|
|
ADD_OPCODE(CRANDC,(OP_REG bt, OP_REG ba, OP_REG bb));
|
|
ADD_OPCODE(ISYNC,());
|
|
ADD_OPCODE(CRXOR,(OP_REG bt, OP_REG ba, OP_REG bb));
|
|
ADD_OPCODE(CRNAND,(OP_REG bt, OP_REG ba, OP_REG bb));
|
|
ADD_OPCODE(CRAND,(OP_REG bt, OP_REG ba, OP_REG bb));
|
|
ADD_OPCODE(CREQV,(OP_REG bt, OP_REG ba, OP_REG bb));
|
|
ADD_OPCODE(CRORC,(OP_REG bt, OP_REG ba, OP_REG bb));
|
|
ADD_OPCODE(CROR,(OP_REG bt, OP_REG ba, OP_REG bb));
|
|
ADD_OPCODE(BCCTR,(OP_REG bo, OP_REG bi, OP_REG bh, OP_REG lk));
|
|
END_OPCODES_GROUP(G_13);
|
|
|
|
ADD_OPCODE(RLWIMI,(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, OP_REG me, bool rc));
|
|
ADD_OPCODE(RLWINM,(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, OP_REG me, bool rc));
|
|
ADD_OPCODE(RLWNM,(OP_REG ra, OP_REG rs, OP_REG rb, OP_REG MB, OP_REG ME, bool rc));
|
|
ADD_OPCODE(ORI,(OP_REG rs, OP_REG ra, OP_uIMM uimm16));
|
|
ADD_OPCODE(ORIS,(OP_REG rs, OP_REG ra, OP_uIMM uimm16));
|
|
ADD_OPCODE(XORI,(OP_REG ra, OP_REG rs, OP_uIMM uimm16));
|
|
ADD_OPCODE(XORIS,(OP_REG ra, OP_REG rs, OP_uIMM uimm16));
|
|
ADD_OPCODE(ANDI_,(OP_REG ra, OP_REG rs, OP_uIMM uimm16));
|
|
ADD_OPCODE(ANDIS_,(OP_REG ra, OP_REG rs, OP_uIMM uimm16));
|
|
|
|
START_OPCODES_GROUP(G_1e)
|
|
ADD_OPCODE(RLDICL,(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, bool rc));
|
|
ADD_OPCODE(RLDICR,(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG me, bool rc));
|
|
ADD_OPCODE(RLDIC,(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, bool rc));
|
|
ADD_OPCODE(RLDIMI,(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, bool rc));
|
|
END_OPCODES_GROUP(G_1e);
|
|
|
|
START_OPCODES_GROUP(G_1f)
|
|
/*0x000*/ADD_OPCODE(CMP,(OP_REG crfd, OP_REG l, OP_REG ra, OP_REG rb));
|
|
/*0x004*/ADD_OPCODE(TW,(OP_uIMM to, OP_REG ra, OP_REG rb));
|
|
/*0x006*/ADD_OPCODE(LVSL,(OP_REG vd, OP_REG ra, OP_REG rb));
|
|
/*0x007*/ADD_OPCODE(LVEBX,(OP_REG vd, OP_REG ra, OP_REG rb));
|
|
/*0x008*/ADD_OPCODE(SUBFC,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
|
/*0x009*/ADD_OPCODE(MULHDU,(OP_REG rd, OP_REG ra, OP_REG rb, bool rc));
|
|
/*0x00a*/ADD_OPCODE(ADDC,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
|
/*0x00b*/ADD_OPCODE(MULHWU,(OP_REG rd, OP_REG ra, OP_REG rb, bool rc));
|
|
/*0x013*/ADD_OPCODE(MFOCRF,(OP_uIMM a, OP_REG rd, OP_uIMM crm));
|
|
/*0x014*/ADD_OPCODE(LWARX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
|
/*0x015*/ADD_OPCODE(LDX,(OP_REG ra, OP_REG rs, OP_REG rb));
|
|
/*0x017*/ADD_OPCODE(LWZX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
|
/*0x018*/ADD_OPCODE(SLW,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
|
/*0x01a*/ADD_OPCODE(CNTLZW,(OP_REG ra, OP_REG rs, bool rc));
|
|
/*0x01b*/ADD_OPCODE(SLD,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
|
/*0x01c*/ADD_OPCODE(AND,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
|
/*0x020*/ADD_OPCODE(CMPL,(OP_REG bf, OP_REG l, OP_REG ra, OP_REG rb));
|
|
/*0x026*/ADD_OPCODE(LVSR,(OP_REG vd, OP_REG ra, OP_REG rb));
|
|
/*0x027*/ADD_OPCODE(LVEHX,(OP_REG vd, OP_REG ra, OP_REG rb));
|
|
/*0x028*/ADD_OPCODE(SUBF,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
|
/*0x035*/ADD_OPCODE(LDUX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
|
/*0x036*/ADD_OPCODE(DCBST,(OP_REG ra, OP_REG rb));
|
|
/*0x03a*/ADD_OPCODE(CNTLZD,(OP_REG ra, OP_REG rs, bool rc));
|
|
/*0x03c*/ADD_OPCODE(ANDC,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
|
/*0x047*/ADD_OPCODE(LVEWX,(OP_REG vd, OP_REG ra, OP_REG rb));
|
|
/*0x049*/ADD_OPCODE(MULHD,(OP_REG rd, OP_REG ra, OP_REG rb, bool rc));
|
|
/*0x04b*/ADD_OPCODE(MULHW,(OP_REG rd, OP_REG ra, OP_REG rb, bool rc));
|
|
/*0x054*/ADD_OPCODE(LDARX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
|
/*0x056*/ADD_OPCODE(DCBF,(OP_REG ra, OP_REG rb));
|
|
/*0x057*/ADD_OPCODE(LBZX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
|
/*0x067*/ADD_OPCODE(LVX,(OP_REG vd, OP_REG ra, OP_REG rb));
|
|
/*0x068*/ADD_OPCODE(NEG,(OP_REG rd, OP_REG ra, OP_REG oe, bool rc));
|
|
/*0x077*/ADD_OPCODE(LBZUX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
|
/*0x07c*/ADD_OPCODE(NOR,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
|
/*0x087*/ADD_OPCODE(STVEBX,(OP_REG vs, OP_REG ra, OP_REG rb));
|
|
/*0x088*/ADD_OPCODE(SUBFE,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
|
/*0x08a*/ADD_OPCODE(ADDE,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
|
/*0x090*/ADD_OPCODE(MTOCRF,(OP_REG crm, OP_REG rs));
|
|
/*0x095*/ADD_OPCODE(STDX,(OP_REG rs, OP_REG ra, OP_REG rb));
|
|
/*0x096*/ADD_OPCODE(STWCX_,(OP_REG rs, OP_REG ra, OP_REG rb));
|
|
/*0x097*/ADD_OPCODE(STWX,(OP_REG rs, OP_REG ra, OP_REG rb));
|
|
/*0x0a7*/ADD_OPCODE(STVEHX,(OP_REG vs, OP_REG ra, OP_REG rb));
|
|
/*0x0b5*/ADD_OPCODE(STDUX,(OP_REG rs, OP_REG ra, OP_REG rb));
|
|
/*0x0c7*/ADD_OPCODE(STVEWX,(OP_REG vs, OP_REG ra, OP_REG rb));
|
|
/*0x0ca*/ADD_OPCODE(ADDZE,(OP_REG rd, OP_REG ra, OP_REG oe, bool rc));
|
|
/*0x0d6*/ADD_OPCODE(STDCX_,(OP_REG rs, OP_REG ra, OP_REG rb));
|
|
/*0x0d7*/ADD_OPCODE(STBX,(OP_REG rs, OP_REG ra, OP_REG rb));
|
|
/*0x0e7*/ADD_OPCODE(STVX,(OP_REG vs, OP_REG ra, OP_REG rb));
|
|
/*0x0e9*/ADD_OPCODE(MULLD,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
|
/*0x0ea*/ADD_OPCODE(ADDME,(OP_REG rd, OP_REG ra, OP_REG oe, bool rc));
|
|
/*0x0eb*/ADD_OPCODE(MULLW,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
|
/*0x0f6*/ADD_OPCODE(DCBTST,(OP_REG th, OP_REG ra, OP_REG rb));
|
|
/*0x10a*/ADD_OPCODE(ADD,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
|
/*0x116*/ADD_OPCODE(DCBT,(OP_REG ra, OP_REG rb, OP_REG th));
|
|
/*0x117*/ADD_OPCODE(LHZX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
|
/*0x11c*/ADD_OPCODE(EQV,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
|
/*0x136*/ADD_OPCODE(ECIWX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
|
/*0x137*/ADD_OPCODE(LHZUX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
|
/*0x13c*/ADD_OPCODE(XOR,(OP_REG rs, OP_REG ra, OP_REG rb, bool rc));
|
|
/*0x153*/ADD_OPCODE(MFSPR,(OP_REG rd, OP_REG spr));
|
|
/*0x156*/ADD_OPCODE(DST,(OP_REG ra, OP_REG rb, OP_uIMM strm, OP_uIMM t));
|
|
/*0x157*/ADD_OPCODE(LHAX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
|
/*0x167*/ADD_OPCODE(LVXL,(OP_REG vd, OP_REG ra, OP_REG rb));
|
|
/*0x168*/ADD_OPCODE(ABS,(OP_REG rd, OP_REG ra, OP_REG oe, bool rc));
|
|
/*0x173*/ADD_OPCODE(MFTB,(OP_REG rd, OP_REG spr));
|
|
/*0x176*/ADD_OPCODE(DSTST,(OP_REG ra, OP_REG rb, OP_uIMM strm, OP_uIMM t));
|
|
/*0x177*/ADD_OPCODE(LHAUX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
|
/*0x197*/ADD_OPCODE(STHX,(OP_REG rs, OP_REG ra, OP_REG rb));
|
|
/*0x19c*/ADD_OPCODE(ORC,(OP_REG rs, OP_REG ra, OP_REG rb, bool rc));
|
|
/*0x1b6*/ADD_OPCODE(ECOWX,(OP_REG rs, OP_REG ra, OP_REG rb));
|
|
/*0x1bc*/ADD_OPCODE(OR,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
|
/*0x1c9*/ADD_OPCODE(DIVDU,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
|
/*0x1cb*/ADD_OPCODE(DIVWU,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
|
/*0x1d3*/ADD_OPCODE(MTSPR,(OP_REG spr, OP_REG rs));
|
|
/*0x1d6*///DCBI
|
|
/*0x1dc*/ADD_OPCODE(NAND,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
|
/*0x1e7*/ADD_OPCODE(STVXL,(OP_REG vs, OP_REG ra, OP_REG rb));
|
|
/*0x1e9*/ADD_OPCODE(DIVD,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
|
/*0x1eb*/ADD_OPCODE(DIVW,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
|
/*0x207*/ADD_OPCODE(LVLX,(OP_REG vd, OP_REG ra, OP_REG rb));
|
|
/*0x216*/ADD_OPCODE(LWBRX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
|
/*0x217*/ADD_OPCODE(LFSX,(OP_REG frd, OP_REG ra, OP_REG rb));
|
|
/*0x218*/ADD_OPCODE(SRW,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
|
/*0x21b*/ADD_OPCODE(SRD,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
|
/*0x227*/ADD_OPCODE(LVRX,(OP_REG vd, OP_REG ra, OP_REG rb));
|
|
/*0x237*/ADD_OPCODE(LFSUX,(OP_REG frd, OP_REG ra, OP_REG rb));
|
|
/*0x256*/ADD_OPCODE(SYNC,(OP_uIMM l));
|
|
/*0x257*/ADD_OPCODE(LFDX,(OP_REG frd, OP_REG ra, OP_REG rb));
|
|
/*0x277*/ADD_OPCODE(LFDUX,(OP_REG frd, OP_REG ra, OP_REG rb));
|
|
/*0x287*/ADD_OPCODE(STVLX,(OP_REG vs, OP_REG ra, OP_REG rb));
|
|
/*0x297*/ADD_OPCODE(STFSX,(OP_REG frs, OP_REG ra, OP_REG rb));
|
|
/*0x2a7*/ADD_OPCODE(STVRX,(OP_REG vs, OP_REG ra, OP_REG rb));
|
|
/*0x2d7*/ADD_OPCODE(STFDX,(OP_REG frs, OP_REG ra, OP_REG rb));
|
|
/*0x307*/ADD_OPCODE(LVLXL,(OP_REG vd, OP_REG ra, OP_REG rb));
|
|
/*0x316*/ADD_OPCODE(LHBRX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
|
/*0x318*/ADD_OPCODE(SRAW,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
|
/*0x31a*/ADD_OPCODE(SRAD,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
|
/*0x327*/ADD_OPCODE(LVRXL,(OP_REG vd, OP_REG ra, OP_REG rb));
|
|
/*0x336*/ADD_OPCODE(DSS,(OP_uIMM strm, OP_uIMM a));
|
|
/*0x338*/ADD_OPCODE(SRAWI,(OP_REG ra, OP_REG rs, OP_REG sh, bool rc));
|
|
/*0x33a*/ADD_OPCODE(SRADI1,(OP_REG ra, OP_REG rs, OP_REG sh, bool rc));
|
|
/*0x33b*/ADD_OPCODE(SRADI2,(OP_REG ra, OP_REG rs, OP_REG sh, bool rc));
|
|
/*0x356*/ADD_OPCODE(EIEIO,());
|
|
/*0x387*/ADD_OPCODE(STVLXL,(OP_REG sd, OP_REG ra, OP_REG rb));
|
|
/*0x39a*/ADD_OPCODE(EXTSH,(OP_REG ra, OP_REG rs, bool rc));
|
|
/*0x3a7*/ADD_OPCODE(STVRXL,(OP_REG sd, OP_REG ra, OP_REG rb));
|
|
/*0x3ba*/ADD_OPCODE(EXTSB,(OP_REG ra, OP_REG rs, bool rc));
|
|
/*0x3d7*/ADD_OPCODE(STFIWX,(OP_REG frs, OP_REG ra, OP_REG rb));
|
|
/*0x3da*/ADD_OPCODE(EXTSW,(OP_REG ra, OP_REG rs, bool rc));
|
|
/*0x3d6*///ICBI
|
|
/*0x3f6*/ADD_OPCODE(DCBZ,(OP_REG ra, OP_REG rb));
|
|
END_OPCODES_GROUP(G_1f);
|
|
|
|
ADD_OPCODE(LWZ,(OP_REG rd, OP_REG ra, OP_sIMM d));
|
|
ADD_OPCODE(LWZU,(OP_REG rd, OP_REG ra, OP_sIMM d));
|
|
ADD_OPCODE(LBZ,(OP_REG rd, OP_REG ra, OP_sIMM d));
|
|
ADD_OPCODE(LBZU,(OP_REG rd, OP_REG ra, OP_sIMM d));
|
|
ADD_OPCODE(STW,(OP_REG rs, OP_REG ra, OP_sIMM d));
|
|
ADD_OPCODE(STWU,(OP_REG rs, OP_REG ra, OP_sIMM d));
|
|
ADD_OPCODE(STB,(OP_REG rs, OP_REG ra, OP_sIMM d));
|
|
ADD_OPCODE(STBU,(OP_REG rs, OP_REG ra, OP_sIMM d));
|
|
ADD_OPCODE(LHZ,(OP_REG rd, OP_REG ra, OP_sIMM d));
|
|
ADD_OPCODE(LHZU,(OP_REG rd, OP_REG ra, OP_sIMM d));
|
|
ADD_OPCODE(STH,(OP_REG rs, OP_REG ra, OP_sIMM d));
|
|
ADD_OPCODE(STHU,(OP_REG rs, OP_REG ra, OP_sIMM d));
|
|
ADD_OPCODE(LMW,(OP_REG rd, OP_REG ra, OP_sIMM d));
|
|
ADD_OPCODE(STMW,(OP_REG rs, OP_REG ra, OP_sIMM d));
|
|
ADD_OPCODE(LFS,(OP_REG frd, OP_REG ra, OP_sIMM d));
|
|
ADD_OPCODE(LFSU,(OP_REG frd, OP_REG ra, OP_sIMM d));
|
|
ADD_OPCODE(LFD,(OP_REG frd, OP_REG ra, OP_sIMM d));
|
|
ADD_OPCODE(LFDU,(OP_REG frd, OP_REG ra, OP_sIMM d));
|
|
ADD_OPCODE(STFS,(OP_REG frs, OP_REG ra, OP_sIMM d));
|
|
ADD_OPCODE(STFSU,(OP_REG frs, OP_REG ra, OP_sIMM d));
|
|
ADD_OPCODE(STFD,(OP_REG frs, OP_REG ra, OP_sIMM d));
|
|
ADD_OPCODE(STFDU,(OP_REG frs, OP_REG ra, OP_sIMM d));
|
|
|
|
START_OPCODES_GROUP(G_3a)
|
|
ADD_OPCODE(LD,(OP_REG rd, OP_REG ra, OP_sIMM ds));
|
|
ADD_OPCODE(LDU,(OP_REG rd, OP_REG ra, OP_sIMM ds));
|
|
END_OPCODES_GROUP(G_3a);
|
|
|
|
START_OPCODES_GROUP(G_3b)
|
|
ADD_OPCODE(FDIVS,(OP_REG frd, OP_REG fra, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FSUBS,(OP_REG frd, OP_REG fra, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FADDS,(OP_REG frd, OP_REG fra, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FSQRTS,(OP_REG frd, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FRES,(OP_REG frd, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FMULS,(OP_REG frd, OP_REG fra, OP_REG frc, bool rc));
|
|
ADD_OPCODE(FMADDS,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FMSUBS,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FNMSUBS,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FNMADDS,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc));
|
|
END_OPCODES_GROUP(G_3b);
|
|
|
|
START_OPCODES_GROUP(G_3e)
|
|
ADD_OPCODE(STD,(OP_REG rs, OP_REG ra, OP_sIMM ds));
|
|
ADD_OPCODE(STDU,(OP_REG rs, OP_REG ra, OP_sIMM ds));
|
|
END_OPCODES_GROUP(G_3e);
|
|
|
|
START_OPCODES_GROUP(G_3f)
|
|
ADD_OPCODE(MTFSB1,(OP_REG bt, bool rc));
|
|
ADD_OPCODE(MCRFS,(OP_REG bf, OP_REG bfa));
|
|
ADD_OPCODE(MTFSB0,(OP_REG bt, bool rc));
|
|
ADD_OPCODE(MTFSFI,(OP_REG crfd, OP_REG i, bool rc));
|
|
ADD_OPCODE(MFFS,(OP_REG frd, bool rc));
|
|
ADD_OPCODE(MTFSF,(OP_REG flm, OP_REG frb, bool rc));
|
|
|
|
ADD_OPCODE(FCMPU,(OP_REG bf, OP_REG fra, OP_REG frb));
|
|
ADD_OPCODE(FRSP,(OP_REG frd, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FCTIW,(OP_REG frd, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FCTIWZ,(OP_REG frd, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FDIV,(OP_REG frd, OP_REG fra, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FSUB,(OP_REG frd, OP_REG fra, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FADD,(OP_REG frd, OP_REG fra, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FSQRT,(OP_REG frd, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FSEL,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FMUL,(OP_REG frd, OP_REG fra, OP_REG frc, bool rc));
|
|
ADD_OPCODE(FRSQRTE,(OP_REG frd, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FMSUB,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FMADD,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FNMSUB,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FNMADD,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FCMPO,(OP_REG crfd, OP_REG fra, OP_REG frb));
|
|
ADD_OPCODE(FNEG,(OP_REG frd, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FMR,(OP_REG frd, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FNABS,(OP_REG frd, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FABS,(OP_REG frd, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FCTID,(OP_REG frd, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FCTIDZ,(OP_REG frd, OP_REG frb, bool rc));
|
|
ADD_OPCODE(FCFID,(OP_REG frd, OP_REG frb, bool rc));
|
|
END_OPCODES_GROUP(G_3f);
|
|
|
|
ADD_OPCODE(UNK,(const u32 code, const u32 opcode, const u32 gcode));
|
|
};
|
|
|
|
//instr_caller* g_instrs[0x40];
|
|
|
|
#undef START_OPCODES_GROUP
|
|
#undef ADD_OPCODE
|
|
#undef ADD_NULL_OPCODE
|
|
#undef END_OPCODES_GROUP |