mirror of
https://github.com/RPCSX/rpcsx.git
synced 2026-01-21 08:00:54 +01:00
4185b1aa40
initial 2d tiler implementation fixed mtbuf index order simplify v_mac_*_f32 instructions
370 lines
13 KiB
C++
370 lines
13 KiB
C++
#include "amdgpu/tiler_vulkan.hpp"
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#include "Scheduler.hpp"
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#include "amdgpu/tiler.hpp"
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#include <bit>
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#include <cstring>
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#include <memory>
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#include <vk.hpp>
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#include <shaders/detiler1d.comp.h>
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#include <shaders/detiler2d.comp.h>
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#include <shaders/detilerLinear.comp.h>
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#include <shaders/tiler1d.comp.h>
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#include <shaders/tiler2d.comp.h>
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#include <shaders/tilerLinear.comp.h>
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struct TilerDecriptorSetLayout {
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VkDescriptorSetLayout layout;
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TilerDecriptorSetLayout() {
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std::vector<VkDescriptorSetLayoutBinding> bindings{{
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.binding = 0,
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.descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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}};
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VkDescriptorSetLayoutCreateInfo layoutInfo{
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
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.bindingCount = static_cast<uint32_t>(bindings.size()),
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.pBindings = bindings.data(),
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};
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VK_VERIFY(vkCreateDescriptorSetLayout(vk::context->device, &layoutInfo,
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nullptr, &layout));
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}
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~TilerDecriptorSetLayout() {
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vkDestroyDescriptorSetLayout(vk::context->device, layout,
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vk::context->allocator);
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}
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};
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struct TilerShader {
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VkShaderEXT shader;
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TilerShader(TilerDecriptorSetLayout &setLayout,
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std::span<const std::uint32_t> spirv) {
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VkShaderCreateInfoEXT shaderInfo{
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.sType = VK_STRUCTURE_TYPE_SHADER_CREATE_INFO_EXT,
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.flags = 0,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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.nextStage = 0,
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.codeType = VK_SHADER_CODE_TYPE_SPIRV_EXT,
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.codeSize = spirv.size_bytes(),
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.pCode = spirv.data(),
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.pName = "main",
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.setLayoutCount = 1,
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.pSetLayouts = &setLayout.layout,
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.pushConstantRangeCount = 0,
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.pPushConstantRanges = 0,
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.pSpecializationInfo = 0,
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};
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VK_VERIFY(vk::CreateShadersEXT(vk::context->device, 1, &shaderInfo, nullptr,
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&shader));
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}
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~TilerShader() {
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vk::DestroyShaderEXT(vk::context->device, shader, vk::context->allocator);
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}
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};
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struct amdgpu::GpuTiler::Impl {
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TilerDecriptorSetLayout descriptorSetLayout;
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std::mutex descriptorMtx;
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VkDescriptorSet descriptorSets[32]{};
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VkDescriptorPool descriptorPool;
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std::uint32_t inUseDescriptorSets = 0;
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vk::Buffer configData;
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TilerShader detilerLinear{descriptorSetLayout, spirv_detilerLinear_comp};
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TilerShader detiler1d{descriptorSetLayout, spirv_detiler1d_comp};
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TilerShader detiler2d{descriptorSetLayout, spirv_detilerLinear_comp};
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TilerShader tilerLinear{descriptorSetLayout, spirv_tiler2d_comp};
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TilerShader tiler1d{descriptorSetLayout, spirv_tiler1d_comp};
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TilerShader tiler2d{descriptorSetLayout, spirv_tiler2d_comp};
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VkPipelineLayout pipelineLayout;
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struct Config {
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uint64_t srcAddress;
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uint64_t dstAddress;
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uint32_t dataWidth;
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uint32_t dataHeight;
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uint32_t tileMode;
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uint32_t macroTileMode;
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uint32_t dfmt;
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uint32_t numFragments;
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uint32_t bitsPerElement;
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uint32_t tiledSurfaceSize;
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uint32_t linearSurfaceSize;
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uint32_t padding[2];
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};
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Impl() {
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std::size_t count = 256;
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configData = vk::Buffer::Allocate(
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vk::getHostVisibleMemory(), sizeof(Config) * count,
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VK_BUFFER_USAGE_TRANSFER_DST_BIT | VK_BUFFER_USAGE_TRANSFER_SRC_BIT |
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VK_BUFFER_USAGE_UNIFORM_BUFFER_BIT);
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VkPipelineLayoutCreateInfo piplineLayoutInfo{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
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.setLayoutCount = 1,
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.pSetLayouts = &descriptorSetLayout.layout,
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};
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VK_VERIFY(vkCreatePipelineLayout(vk::context->device, &piplineLayoutInfo,
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nullptr, &pipelineLayout));
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{
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VkDescriptorPoolSize poolSizes[]{{
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.type = VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER,
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.descriptorCount =
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static_cast<std::uint32_t>(std::size(descriptorSets)) * 2,
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}};
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VkDescriptorPoolCreateInfo info{
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_POOL_CREATE_INFO,
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.maxSets = static_cast<std::uint32_t>(std::size(descriptorSets)) * 2,
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.poolSizeCount = static_cast<uint32_t>(std::size(poolSizes)),
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.pPoolSizes = poolSizes,
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};
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VK_VERIFY(vkCreateDescriptorPool(
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vk::context->device, &info, vk::context->allocator, &descriptorPool));
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}
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VkDescriptorSetAllocateInfo info{
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_ALLOCATE_INFO,
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.descriptorPool = descriptorPool,
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.descriptorSetCount = 1,
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.pSetLayouts = &descriptorSetLayout.layout,
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};
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for (std::size_t i = 0; i < std::size(descriptorSets); ++i) {
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VK_VERIFY(vkAllocateDescriptorSets(vk::context->device, &info,
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descriptorSets + i));
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}
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}
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~Impl() {
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vkDestroyDescriptorPool(vk::context->device, descriptorPool,
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vk::context->allocator);
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vkDestroyPipelineLayout(vk::context->device, pipelineLayout,
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vk::context->allocator);
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}
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std::uint32_t allocateDescriptorSlot() {
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std::lock_guard lock(descriptorMtx);
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auto result = std::countl_one(inUseDescriptorSets);
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rx::dieIf(result >= std::size(descriptorSets),
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"out of tiler descriptor sets");
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inUseDescriptorSets |= (1 << result);
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return result;
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}
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void releaseDescriptorSlot(std::uint32_t slot) {
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std::lock_guard lock(descriptorMtx);
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inUseDescriptorSets &= ~(1u << slot);
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}
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};
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amdgpu::GpuTiler::GpuTiler() { mImpl = std::make_unique<Impl>(); }
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amdgpu::GpuTiler::~GpuTiler() = default;
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void amdgpu::GpuTiler::detile(Scheduler &scheduler,
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const amdgpu::SurfaceInfo &info,
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amdgpu::TileMode tileMode, gnm::DataFormat dfmt,
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std::uint64_t srcTiledAddress,
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std::uint64_t dstLinearAddress, int mipLevel,
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int baseArray, int arrayCount) {
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auto commandBuffer = scheduler.getCommandBuffer();
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auto slot = mImpl->allocateDescriptorSlot();
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auto configOffset = slot * sizeof(Impl::Config);
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auto config = reinterpret_cast<Impl::Config *>(mImpl->configData.getData() +
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configOffset);
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auto &subresource = info.getSubresourceInfo(mipLevel);
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config->srcAddress = srcTiledAddress + subresource.offset +
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(subresource.tiledSize * baseArray);
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config->dstAddress = dstLinearAddress + (subresource.linearSize * baseArray);
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config->dataWidth = subresource.dataWidth;
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config->dataHeight = subresource.dataHeight;
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config->tileMode = tileMode.raw;
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config->dfmt = dfmt;
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config->numFragments = info.numFragments;
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config->bitsPerElement = info.bitsPerElement;
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uint32_t groupCountZ = subresource.dataDepth;
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if (arrayCount > 1) {
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config->tiledSurfaceSize = subresource.tiledSize;
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config->linearSurfaceSize = subresource.linearSize;
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groupCountZ = arrayCount;
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} else {
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config->tiledSurfaceSize = 0;
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config->linearSurfaceSize = 0;
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}
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VkShaderStageFlagBits stages[]{VK_SHADER_STAGE_COMPUTE_BIT};
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switch (tileMode.arrayMode()) {
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case amdgpu::kArrayModeLinearGeneral:
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case amdgpu::kArrayModeLinearAligned:
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vk::CmdBindShadersEXT(commandBuffer, 1, stages,
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&mImpl->detilerLinear.shader);
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break;
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case amdgpu::kArrayMode1dTiledThin:
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case amdgpu::kArrayMode1dTiledThick:
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vk::CmdBindShadersEXT(commandBuffer, 1, stages, &mImpl->detiler1d.shader);
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break;
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case amdgpu::kArrayMode2dTiledThin:
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case amdgpu::kArrayModeTiledThinPrt:
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case amdgpu::kArrayMode2dTiledThinPrt:
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case amdgpu::kArrayMode2dTiledThick:
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case amdgpu::kArrayMode2dTiledXThick:
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case amdgpu::kArrayModeTiledThickPrt:
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case amdgpu::kArrayMode2dTiledThickPrt:
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case amdgpu::kArrayMode3dTiledThinPrt:
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case amdgpu::kArrayMode3dTiledThin:
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case amdgpu::kArrayMode3dTiledThick:
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case amdgpu::kArrayMode3dTiledXThick:
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case amdgpu::kArrayMode3dTiledThickPrt:
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config->macroTileMode =
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getDefaultMacroTileModes()[computeMacroTileIndex(
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tileMode, info.bitsPerElement,
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1 << info.numFragments)]
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.raw;
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vk::CmdBindShadersEXT(commandBuffer, 1, stages, &mImpl->detiler1d.shader);
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break;
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}
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VkDescriptorBufferInfo bufferInfo{
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.buffer = mImpl->configData.getHandle(),
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.offset = configOffset,
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.range = sizeof(Impl::Config),
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};
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VkWriteDescriptorSet writeDescSet{
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.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstSet = mImpl->descriptorSets[slot],
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.dstBinding = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER,
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.pBufferInfo = &bufferInfo,
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};
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vkUpdateDescriptorSets(vk::context->device, 1, &writeDescSet, 0, nullptr);
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vkCmdBindDescriptorSets(commandBuffer, VK_PIPELINE_BIND_POINT_COMPUTE,
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mImpl->pipelineLayout, 0, 1,
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&mImpl->descriptorSets[slot], 0, nullptr);
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vkCmdDispatch(commandBuffer, subresource.dataWidth, subresource.dataHeight,
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groupCountZ);
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scheduler.afterSubmit([this, slot] { mImpl->releaseDescriptorSlot(slot); });
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}
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void amdgpu::GpuTiler::tile(Scheduler &scheduler,
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const amdgpu::SurfaceInfo &info,
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amdgpu::TileMode tileMode, gnm::DataFormat dfmt,
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std::uint64_t srcLinearAddress,
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std::uint64_t dstTiledAddress, int mipLevel,
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int baseArray, int arrayCount) {
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auto commandBuffer = scheduler.getCommandBuffer();
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auto slot = mImpl->allocateDescriptorSlot();
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auto configOffset = slot * sizeof(Impl::Config);
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auto config = reinterpret_cast<Impl::Config *>(mImpl->configData.getData() +
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configOffset);
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auto &subresource = info.getSubresourceInfo(mipLevel);
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config->srcAddress = srcLinearAddress + subresource.offset +
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subresource.linearSize * baseArray;
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config->dstAddress = dstTiledAddress;
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config->dataWidth = subresource.dataWidth;
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config->dataHeight = subresource.dataHeight;
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config->tileMode = tileMode.raw;
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config->dfmt = dfmt;
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config->numFragments = info.numFragments;
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config->bitsPerElement = info.bitsPerElement;
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uint32_t groupCountZ = subresource.dataDepth;
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if (arrayCount > 1) {
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config->tiledSurfaceSize = subresource.tiledSize;
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config->linearSurfaceSize = subresource.linearSize;
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groupCountZ = arrayCount;
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} else {
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config->tiledSurfaceSize = 0;
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config->linearSurfaceSize = 0;
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}
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VkShaderStageFlagBits stages[]{VK_SHADER_STAGE_COMPUTE_BIT};
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switch (tileMode.arrayMode()) {
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case amdgpu::kArrayModeLinearGeneral:
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case amdgpu::kArrayModeLinearAligned:
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vk::CmdBindShadersEXT(commandBuffer, 1, stages, &mImpl->tilerLinear.shader);
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break;
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case amdgpu::kArrayMode1dTiledThin:
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case amdgpu::kArrayMode1dTiledThick:
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vk::CmdBindShadersEXT(commandBuffer, 1, stages, &mImpl->tiler1d.shader);
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break;
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case amdgpu::kArrayMode2dTiledThin:
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case amdgpu::kArrayModeTiledThinPrt:
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case amdgpu::kArrayMode2dTiledThinPrt:
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case amdgpu::kArrayMode2dTiledThick:
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case amdgpu::kArrayMode2dTiledXThick:
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case amdgpu::kArrayModeTiledThickPrt:
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case amdgpu::kArrayMode2dTiledThickPrt:
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case amdgpu::kArrayMode3dTiledThinPrt:
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case amdgpu::kArrayMode3dTiledThin:
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case amdgpu::kArrayMode3dTiledThick:
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case amdgpu::kArrayMode3dTiledXThick:
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case amdgpu::kArrayMode3dTiledThickPrt:
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config->macroTileMode =
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getDefaultMacroTileModes()[computeMacroTileIndex(
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tileMode, info.bitsPerElement,
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1 << info.numFragments)]
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.raw;
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vk::CmdBindShadersEXT(commandBuffer, 1, stages, &mImpl->tiler1d.shader);
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break;
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}
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VkDescriptorBufferInfo bufferInfo{
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.buffer = mImpl->configData.getHandle(),
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.offset = configOffset,
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.range = sizeof(Impl::Config),
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};
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VkWriteDescriptorSet writeDescSet{
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.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstSet = mImpl->descriptorSets[slot],
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.dstBinding = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER,
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.pBufferInfo = &bufferInfo,
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};
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vkUpdateDescriptorSets(vk::context->device, 1, &writeDescSet, 0, nullptr);
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vkCmdBindDescriptorSets(commandBuffer, VK_PIPELINE_BIND_POINT_COMPUTE,
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mImpl->pipelineLayout, 0, 1,
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&mImpl->descriptorSets[slot], 0, nullptr);
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vkCmdDispatch(commandBuffer, subresource.dataWidth, subresource.dataHeight,
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groupCountZ);
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scheduler.afterSubmit([this, slot] { mImpl->releaseDescriptorSlot(slot); });
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}
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