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https://github.com/RPCSX/rpcsx.git
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16f5167aed
This restores some functionality removed in SPU ASMJIT v2.0 Also implements new experimental features
548 lines
11 KiB
C++
548 lines
11 KiB
C++
#include "stdafx.h"
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#include "Emu/System.h"
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#include "Emu/IdManager.h"
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#include "Emu/Memory/Memory.h"
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#include "SPUThread.h"
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#include "SPUAnalyser.h"
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#include "SPUInterpreter.h"
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#include "SPUDisAsm.h"
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#include "SPURecompiler.h"
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#include <algorithm>
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#include <mutex>
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#include <thread>
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extern u64 get_system_time();
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const spu_decoder<spu_itype> s_spu_itype;
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spu_recompiler_base::spu_recompiler_base(SPUThread& spu)
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: m_spu(spu)
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{
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// Initialize lookup table
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spu.jit_dispatcher.fill(&dispatch);
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}
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spu_recompiler_base::~spu_recompiler_base()
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{
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}
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void spu_recompiler_base::dispatch(SPUThread& spu, void*, u8* rip)
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{
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// If check failed after direct branch, patch it with single NOP
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if (rip)
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{
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#ifdef _MSC_VER
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*(volatile u64*)(rip) = 0x841f0f;
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#else
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__atomic_store_n(reinterpret_cast<u64*>(rip), 0x841f0f, __ATOMIC_RELAXED);
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#endif
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}
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const auto func = spu.jit->get(spu.pc);
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// First attempt (load new trampoline and retry)
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if (func != spu.jit_dispatcher[spu.pc / 4])
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{
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spu.jit_dispatcher[spu.pc / 4] = func;
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return;
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}
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// Second attempt (recover from the recursion after repeated unsuccessful trampoline call)
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if (spu.block_counter != spu.block_recover && func != &dispatch)
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{
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spu.block_recover = spu.block_counter;
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return;
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}
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// Compile
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verify(HERE), spu.jit->compile(block(spu, spu.pc, &spu.jit->m_block_info));
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spu.jit_dispatcher[spu.pc / 4] = spu.jit->get(spu.pc);
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}
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void spu_recompiler_base::branch(SPUThread& spu, void*, u8* rip)
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{
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const auto pair = *reinterpret_cast<std::pair<const std::vector<u32>, spu_function_t>**>(rip + 24);
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spu.pc = pair->first[0];
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const auto func = pair->second ? pair->second : spu.jit->compile(pair->first);
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verify(HERE), func, pair->second == func;
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// Overwrite function address
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reinterpret_cast<atomic_t<spu_function_t>*>(rip + 32)->store(func);
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// Overwrite jump to this function with jump to the compiled function
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const s64 rel = reinterpret_cast<u64>(func) - reinterpret_cast<u64>(rip) - 5;
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alignas(8) u8 bytes[8];
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if (rel >= INT32_MIN && rel <= INT32_MAX)
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{
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const s64 rel8 = (rel + 5) - 2;
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if (rel8 >= INT8_MIN && rel8 <= INT8_MAX)
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{
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bytes[0] = 0xeb; // jmp rel8
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bytes[1] = static_cast<s8>(rel8);
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std::memset(bytes + 2, 0x90, 6);
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}
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else
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{
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bytes[0] = 0xe9; // jmp rel32
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std::memcpy(bytes + 1, &rel, 4);
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std::memset(bytes + 5, 0x90, 3);
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}
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}
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else
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{
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bytes[0] = 0xff; // jmp [rip+26]
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bytes[1] = 0x25;
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bytes[2] = 0x1a;
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bytes[3] = 0x00;
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bytes[4] = 0x00;
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bytes[5] = 0x00;
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bytes[6] = 0x90;
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bytes[7] = 0x90;
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}
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#ifdef _MSC_VER
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*(volatile u64*)(rip) = *reinterpret_cast<u64*>(+bytes);
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#else
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__atomic_store_n(reinterpret_cast<u64*>(rip), *reinterpret_cast<u64*>(+bytes), __ATOMIC_RELAXED);
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#endif
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}
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std::vector<u32> spu_recompiler_base::block(SPUThread& spu, u32 lsa, std::bitset<0x10000>* out_info)
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{
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// Block info (local)
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std::bitset<0x10000> block_info{};
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// Select one to use
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std::bitset<0x10000>& blocks = out_info ? *out_info : block_info;
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if (out_info)
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{
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out_info->reset();
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}
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// Result: addr + raw instruction data
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std::vector<u32> result;
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result.reserve(256);
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result.push_back(lsa);
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blocks.set(lsa / 4);
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// Simple block entry workload list
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std::vector<u32> wl;
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wl.push_back(lsa);
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// Value flags (TODO)
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enum class vf : u32
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{
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is_const,
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is_mask,
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__bitset_enum_max
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};
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// Weak constant propagation context (for guessing branch targets)
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std::array<bs_t<vf>, 128> vflags{};
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// Associated constant values for 32-bit preferred slot
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std::array<u32, 128> values;
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if (spu.pc == lsa && g_cfg.core.spu_block_size == spu_block_size_type::giga)
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{
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// TODO: use current register values for speculations
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vflags[0] = +vf::is_const;
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values[0] = spu.gpr[0]._u32[3];
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}
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for (u32 wi = 0; wi < wl.size();)
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{
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const auto next_block = [&]
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{
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// Reset value information
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vflags.fill({});
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wi++;
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};
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const auto add_block = [&](u32 target)
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{
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// Verify validity of the new target (TODO)
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if (target > lsa)
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{
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// Check for redundancy
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if (!blocks[target / 4])
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{
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blocks[target / 4] = true;
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wl.push_back(target);
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return;
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}
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}
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};
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const u32 pos = wl[wi];
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const u32 data = spu._ref<u32>(pos);
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const auto op = spu_opcode_t{data};
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wl[wi] += 4;
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// Analyse instruction
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switch (const auto type = s_spu_itype.decode(data))
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{
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case spu_itype::UNK:
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case spu_itype::DFCEQ:
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case spu_itype::DFCMEQ:
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case spu_itype::DFCGT:
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//case spu_itype::DFCMGT:
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case spu_itype::DFTSV:
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{
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// Stop on invalid instructions (TODO)
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blocks[pos / 4] = true;
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next_block();
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continue;
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}
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case spu_itype::SYNC:
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case spu_itype::DSYNC:
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case spu_itype::STOP:
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case spu_itype::STOPD:
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{
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if (data == 0)
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{
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// Stop before null data
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blocks[pos / 4] = true;
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next_block();
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continue;
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}
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if (g_cfg.core.spu_block_size != spu_block_size_type::giga)
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{
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// Stop on special instructions (TODO)
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next_block();
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break;
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}
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break;
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}
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case spu_itype::IRET:
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{
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next_block();
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break;
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}
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case spu_itype::BI:
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case spu_itype::BISL:
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case spu_itype::BIZ:
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case spu_itype::BINZ:
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case spu_itype::BIHZ:
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case spu_itype::BIHNZ:
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{
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const auto af = vflags[op.ra];
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const auto av = values[op.ra];
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if (type == spu_itype::BISL)
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{
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vflags[op.rt] = +vf::is_const;
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values[op.rt] = pos + 4;
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}
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if (test(af, vf::is_const))
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{
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const u32 target = spu_branch_target(av);
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if (target == pos + 4)
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{
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// Nop (unless BISL)
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break;
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}
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if (type != spu_itype::BISL || g_cfg.core.spu_block_size == spu_block_size_type::giga)
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{
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// TODO
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if (g_cfg.core.spu_block_size != spu_block_size_type::safe)
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{
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add_block(target);
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}
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}
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if (type == spu_itype::BISL && target < lsa)
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{
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next_block();
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break;
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}
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}
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else if (type == spu_itype::BI && !op.d && !op.e)
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{
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// Analyse jump table (TODO)
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std::basic_string<u32> jt_abs;
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std::basic_string<u32> jt_rel;
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const u32 start = pos + 4;
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const u32 limit = 0x40000;
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for (u32 i = start; i < limit; i += 4)
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{
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const u32 target = spu._ref<u32>(i);
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if (target % 4)
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{
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// Address cannot be misaligned: abort
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break;
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}
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if (target >= lsa && target < limit)
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{
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// Possible jump table entry (absolute)
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jt_abs.push_back(target);
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}
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if (target + start >= lsa && target + start < limit)
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{
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// Possible jump table entry (relative)
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jt_rel.push_back(target + start);
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}
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if (std::max(jt_abs.size(), jt_rel.size()) * 4 + start <= i)
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{
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// Neither type of jump table completes
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break;
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}
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}
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// Add detected jump table blocks (TODO: avoid adding both)
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if (jt_abs.size() >= 3 || jt_rel.size() >= 3)
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{
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if (jt_abs.size() >= jt_rel.size())
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{
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for (u32 target : jt_abs)
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{
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add_block(target);
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}
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}
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if (jt_rel.size() >= jt_abs.size())
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{
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for (u32 target : jt_rel)
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{
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add_block(target);
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}
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}
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}
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}
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if (type == spu_itype::BI || type == spu_itype::BISL || g_cfg.core.spu_block_size == spu_block_size_type::safe)
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{
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if (type == spu_itype::BI || g_cfg.core.spu_block_size != spu_block_size_type::giga)
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{
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next_block();
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break;
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}
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}
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break;
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}
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case spu_itype::BRSL:
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case spu_itype::BRASL:
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{
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const u32 target = spu_branch_target(type == spu_itype::BRASL ? 0 : pos, op.i16);
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vflags[op.rt] = +vf::is_const;
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values[op.rt] = pos + 4;
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if (target == pos + 4)
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{
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// Get next instruction address idiom
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break;
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}
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if (target < lsa || g_cfg.core.spu_block_size != spu_block_size_type::giga)
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{
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// Stop on direct calls
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next_block();
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break;
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}
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if (g_cfg.core.spu_block_size == spu_block_size_type::giga)
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{
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add_block(target);
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}
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break;
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}
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case spu_itype::BR:
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case spu_itype::BRA:
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case spu_itype::BRZ:
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case spu_itype::BRNZ:
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case spu_itype::BRHZ:
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case spu_itype::BRHNZ:
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{
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const u32 target = spu_branch_target(type == spu_itype::BRA ? 0 : pos, op.i16);
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if (target == pos + 4)
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{
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// Nop
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break;
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}
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add_block(target);
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if (type == spu_itype::BR || type == spu_itype::BRA)
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{
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// Stop on direct branches
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next_block();
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break;
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}
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break;
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}
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case spu_itype::HEQ:
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case spu_itype::HEQI:
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case spu_itype::HGT:
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case spu_itype::HGTI:
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case spu_itype::HLGT:
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case spu_itype::HLGTI:
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case spu_itype::HBR:
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case spu_itype::HBRA:
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case spu_itype::HBRR:
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case spu_itype::LNOP:
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case spu_itype::NOP:
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case spu_itype::MTSPR:
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case spu_itype::WRCH:
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case spu_itype::FSCRWR:
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case spu_itype::STQA:
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case spu_itype::STQD:
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case spu_itype::STQR:
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case spu_itype::STQX:
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{
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// Do nothing
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break;
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}
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case spu_itype::IL:
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{
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vflags[op.rt] = +vf::is_const;
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values[op.rt] = op.si16;
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break;
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}
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case spu_itype::ILA:
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{
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vflags[op.rt] = +vf::is_const;
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values[op.rt] = op.i18;
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break;
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}
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case spu_itype::ILH:
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{
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vflags[op.rt] = +vf::is_const;
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values[op.rt] = op.i16 << 16 | op.i16;
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break;
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}
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case spu_itype::ILHU:
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{
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vflags[op.rt] = +vf::is_const;
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values[op.rt] = op.i16 << 16;
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break;
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}
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case spu_itype::IOHL:
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{
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values[op.rt] = values[op.rt] | op.i16;
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break;
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}
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case spu_itype::ORI:
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{
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vflags[op.rt] = vflags[op.ra] & vf::is_const;
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values[op.rt] = values[op.ra] | op.si10;
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break;
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}
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case spu_itype::OR:
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{
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vflags[op.rt] = vflags[op.ra] & vflags[op.rb] & vf::is_const;
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values[op.rt] = values[op.ra] | values[op.rb];
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break;
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}
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case spu_itype::AI:
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{
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vflags[op.rt] = vflags[op.ra] & vf::is_const;
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values[op.rt] = values[op.ra] + op.si10;
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break;
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}
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case spu_itype::A:
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{
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vflags[op.rt] = vflags[op.ra] & vflags[op.rb] & vf::is_const;
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values[op.rt] = values[op.ra] + values[op.rb];
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break;
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}
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default:
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{
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// Unconst
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vflags[type & spu_itype::_quadrop ? +op.rt4 : +op.rt] = {};
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break;
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}
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}
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// Insert raw instruction value
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if (result.size() - 1 <= (pos - lsa) / 4)
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{
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if (result.size() - 1 < (pos - lsa) / 4)
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{
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result.resize((pos - lsa) / 4 + 1);
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}
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result.emplace_back(se_storage<u32>::swap(data));
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}
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else if (u32& raw_val = result[(pos - lsa) / 4 + 1])
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{
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verify(HERE), raw_val == se_storage<u32>::swap(data);
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}
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else
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{
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raw_val = se_storage<u32>::swap(data);
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}
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}
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if (g_cfg.core.spu_block_size == spu_block_size_type::safe)
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{
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// Check holes in safe mode (TODO)
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u32 valid_size = 0;
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for (u32 i = 1; i < result.size(); i++)
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{
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if (result[i] == 0)
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{
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const u32 pos = lsa + (i - 1) * 4;
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const u32 data = spu._ref<u32>(pos);
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const auto type = s_spu_itype.decode(data);
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// Allow only NOP or LNOP instructions in holes
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if (type == spu_itype::NOP || type == spu_itype::LNOP)
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{
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if (i + 1 < result.size())
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{
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continue;
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}
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}
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result.resize(valid_size + 1);
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break;
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}
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else
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{
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valid_size = i;
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}
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}
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}
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if (result.size() == 1)
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{
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// Blocks starting from 0x0 or invalid instruction won't be compiled, may need special interpreter fallback
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result.clear();
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}
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return result;
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}
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