Magn3s1um
63482dcfdc
-Fixed MPYU and special registers based on comments
2013-11-09 07:51:26 -08:00
Magn3s1um
1192d20295
-Partial Implementation of Floating-Point Status and Control Register (FPSCR)
2013-11-09 07:41:56 -08:00
Magn3s1um
3c762750a0
-Added SPR registers
...
-Implemented MTSPR
2013-11-08 17:17:44 -08:00
DH
0b35be32a4
- Implemented ARM9Thread.
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- Improved OpenGL Renderer.
- Improved RAW SPU mfc.
2013-11-03 21:23:16 +02:00
Alexandro Sánchez Bach
7d97bbfbbf
Changed syntax of last SPU instructions
2013-09-23 14:20:47 +02:00
Alexandro Sánchez Bach
03dcfeabc3
More SPU Instructions: Floating point comparison
...
* Implemented Floating/Double-floating comparison instructions:
FCGT, FCMGT, FCEQ, FCMEQ, DFCGT, DFCMGT, DFCEQ, DFCMEQ
* Implemented more Floating/Double-floating operations:
FMA, FMS, FNMS, DFMA, DFMS, DFNMS, DFNMA
* Implemented Double / Single floating-point conversion:
FESD, FRSD
2013-09-23 12:48:27 +02:00
Alexandro Sánchez Bach
db7e68d308
More SPU Instructions: Floating point arithmetic
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Implemented Floating/Double-floating arithmetic operations: Add,
Substract and Multiply: FA, FS, FM, DFA, DFS, DFM respectively.
* Fixed issue in the register editor: Wrong value displayed when reading
64 bit or 128 bit registers.
* Fixed issue in the register editor: Error when writing to 128 bit
registers.
2013-09-23 01:50:16 +02:00
DH
81e874c9e2
- Implemented HDD manager.
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- Implemented VFS manager.
- Implemented MFC.
- Fixed ELF Compiler.
- Improved HLE Func binder.
2013-08-03 12:40:03 +03:00
DH
559852a8fc
- Implemented RAW SPU.
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- Implemented memory mapping.
2013-07-12 15:42:17 +03:00
DH
6d7d3acb43
- Fixed loading modules in debug mode.
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- Improved Lwmutex.
- Implemented events syscalls.
- Fixed SPU local storage.
2013-07-06 02:49:38 +03:00
DH
991f281bbd
- Improved SPU Decoder.
2013-07-04 17:20:36 +03:00
DH
5753edf6ef
- Improved sc function binder.
...
- Improved GLGSRender.
2013-06-30 11:46:29 +03:00
DH
a90b5cf37a
http://code.google.com/p/rpcs3/source/detail?r=44
2012-11-15 01:39:56 +02:00
