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5 commits

Author SHA1 Message Date
Eladash 2bce367488 Fixup for fixup (#6153) 
* Fixup for fixup

* Fix memory ordering for MTRSX

volatile doesnt block reordering.

* ugh
 2019-06-30 12:47:42 +03:00
Eladash 43f919c04b Fixup after #6143 (#6146) 
vm::spu max address was overflowing resulting in issues, so cast to u64 where needed. Fixes #6145.
    Use vm::get_addr instead of manually substructing vm::base(0) from pointer in texture cache code.
    Prefer std::atomic_thread_fence over _mm_?fence(), adjust usage to be more correct.
    Used sequantially consistent ordering in semaphore_release for TSX path as well.
    Improved memory ordering for sys_rsx_context_iounmap/map.
    Fixed sync bugs in HLE gcm because of not using atomic instructions.
    Use release memory barrier in lwsync for PPU LLVM, according to this xbox360 programming guide lwsync is a hw release memory barrier.
    Also use release barrier where lwsync was originally used in liblv2 sys_lwmutex and cellSync.
    Use acquire barrier for isync instruction, see https://devblogs.microsoft.com/oldnewthing/20180814-00/?p=99485
 2019-06-29 18:48:42 +03:00
kd-11 4ff77a8555 rsx: Improve balancing of the offloader thread 
- Use two counters to avoid atomic operations
- Yield instead of sleeping because some games are very sensitive to timing
 2019-06-25 20:50:54 +03:00
kd-11 2b9c315374 rsx: Use rpcs3 thread construct for the offloader thread 2019-06-25 20:50:54 +03:00
kd-11 b893a75002 rsx: Rework RSX offloading 
- Use a lockless queue
- Do not enqueue small transfers
 2019-06-25 20:50:54 +03:00