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5656 commits

Author SHA1 Message Date
scribam
22f61caf9f GLTexture: add missing #pragma once directive 2019-05-12 18:32:11 +03:00
scribam
6c5ea068c9 Remove redundant semicolons 
Fix "-Wextra-semi" warnings
 2019-05-12 18:32:11 +03:00
Rui Pinheiro
1f82a26a9c SPU LLVM: Fix Mega 2019-05-12 00:39:42 +03:00
scribam
3623f4343f gl/vk: clear scissor_setup_invalid bit along with scissor_config_state_dirty bit 2019-05-11 13:13:49 +03:00
Nekotekina
8194c92f1c SPU LLVM: disable GHC CC for chunks on Windows 
Causes fatal error inside LLVM.
 2019-05-11 02:35:16 +03:00
Nekotekina
5d33d9a3d9 Enable most warnings in GCC 2019-05-11 02:13:19 +03:00
Nekotekina
7492f335e9 SPU analyser: basic function detection in Giga mode 
Misc: fix EH frame registration (LLVM, non-Windows).
Misc: constant-folding bitcast (cpu_translator).
Misc: add syntax for LLVM arrays (cpu_translator).
Misc: use function names for proper linkage (SPU LLVM).

Changed function search and verification in Giga mode.
Basic stack frame layout analysis.
Function detection in Giga mode.
Basic use of new information in SPU LLVM.
Fixed jump table compilation in SPU LLVM.
Disable broken optimization in Accurate xfloat mode.
Make compiled SPU modules position-independent in SPU LLVM.

Optimizations include but not limited to:
 * Compiling SPU functions as native functions when eligible
 * Avoiding register context write-out
 * Aligned stack assumption (CWD alike instruction)
 2019-05-11 02:13:19 +03:00
Megamouse
fce9d6a7b8 Qt/input: add LED color picker to pad settings dialog 2019-05-09 22:02:00 +02:00
eladash
7ead021aa7 rsx: Fix 3d swizzled texture to linear conversation 2019-05-08 23:48:39 +03:00
eladash
13d8e33d9a Return ESRCH if ppu thread ID was not found in sys_cond_signal_to 2019-05-07 08:58:07 +03:00
eladash
4e2650af91 Fix sys_rwlock_wlock timedout event 
If the rwlock is currently acquired by a writer signaling readers is wrong and will lead to EPERM for wunlock!
Only signal blocked readers if the rwlock is currently acquired by readers
 2019-05-07 08:58:07 +03:00
eladash
ca08418dc1 Fix sys_rwlock_runlock on waiting readers 
readers can wait on the sleep queue if a writer lock has been blocked before it, in this case after runlock: writer should acquire the lock but the r's sleep queue is still not empty!
 2019-05-07 08:58:07 +03:00
Megamouse
5141590729 overlays: add separate timestamp for the start of the d-pad interval 2019-05-06 22:00:40 +02:00
Malcolm Jestadt
fd2bc95a7b overlays: Double dpad repeat rate 2019-05-06 22:00:40 +02:00
Megamouse
c1e245ae73 Emu: msg_dialog_frame fixup: don't reject on Close to prevent Emu.Stop() 2019-05-05 16:29:50 +02:00
Megamouse
b639584acc Emu/Qt: Fix Boot Recent when using BootGame(add_only=true) 2019-05-05 16:29:50 +02:00
Megamouse
b0a24665e5 Emu: msg_dialog_frame fixes 2019-05-05 16:29:50 +02:00
kd-11
9c346c92f3 gl: undo an accidental deletion 2019-05-05 13:37:55 +03:00
kd-11
2bec304cca vk: Allow some drivers to bypass window polling if not needed 2019-05-05 13:37:55 +03:00
Nekotekina
a703460fc6 SPU ASMJIT: skip some unused analyser steps 
May improve performance
 2019-05-04 19:35:13 +03:00
Nekotekina
ba1ec1d5d6 SPU analyser: remove use_ra from HBR 
Since this is a hint instruction, we don't really use reg value here.
 2019-05-04 18:33:58 +03:00
Nekotekina
45ce8db6cb SPU Analyser: fix reg origin regression 
Propagate phi instead of claiming new values
 2019-05-04 18:29:47 +03:00
Nekotekina
4bd022f778 SPU analyser: minor logic fix and cleanup 
Don't fill any chunk info for now (design mistake).
 2019-05-03 14:18:22 +03:00
Nekotekina
6c34d7104e SPU analyser: fix excessive workload list size 
Typo grade; regression
 2019-05-02 23:29:02 +03:00
Nekotekina
54dc617f39 SPU analyser: internal spu_itype optimization 
Use only 1 byte for instruction type.
Flags are transformed into range comparisons.
 2019-05-02 19:32:09 +03:00
Nekotekina
15bd3b8724 SPU: fix minor UB in STQD/LQD instructions 2019-05-02 18:00:49 +03:00
Nekotekina
2b4da18709 SPU LLVM: fix xfloat regression 
It was an old bug with possible hidden use of deleted instructions.
 2019-05-02 13:39:43 +03:00
Nekotekina
d48dc29e55 SPU LLVM: fix perf regression 
Bug in the analyser was created recently in #5882.
 2019-05-02 13:39:43 +03:00
Nekotekina
69d2ea35b9 SPU: minor analyser cleanup 2019-05-02 13:39:43 +03:00
Nekotekina
a4c4ee9cb2 SPU: fix excessive cache size regression 2019-05-02 13:39:43 +03:00
kd-11
6b7cd458e3 rsx: Silence some diagnostics unless compiled with debugging options 2019-05-01 15:36:21 +03:00
kd-11
1d5c52f476 rsx: Ignore stencil clear flag if the stencil write mask is disabled 2019-05-01 15:36:21 +03:00
kd-11
48cb265c2c rsx: Bounds check on local resource for atlas merge. 
- Local resources can also have padded pitch dimensions and false-positives on range overlap tests
 2019-05-01 15:36:21 +03:00
kd-11
63f9b8e0c6 gl/vk: Minor cleanup 2019-05-01 15:36:21 +03:00
kd-11
ec9aa74008 rsx: Fix section base offset calculation for blit_dst targets which affects confirmed memory range 
- Fixes flushes only writing partially to target memory
 2019-05-01 15:36:21 +03:00
kd-11
4e3ec162e2 rsx: Fix broken texture cache search when flipping 2019-05-01 15:36:21 +03:00
kd-11
6feffe6ff6 rsx: Ignore transfer offsets when wrapping behaviour is expected 2019-05-01 15:36:21 +03:00
kd-11
f56a6548b0 gl: Remove workaround for AMD driver bug fixed in driver 19.4.3 2019-05-01 15:36:21 +03:00
Nekotekina
1bc5e27507 SPU LLVM: move reg origin search to analyser 
Refactor SPU analyser (block_info struct).
Fill register use info (currently unused).
 2019-05-01 00:37:15 +03:00
Nekotekina
1294e0d189 SPU LLVM: improve codegen in loops 
Use a trick in check_state to improve LICM pass.
 2019-05-01 00:37:15 +03:00
Nekotekina
e09c6ea4b4 SPU analyser: add spu_iflag 
Register information about register accesses.
 2019-04-30 14:33:27 +03:00
Nekotekina
716737ecf2 LLVM DSL: expression matching (alpha) 
Implement remaining instructions.
Implement match_expr method.
Implement helper methods.
 2019-04-30 14:33:27 +03:00
eladash
3bd29b8bac Fix Unregistered HLE function access 2019-04-29 23:04:16 +03:00
eladash
ea1c9a2e17 Fix PPU Breakpoints and ppu_check_toc 2019-04-29 23:04:16 +03:00
kd-11
243df38360 rsx: Fix VP writes to CC with a MOV instruction 
- When moving to CC, the operation has VEC flag disabled and also temp
regs disabled. Looks to be the catch-all ELSE in the selection logic.
 2019-04-25 16:23:05 +03:00
kd-11
3cbccdd760 rsx: Fragment shader decompiler cleanup 
TODO: Investigate the _s input modifier behaviour further, in case it can avoid generating zeroes from a MAD instruction.
x = MAD(+ve, -ve, -ve) with _s input modifier in BFBC expects result to be Non-zero
 2019-04-25 16:23:05 +03:00
kd-11
4cd1c25729 "rsx: Ignore argument sign for SQRT operations" 2019-04-25 16:23:05 +03:00
kd-11
32396ba366 rsx: Simplify use of some mixed input functions using OPFLAGS to avoid implicit conversions 2019-04-25 16:23:05 +03:00
kd-11
f12bd8068c rsx: Fragment decompiler fixups 
- Properly test for NaN and Inf when clamping down to fp16
- Optimize divsq a bit; mix(vec, vec, bvec) emits OpSelect which is what
we want here, instead of component-wise selection which is much slower.
 2019-04-25 16:23:05 +03:00
kd-11
abe7188acf rsx: Proper workaround for broken DIVSQ instruction on realhw 
- While mul(0, nan) = nan and 0 / 0 = nan, 0 / sqrt(0) = 0 because of hw
gremlins. normalize(0) is also nan so this behaviour does not work
around that particular case either which makes it even more baffling.
 2019-04-25 16:23:05 +03:00