mirror of
https://github.com/RPCSX/rpcsx.git
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TTY output improved; ARMv7: new instructions
ADC_REG, MVN_REG, ORR_REG, ROR_IMM, ROR_REG, TST_IMM, armv7_fmt improved
This commit is contained in:
Nekotekina
parent
d5bbea097b
commit
e3f55a75a3
7 changed files with 426 additions and 76 deletions
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@ -30,137 +30,147 @@ struct ARMv7_opcode_t
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const ARMv7_opcode_t ARMv7_opcode_table[] =
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{
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ARMv7_OP4(0xffff, 0x0000, 0xf870, 0x0000, T1, HACK), // "Undefined" Thumb opcode used
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ARMv7_OP4(0xffff, 0x0000, 0xf870, 0x0000, T1, HACK, nullptr), // "Undefined" Thumb opcode used
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ARMv7_OP4(0x0ff0, 0x00f0, 0x0070, 0x0090, A1, HACK), // "Undefined" ARM opcode used
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ARMv7_OP4(0xfbe0, 0x8000, 0xf140, 0x0000, T1, ADC_IMM),
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ARMv7_OP4(0xfbe0, 0x8000, 0xf140, 0x0000, T1, ADC_IMM, nullptr),
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ARMv7_OP4(0x0fe0, 0x0000, 0x02a0, 0x0000, A1, ADC_IMM),
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ARMv7_OP2(0xffc0, 0x4040, T1, ADC_REG),
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ARMv7_OP4(0xffe0, 0x8000, 0xeb40, 0x0000, T2, ADC_REG),
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ARMv7_OP2(0xffc0, 0x4040, T1, ADC_REG, nullptr),
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ARMv7_OP4(0xffe0, 0x8000, 0xeb40, 0x0000, T2, ADC_REG, nullptr),
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ARMv7_OP4(0x0fe0, 0x0010, 0x00a0, 0x0000, A1, ADC_REG),
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ARMv7_OP4(0x0fe0, 0x0090, 0x00a0, 0x0010, A1, ADC_RSR),
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ARMv7_OP2(0xfe00, 0x1c00, T1, ADD_IMM),
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ARMv7_OP2(0xf800, 0x3000, T2, ADD_IMM),
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ARMv7_OP2(0xfe00, 0x1c00, T1, ADD_IMM, nullptr),
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ARMv7_OP2(0xf800, 0x3000, T2, ADD_IMM, nullptr),
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ARMv7_OP4(0xfbe0, 0x8000, 0xf100, 0x0000, T3, ADD_IMM, SKIP_IF( (BF(8, 11) == 15 && BT(20)) || BF(16, 19) == 13 )),
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ARMv7_OP4(0xfbf0, 0x8000, 0xf200, 0x0000, T4, ADD_IMM, SKIP_IF( (BF(16, 19) & 13) == 13 )),
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ARMv7_OP4(0x0fe0, 0x0000, 0x0280, 0x0000, A1, ADD_IMM),
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ARMv7_OP2(0xfe00, 0x1800, T1, ADD_REG),
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ARMv7_OP2(0xfe00, 0x1800, T1, ADD_REG, nullptr),
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ARMv7_OP2(0xff00, 0x4400, T2, ADD_REG, SKIP_IF( (c & 0x87) == 0x85 || BF(3, 6) == 13 )),
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ARMv7_OP4(0xffe0, 0x8000, 0xeb00, 0x0000, T3, ADD_REG, SKIP_IF( (BF(8, 11) == 15 && BT(20)) || BF(16, 19) == 13 )),
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ARMv7_OP4(0x0fe0, 0x0010, 0x0080, 0x0000, A1, ADD_REG),
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ARMv7_OP4(0x0fe0, 0x0090, 0x0080, 0x0010, A1, ADD_RSR),
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ARMv7_OP2(0xf800, 0xa800, T1, ADD_SPI),
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ARMv7_OP2(0xff80, 0xb000, T2, ADD_SPI),
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ARMv7_OP2(0xf800, 0xa800, T1, ADD_SPI, nullptr),
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ARMv7_OP2(0xff80, 0xb000, T2, ADD_SPI, nullptr),
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ARMv7_OP4(0xfbef, 0x8000, 0xf10d, 0x0000, T3, ADD_SPI, SKIP_IF( BF(8, 11) == 15 && BT(20) )),
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ARMv7_OP4(0xfbff, 0x8000, 0xf20d, 0x0000, T4, ADD_SPI),
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ARMv7_OP4(0xfbff, 0x8000, 0xf20d, 0x0000, T4, ADD_SPI, nullptr),
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ARMv7_OP4(0x0fef, 0x0000, 0x028d, 0x0000, A1, ADD_SPI),
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ARMv7_OP2(0xff78, 0x4468, T1, ADD_SPR),
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ARMv7_OP2(0xff78, 0x4468, T1, ADD_SPR, nullptr),
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ARMv7_OP2(0xff87, 0x4485, T2, ADD_SPR, SKIP_IF( BF(3, 6) == 13 )),
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ARMv7_OP4(0xffef, 0x8000, 0xeb0d, 0x0000, T3, ADD_SPR),
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ARMv7_OP4(0xffef, 0x8000, 0xeb0d, 0x0000, T3, ADD_SPR, nullptr),
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ARMv7_OP4(0x0fef, 0x0010, 0x008d, 0x0000, A1, ADD_SPR),
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ARMv7_OP2(0xf800, 0xa000, T1, ADR),
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ARMv7_OP4(0xfbff, 0x8000, 0xf2af, 0x0000, T2, ADR),
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ARMv7_OP4(0xfbff, 0x8000, 0xf20f, 0x0000, T3, ADR),
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ARMv7_OP2(0xf800, 0xa000, T1, ADR, nullptr),
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ARMv7_OP4(0xfbff, 0x8000, 0xf2af, 0x0000, T2, ADR, nullptr),
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ARMv7_OP4(0xfbff, 0x8000, 0xf20f, 0x0000, T3, ADR, nullptr),
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ARMv7_OP4(0x0fff, 0x0000, 0x028f, 0x0000, A1, ADR),
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ARMv7_OP4(0x0fff, 0x0000, 0x024f, 0x0000, A2, ADR),
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ARMv7_OP4(0xfbe0, 0x8000, 0xf000, 0x0000, T1, AND_IMM),
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ARMv7_OP4(0xfbe0, 0x8000, 0xf000, 0x0000, T1, AND_IMM, SKIP_IF( BF(8, 11) == 15 && BT(20) )),
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ARMv7_OP4(0x0fe0, 0x0000, 0x0200, 0x0000, A1, AND_IMM),
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ARMv7_OP2(0xffc0, 0x4000, T1, AND_REG),
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ARMv7_OP4(0xffe0, 0x8000, 0xea00, 0x0000, T2, AND_REG),
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ARMv7_OP2(0xffc0, 0x4000, T1, AND_REG, nullptr),
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ARMv7_OP4(0xffe0, 0x8000, 0xea00, 0x0000, T2, AND_REG, SKIP_IF( BF(8, 11) == 15 && BT(20) )),
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ARMv7_OP4(0x0fe0, 0x0010, 0x0000, 0x0000, A1, AND_REG),
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ARMv7_OP4(0x0fe0, 0x0090, 0x0000, 0x0010, A1, AND_RSR),
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ARMv7_OP2(0xf800, 0x1000, T1, ASR_IMM),
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ARMv7_OP4(0xffef, 0x8030, 0xea4f, 0x0020, T2, ASR_IMM),
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ARMv7_OP2(0xf800, 0x1000, T1, ASR_IMM, nullptr),
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ARMv7_OP4(0xffef, 0x8030, 0xea4f, 0x0020, T2, ASR_IMM, nullptr),
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ARMv7_OP4(0x0fef, 0x0070, 0x01a0, 0x0040, A1, ASR_IMM),
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ARMv7_OP2(0xffc0, 0x4100, T1, ASR_REG),
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ARMv7_OP4(0xffe0, 0xf0f0, 0xfa40, 0xf000, T2, ASR_REG),
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ARMv7_OP2(0xffc0, 0x4100, T1, ASR_REG, nullptr),
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ARMv7_OP4(0xffe0, 0xf0f0, 0xfa40, 0xf000, T2, ASR_REG, nullptr),
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ARMv7_OP4(0x0fef, 0x00f0, 0x01a0, 0x0050, A1, ASR_REG),
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ARMv7_OP2(0xf000, 0xd000, T1, B),
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ARMv7_OP2(0xf800, 0xe000, T2, B),
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ARMv7_OP4(0xf800, 0xd000, 0xf000, 0x8000, T3, B),
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ARMv7_OP4(0xf800, 0xd000, 0xf000, 0x9000, T4, B),
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ARMv7_OP2(0xf000, 0xd000, T1, B, SKIP_IF( BF(9, 11) == 0x7 )),
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ARMv7_OP2(0xf800, 0xe000, T2, B, nullptr),
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ARMv7_OP4(0xf800, 0xd000, 0xf000, 0x8000, T3, B, SKIP_IF( BF(23, 25) == 0x7 )),
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ARMv7_OP4(0xf800, 0xd000, 0xf000, 0x9000, T4, B, nullptr),
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ARMv7_OP4(0x0f00, 0x0000, 0x0a00, 0x0000, A1, B),
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ARMv7_OP4(0xffff, 0x8020, 0xf36f, 0x0000, T1, BFC),
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ARMv7_OP4(0xffff, 0x8020, 0xf36f, 0x0000, T1, BFC, nullptr),
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ARMv7_OP4(0x0fe0, 0x007f, 0x07c0, 0x001f, A1, BFC),
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ARMv7_OP4(0xfff0, 0x8020, 0xf360, 0x0000, T1, BFI),
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ARMv7_OP4(0xfff0, 0x8020, 0xf360, 0x0000, T1, BFI, SKIP_IF( BF(16, 19) == 15 )),
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ARMv7_OP4(0x0fe0, 0x0070, 0x07c0, 0x0010, A1, BFI),
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ARMv7_OP4(0xfbe0, 0x8000, 0xf020, 0x0000, T1, BIC_IMM),
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ARMv7_OP4(0xfbe0, 0x8000, 0xf020, 0x0000, T1, BIC_IMM, nullptr),
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ARMv7_OP4(0x0fe0, 0x0000, 0x03c0, 0x0000, A1, BIC_IMM),
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ARMv7_OP2(0xffc0, 0x4380, T1, BIC_REG),
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ARMv7_OP4(0xffe0, 0x8000, 0xea20, 0x0000, T2, BIC_REG),
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ARMv7_OP2(0xffc0, 0x4380, T1, BIC_REG, nullptr),
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ARMv7_OP4(0xffe0, 0x8000, 0xea20, 0x0000, T2, BIC_REG, nullptr),
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ARMv7_OP4(0x0fe0, 0x0010, 0x01c0, 0x0000, A1, BIC_REG),
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ARMv7_OP4(0x0fe0, 0x0090, 0x01c0, 0x0010, A1, BIC_RSR),
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ARMv7_OP2(0xff00, 0xbe00, T1, BKPT),
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ARMv7_OP2(0xff00, 0xbe00, T1, BKPT, nullptr),
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ARMv7_OP4(0x0ff0, 0x00f0, 0x0120, 0x0070, A1, BKPT),
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ARMv7_OP4(0xf800, 0xd000, 0xf000, 0xd000, T1, BL),
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ARMv7_OP4(0xf800, 0xd000, 0xf000, 0xd000, T1, BL, nullptr),
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ARMv7_OP4(0x0f00, 0x0000, 0x0b00, 0x0000, A1, BL),
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ARMv7_OP2(0xff80, 0x4780, T1, BLX),
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ARMv7_OP4(0xf800, 0xc001, 0xf000, 0xc000, T2, BLX),
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ARMv7_OP2(0xff80, 0x4780, T1, BLX, nullptr),
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ARMv7_OP4(0xf800, 0xc001, 0xf000, 0xc000, T2, BLX, nullptr),
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ARMv7_OP4(0x0fff, 0xfff0, 0x012f, 0xff30, A1, BLX),
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ARMv7_OP4(0xfe00, 0x0000, 0xfa00, 0x0000, A2, BLX),
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ARMv7_OP2(0xff87, 0x4700, T1, BX),
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ARMv7_OP2(0xff87, 0x4700, T1, BX, nullptr),
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ARMv7_OP4(0x0fff, 0xfff0, 0x012f, 0xff10, A1, BX),
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ARMv7_OP2(0xf500, 0xb100, T1, CB_Z),
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ARMv7_OP2(0xf500, 0xb100, T1, CB_Z, nullptr),
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ARMv7_OP4(0xfff0, 0xf0f0, 0xfab0, 0xf080, T1, CLZ),
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ARMv7_OP4(0xfff0, 0xf0f0, 0xfab0, 0xf080, T1, CLZ, nullptr),
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ARMv7_OP4(0x0fff, 0x0ff0, 0x016f, 0x0f10, A1, CLZ),
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ARMv7_OP4(0xfbf0, 0x8f00, 0xf110, 0x0f00, T1, CMN_IMM),
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ARMv7_OP4(0xfbf0, 0x8f00, 0xf110, 0x0f00, T1, CMN_IMM, nullptr),
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ARMv7_OP4(0x0ff0, 0xf000, 0x0370, 0x0000, A1, CMN_IMM),
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ARMv7_OP2(0xffc0, 0x42c0, T1, CMN_REG),
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ARMv7_OP4(0xfff0, 0x8f00, 0xeb10, 0x0f00, T2, CMN_REG),
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ARMv7_OP2(0xffc0, 0x42c0, T1, CMN_REG, nullptr),
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ARMv7_OP4(0xfff0, 0x8f00, 0xeb10, 0x0f00, T2, CMN_REG, nullptr),
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ARMv7_OP4(0x0ff0, 0xf010, 0x0170, 0x0000, A1, CMN_REG),
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ARMv7_OP4(0x0ff0, 0xf090, 0x0170, 0x0010, A1, CMN_RSR),
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ARMv7_OP2(0xf800, 0x2800, T1, CMP_IMM),
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ARMv7_OP4(0xfbf0, 0x8f00, 0xf1b0, 0x0f00, T2, CMP_IMM),
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ARMv7_OP2(0xf800, 0x2800, T1, CMP_IMM, nullptr),
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ARMv7_OP4(0xfbf0, 0x8f00, 0xf1b0, 0x0f00, T2, CMP_IMM, nullptr),
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ARMv7_OP4(0x0ff0, 0xf000, 0x0350, 0x0000, A1, CMP_IMM),
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ARMv7_OP2(0xffc0, 0x4280, T1, CMP_REG),
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ARMv7_OP2(0xff00, 0x4500, T2, CMP_REG),
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ARMv7_OP4(0xfff0, 0x8f00, 0xebb0, 0x0f00, T3, CMP_REG),
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ARMv7_OP2(0xffc0, 0x4280, T1, CMP_REG, nullptr),
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ARMv7_OP2(0xff00, 0x4500, T2, CMP_REG, nullptr),
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ARMv7_OP4(0xfff0, 0x8f00, 0xebb0, 0x0f00, T3, CMP_REG, nullptr),
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ARMv7_OP4(0x0ff0, 0xf010, 0x0150, 0x0000, A1, CMP_REG),
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ARMv7_OP4(0x0ff0, 0xf090, 0x0150, 0x0010, A1, CMP_RSR),
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ARMv7_OP4(0xfbe0, 0x8000, 0xf080, 0x0000, T1, EOR_IMM),
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ARMv7_OP4(0xffff, 0xfff0, 0xf3af, 0x80f0, T1, DBG, nullptr),
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ARMv7_OP4(0x0fff, 0xfff0, 0x0320, 0xf0f0, A1, DBG),
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ARMv7_OP4(0xffff, 0xfff0, 0xf3bf, 0x8f50, T1, DMB, nullptr),
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ARMv7_OP4(0xffff, 0xfff0, 0xf57f, 0xf050, A1, DMB),
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ARMv7_OP4(0xffff, 0xfff0, 0xf3bf, 0x8f40, T1, DSB, nullptr),
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ARMv7_OP4(0xffff, 0xfff0, 0xf57f, 0xf040, A1, DSB),
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ARMv7_OP4(0xfbe0, 0x8000, 0xf080, 0x0000, T1, EOR_IMM, SKIP_IF( BF(8, 11) == 15 && BT(20) )),
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ARMv7_OP4(0x0fe0, 0x0000, 0x0220, 0x0000, A1, EOR_IMM),
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ARMv7_OP2(0xffc0, 0x4040, T1, EOR_REG),
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ARMv7_OP4(0xffe0, 0x8000, 0xea80, 0x0000, T2, EOR_REG),
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ARMv7_OP2(0xffc0, 0x4040, T1, EOR_REG, nullptr),
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ARMv7_OP4(0xffe0, 0x8000, 0xea80, 0x0000, T2, EOR_REG, SKIP_IF( BF(8, 11) == 15 && BT(20) )),
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ARMv7_OP4(0x0fe0, 0x0010, 0x0020, 0x0000, A1, EOR_REG),
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ARMv7_OP4(0x0fe0, 0x0090, 0x0020, 0x0010, A1, EOR_RSR),
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ARMv7_OP2(0xff00, 0xbf00, T1, IT, SKIP_IF( BF(0, 3) == 0 )),
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ARMv7_OP2(0xf800, 0xc800, T1, LDM),
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ARMv7_OP4(0xffd0, 0x2000, 0xe890, 0x0000, T2, LDM),
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ARMv7_OP2(0xf800, 0xc800, T1, LDM, nullptr),
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ARMv7_OP4(0xffd0, 0x2000, 0xe890, 0x0000, T2, LDM, SKIP_IF( BT(21) && BF(16, 19) == 13 )),
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ARMv7_OP4(0x0fd0, 0x0000, 0x0890, 0x0000, A1, LDM),
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ARMv7_OP4(0x0fd0, 0x0000, 0x0810, 0x0000, A1, LDMDA),
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ARMv7_OP4(0xffd0, 0x2000, 0xe910, 0x0000, T1, LDMDB),
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ARMv7_OP4(0xffd0, 0x2000, 0xe910, 0x0000, T1, LDMDB, nullptr),
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ARMv7_OP4(0x0fd0, 0x0000, 0x0910, 0x0000, A1, LDMDB),
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ARMv7_OP4(0x0fd0, 0x0000, 0x0990, 0x0000, A1, LDMIB),
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ARMv7_OP2(0xf800, 0x6800, T1, LDR_IMM),
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ARMv7_OP2(0xf800, 0x9800, T2, LDR_IMM),
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ARMv7_OP2(0xf800, 0x6800, T1, LDR_IMM, nullptr),
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ARMv7_OP2(0xf800, 0x9800, T2, LDR_IMM, nullptr),
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ARMv7_OP4(0xfff0, 0x0000, 0xf8d0, 0x0000, T3, LDR_IMM, SKIP_IF( BF(16, 19) == 15 )),
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ARMv7_OP4(0xfff0, 0x0800, 0xf850, 0x0800, T4, LDR_IMM, SKIP_IF( BF(16, 19) == 15 || BF(8, 10) == 6 || (c & 0xf07ff) == 0xd0304 || (c & 0x500) == 0 )),
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ARMv7_OP4(0x0e50, 0x0000, 0x0410, 0x0000, A1, LDR_IMM),
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ARMv7_OP2(0xf800, 0x4800, T1, LDR_LIT),
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ARMv7_OP4(0xff7f, 0x0000, 0xf85f, 0x0000, T2, LDR_LIT),
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ARMv7_OP2(0xf800, 0x4800, T1, LDR_LIT, nullptr),
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ARMv7_OP4(0xff7f, 0x0000, 0xf85f, 0x0000, T2, LDR_LIT, nullptr),
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ARMv7_OP4(0x0f7f, 0x0000, 0x051f, 0x0000, A1, LDR_LIT),
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ARMv7_OP2(0xfe00, 0x5800, T1, LDR_REG),
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ARMv7_OP4(0xfff0, 0x0fc0, 0xf850, 0x0000, T2, LDR_REG),
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ARMv7_OP2(0xfe00, 0x5800, T1, LDR_REG, nullptr),
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ARMv7_OP4(0xfff0, 0x0fc0, 0xf850, 0x0000, T2, LDR_REG, SKIP_IF( BF(16, 19) == 15 )),
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ARMv7_OP4(0x0e50, 0x0010, 0x0610, 0x0000, A1, LDR_REG),
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ARMv7_OP2(0xf800, 0x7800, T1, LDRB_IMM),
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ARMv7_OP4(0xfff0, 0x0000, 0xf890, 0x0000, T2, LDRB_IMM),
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ARMv7_OP4(0xfff0, 0x0800, 0xf810, 0x0800, T3, LDRB_IMM),
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@ -280,7 +290,7 @@ const ARMv7_opcode_t ARMv7_opcode_table[] =
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ARMv7_OP4(0xfbe0, 0x8000, 0xf040, 0x0000, T1, ORR_IMM),
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ARMv7_OP4(0x0fe0, 0x0000, 0x0380, 0x0000, A1, ORR_IMM),
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ARMv7_OP2(0xffc0, 0x4300, T1, ORR_REG),
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ARMv7_OP4(0xffe0, 0x8000, 0xea40, 0x0000, T2, ORR_REG),
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ARMv7_OP4(0xffe0, 0x8000, 0xea40, 0x0000, T2, ORR_REG, SKIP_IF( BF(16, 19) == 15 )),
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ARMv7_OP4(0x0fe0, 0x0010, 0x0180, 0x0000, A1, ORR_REG),
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ARMv7_OP4(0x0fe0, 0x0090, 0x0180, 0x0010, A1, ORR_RSR),
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Reference in a new issue