ppu interpreter: Improve FPCC field handling

rpcs3/Emu/Cell/PPUThread.h

@@ -1,4 +1,4 @@
-#pragma once
+#pragma once
 
 #include "Common.h"
 #include "../CPU/CPUThread.h"
@@ -59,48 +59,65 @@ public:
 	f64 fpr[32] = {}; // Floating Point Registers
 	v128 vr[32] = {}; // Vector Registers
 
-	alignas(16) bool cr[32] = {}; // Condition Registers (unpacked)
-
-	alignas(16) struct // Floating-Point Status and Control Register (unpacked)
+	struct cr_bits
 	{
-		// TODO
-		bool _start[16]{};
-		bool fl{}; // FPCC.FL
-		bool fg{}; // FPCC.FG
-		bool fe{}; // FPCC.FE
-		bool fu{}; // FPCC.FU
-		bool _end[12]{};
+		alignas(16) u8 bits[32];
+
+		u8& operator [](std::size_t i)
+		{
+			return bits[i];
+		}
+
+		// Pack CR bits
+		u32 pack() const
+		{
+			u32 result{};
+
+			for (u32 bit : bits)
+			{
+				result <<= 1;
+				result |= bit;
+			}
+
+			return result;	
+		}
+
+		// Unpack CR bits
+		void unpack(u32 value)
+		{
+			for (u8& b : bits)
+			{
+				b = value & 0x1;
+				value >>= 1;
+			}
+		}
+	};
+
+	cr_bits cr{}; // Condition Registers (unpacked)
+
+	// Floating-Point Status and Control Register (unpacked)
+	union
+	{
+		struct
+		{
+			// TODO
+			bool _start[16];
+			bool fl; // FPCC.FL
+			bool fg; // FPCC.FG
+			bool fe; // FPCC.FE
+			bool fu; // FPCC.FU
+			bool _end[12];
+		};
+
+		cr_bits bits;
 	}
-	fpscr;
+	fpscr{};
 
 	u64 lr{}; // Link Register
 	u64 ctr{}; // Counter Register
 	u32 vrsave{0xffffffff}; // VR Save Register
 	u32 cia{}; // Current Instruction Address
 
-	// Pack CR bits
-	u32 cr_pack() const
-	{
-		u32 result{};
-
-		for (u32 bit : cr)
-		{
-			result = (result << 1) | bit;
-		}
-
-		return result;
-	}
-
-	// Unpack CR bits
-	void cr_unpack(u32 value)
-	{
-		for (bool& b : cr)
-		{
-			b = (value & 0x1) != 0;
-			value >>= 1;
-		}
-	}
-
 	// Fixed-Point Exception Register (abstract representation)
 	struct
 	{