mirror of
https://github.com/RPCSX/rpcsx.git
synced 2025-12-06 07:12:14 +01:00
gpu: fixed command ring corruption in release build
add IT_DMA_DATA for compute pipe implement 3 indirection gfx ring commands
This commit is contained in:
DH
parent
2f1c8e9a91
commit
b85c6e6acc
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@ -532,7 +532,8 @@ void Device::submitCommand(Ring &ring, std::span<const std::uint32_t> command) {
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ring.wptr = ring.base;
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}
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std::memcpy(ring.wptr, command.data(), command.size_bytes());
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std::memcpy(const_cast<std::uint32_t *>(ring.wptr), command.data(),
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command.size_bytes());
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ring.wptr += command.size();
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}
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@ -594,6 +595,10 @@ void Device::unmapProcess(std::uint32_t pid) {
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auto &process = processInfo[pid];
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auto startAddress = static_cast<std::uint64_t>(process.vmId) << 40;
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auto size = static_cast<std::uint64_t>(1) << 40;
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startAddress += orbis::kMinAddress;
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size -= orbis::kMinAddress;
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rx::mem::reserve(reinterpret_cast<void *>(startAddress), size);
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::close(process.vmFd);
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@ -607,7 +612,7 @@ void Device::protectMemory(std::uint32_t pid, std::uint64_t address,
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auto vmSlotIt = process.vmTable.queryArea(address);
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if (vmSlotIt == process.vmTable.end()) {
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std::abort();
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return;
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}
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auto vmSlot = (*vmSlotIt).payload;
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@ -1027,7 +1032,9 @@ static void notifyPageChanges(Device *device, int vmId, std::uint32_t firstPage,
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1, std::memory_order::release);
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device->cpuCacheCommandsIdle[vmId].notify_one();
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while (device->cpuCacheCommands[vmId][i].load(std::memory_order::acquire) != 0) {}
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while (device->cpuCacheCommands[vmId][i].load(
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std::memory_order::acquire) != 0) {
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}
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return;
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}
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}
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@ -97,6 +97,7 @@ ComputePipe::ComputePipe(int index)
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commandHandlers[gnm::IT_WRITE_DATA] = &ComputePipe::writeData;
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commandHandlers[gnm::IT_INDIRECT_BUFFER] = &ComputePipe::indirectBuffer;
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commandHandlers[gnm::IT_ACQUIRE_MEM] = &ComputePipe::acquireMem;
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commandHandlers[gnm::IT_DMA_DATA] = &ComputePipe::dmaData;
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}
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bool ComputePipe::processAllRings() {
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@ -186,8 +187,8 @@ void ComputePipe::setIndirectRing(int queueId, int indirectLevel, Ring ring) {
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}
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ring.indirectLevel = indirectLevel;
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std::println("mapQueue: {}, {}, {}", (void *)ring.base, (void *)ring.wptr,
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ring.size);
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std::println(stderr, "mapQueue: {}, {}, {}", (void *)ring.base,
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(void *)ring.wptr, ring.size);
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queues[1 - ring.indirectLevel][queueId] = ring;
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}
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@ -202,8 +203,8 @@ void ComputePipe::mapQueue(int queueId, Ring ring,
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waitForIdle(queueId, lock);
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}
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std::println("mapQueue: {}, {}, {}, {}", (void *)ring.base, (void *)ring.wptr,
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ring.size, (void *)ring.doorbell);
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std::println(stderr, "mapQueue: {}, {}, {}, {}", (void *)ring.base,
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(void *)ring.wptr, ring.size, (void *)ring.doorbell);
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queues[1 - ring.indirectLevel][queueId] = ring;
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}
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@ -260,7 +261,7 @@ bool ComputePipe::setShReg(Ring &ring) {
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data[i]);
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}
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std::memcpy(ring.doorbell + offset, data, sizeof(std::uint32_t) * len);
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std::memcpy(ring.doorbell + offset, const_cast<const uint32_t *>(data), sizeof(std::uint32_t) * len);
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return true;
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}
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@ -404,7 +405,7 @@ bool ComputePipe::writeData(Ring &ring) {
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*dstPointer = data[i];
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}
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} else {
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std::memcpy(dstPointer, data, len * sizeof(std::uint32_t));
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std::memcpy(dstPointer, const_cast<const uint32_t *>(data), len * sizeof(std::uint32_t));
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}
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return true;
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@ -430,6 +431,138 @@ bool ComputePipe::indirectBuffer(Ring &ring) {
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bool ComputePipe::acquireMem(Ring &ring) { return true; }
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bool ComputePipe::dmaData(Ring &ring) {
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auto control = ring.rptr[1];
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auto srcAddressLo = ring.rptr[2];
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auto data = srcAddressLo;
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auto srcAddressHi = ring.rptr[3];
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auto dstAddressLo = ring.rptr[4];
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auto dstAddressHi = ring.rptr[5];
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auto cmdSize = ring.rptr[6];
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auto size = rx::getBits(cmdSize, 20, 0);
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auto engine = rx::getBit(control, 0);
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auto srcVolatile = rx::getBit(control, 15);
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// 0 - dstAddress using das
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// 1 - gds
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// 3 - dstAddress using L2
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auto dstSel = rx::getBits(control, 21, 20);
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// 0 - LRU
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// 1 - Stream
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// 2 - Bypass
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auto dstCachePolicy = rx::getBits(control, 26, 25);
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auto dstVolatile = rx::getBit(control, 27);
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// 0 - srcAddress using sas
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// 1 - gds
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// 2 - data
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// 3 - srcAddress using L2
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auto srcSel = rx::getBits(control, 30, 29);
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auto cpSync = rx::getBit(control, 31);
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auto dataDisWc = rx::getBit(cmdSize, 21);
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// 0 - none
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// 1 - 8 in 16
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// 2 - 8 in 32
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// 3 - 8 in 64
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auto dstSwap = rx::getBits(cmdSize, 25, 24);
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// 0 - memory
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// 1 - register
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auto sas = rx::getBit(cmdSize, 26);
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// 0 - memory
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// 1 - register
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auto das = rx::getBit(cmdSize, 27);
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auto saic = rx::getBit(cmdSize, 28);
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auto daic = rx::getBit(cmdSize, 29);
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auto rawWait = rx::getBit(cmdSize, 30);
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void *dst = nullptr;
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switch (dstSel) {
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case 3:
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case 0:
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if (dstSel == 3 || das == 0) {
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auto dstAddress =
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dstAddressLo | (static_cast<std::uint64_t>(dstAddressHi) << 32);
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dst = amdgpu::RemoteMemory{ring.vmId}.getPointer(dstAddress);
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device->caches[ring.vmId].invalidate(
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scheduler, rx::AddressRange::fromBeginSize(dstAddress, size));
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} else {
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dst = getMmRegister(ring, dstAddressLo / sizeof(std::uint32_t));
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}
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break;
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case 1:
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dst = device->caches[ring.vmId].getGdsBuffer().getData() + dstAddressLo;
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break;
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default:
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rx::die("IT_DMA_DATA: unexpected dstSel %u", dstSel);
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}
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void *src = nullptr;
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std::uint32_t srcSize = 0;
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switch (srcSel) {
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case 3:
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case 0:
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if (srcSel == 3 || sas == 0) {
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auto srcAddress =
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srcAddressLo | (static_cast<std::uint64_t>(srcAddressHi) << 32);
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src = amdgpu::RemoteMemory{ring.vmId}.getPointer(srcAddress);
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device->caches[ring.vmId].flush(
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scheduler, rx::AddressRange::fromBeginSize(srcAddress, size));
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} else {
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src = getMmRegister(ring, srcAddressLo / sizeof(std::uint32_t));
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}
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srcSize = ~0;
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break;
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case 1:
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src = device->caches[ring.vmId].getGdsBuffer().getData() + srcAddressLo;
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srcSize = ~0;
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break;
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case 2:
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src = &data;
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srcSize = sizeof(data);
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saic = 1;
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break;
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default:
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rx::die("IT_DMA_DATA: unexpected srcSel %u", srcSel);
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}
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rx::dieIf(size > srcSize && saic == 0,
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"IT_DMA_DATA: out of source size srcSel %u, dstSel %u, size %u",
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srcSel, dstSel, size);
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if (saic != 0) {
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if (daic != 0 && dstSel == 0 && das == 1) {
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std::memcpy(dst, src, sizeof(std::uint32_t));
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} else {
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for (std::uint32_t i = 0; i < size / sizeof(std::uint32_t); ++i) {
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std::memcpy(std::bit_cast<std::uint32_t *>(dst) + i, src,
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sizeof(std::uint32_t));
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}
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}
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} else if (daic != 0 && dstSel == 0 && das == 1) {
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for (std::uint32_t i = 0; i < size / sizeof(std::uint32_t); ++i) {
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std::memcpy(dst, std::bit_cast<std::uint32_t *>(src) + i,
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sizeof(std::uint32_t));
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}
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} else {
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std::memcpy(dst, src, size);
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}
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return true;
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}
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bool ComputePipe::unknownPacket(Ring &ring) {
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auto op = rx::getBits(ring.rptr[0], 15, 8);
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@ -650,11 +783,15 @@ bool GraphicsPipe::processAllRings() {
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}
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void GraphicsPipe::processRing(Ring &ring) {
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int cp;
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int cp = 1;
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if (ring.indirectLevel < 0) {
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cp = 0;
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} else {
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cp = ring.indirectLevel + 1;
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if (ring.indirectLevel == 2) {
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cp = 2;
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}
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}
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while (ring.rptr != ring.wptr) {
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@ -685,7 +822,8 @@ void GraphicsPipe::processRing(Ring &ring) {
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return;
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}
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ring.rptr += len;
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ring.rptr +=
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std::min<std::uint32_t>(ring.size - (ring.rptr - ring.base), len);
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if (op == gnm::IT_INDIRECT_BUFFER || op == gnm::IT_INDIRECT_BUFFER_CNST) {
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break;
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@ -956,7 +1094,7 @@ bool GraphicsPipe::drawIndexAuto(Ring &ring) {
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return true;
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}
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bool GraphicsPipe::numInstances(Ring &ring) {
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uConfig.vgtNumInstances = std::max(ring.rptr[1], 1u);
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uConfig.vgtNumInstances = std::max(std::uint32_t(ring.rptr[1]), 1u);
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return true;
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}
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bool GraphicsPipe::drawIndexMultiAuto(Ring &ring) {
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@ -1024,7 +1162,7 @@ bool GraphicsPipe::writeData(Ring &ring) {
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*dstPointer = data[i];
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}
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} else {
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std::memcpy(dstPointer, data, len * sizeof(std::uint32_t));
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std::memcpy(dstPointer, const_cast<std::uint32_t *>(data), len * sizeof(std::uint32_t));
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}
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return true;
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@ -1264,7 +1402,7 @@ bool GraphicsPipe::eventWriteEos(Ring &ring) {
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case 1: { // store GDS data to memory
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auto sizeDw = rx::getBits(dataInfo, 31, 16);
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auto gdsIndexDw = rx::getBits(dataInfo, 15, 0);
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std::println("event write eos: gds data {:x}-{:x}", gdsIndexDw,
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std::println(stderr, "event write eos: gds data {:x}-{:x}", gdsIndexDw,
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gdsIndexDw + sizeDw);
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auto size = sizeof(std::uint32_t) * sizeDw;
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@ -1431,7 +1569,8 @@ bool GraphicsPipe::setConfigReg(Ring &ring) {
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if (contextOffset + len <= sizeof(context)) {
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std::memcpy(reinterpret_cast<std::uint32_t *>(&context) + contextOffset,
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data, sizeof(std::uint32_t) * len);
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const_cast<std::uint32_t *>(data),
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sizeof(std::uint32_t) * len);
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return true;
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}
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}
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@ -1441,8 +1580,8 @@ bool GraphicsPipe::setConfigReg(Ring &ring) {
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"out of Config regs, offset: %x, count %u, %s\n", offset, len,
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gnm::mmio::registerName(decltype(device->config)::kMmioOffset + offset));
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std::memcpy(reinterpret_cast<std::uint32_t *>(&device->config) + offset, data,
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sizeof(std::uint32_t) * len);
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std::memcpy(reinterpret_cast<std::uint32_t *>(&device->config) + offset,
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const_cast<std::uint32_t *>(data), sizeof(std::uint32_t) * len);
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return true;
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}
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@ -1457,8 +1596,8 @@ bool GraphicsPipe::setShReg(Ring &ring) {
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"out of SH regs, offset: %x, count %u, %s\n", offset, len,
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gnm::mmio::registerName(decltype(sh)::kMmioOffset + offset));
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std::memcpy(reinterpret_cast<std::uint32_t *>(&sh) + offset, data,
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sizeof(std::uint32_t) * len);
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std::memcpy(reinterpret_cast<std::uint32_t *>(&sh) + offset,
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const_cast<std::uint32_t *>(data), sizeof(std::uint32_t) * len);
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// for (std::size_t i = 0; i < len; ++i) {
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// std::fprintf(
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// stderr, "writing to %s value %x\n",
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@ -1487,9 +1626,9 @@ bool GraphicsPipe::setUConfigReg(Ring &ring) {
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for (std::size_t i = 0; i < len; ++i) {
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auto id = decltype(uConfig)::kMmioOffset + offset + i;
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if (auto regName = gnm::mmio::registerName(id)) {
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std::println(stderr, "writing to {} value {:x}", regName, data[i]);
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std::println(stderr, "writing to {} value {:x}", regName, uint32_t(data[i]));
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} else {
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std::println(stderr, "writing to {:x} value {:x}", id, data[i]);
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std::println(stderr, "writing to {:x} value {:x}", id, uint32_t(data[i]));
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}
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}
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}
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@ -1498,8 +1637,8 @@ bool GraphicsPipe::setUConfigReg(Ring &ring) {
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"out of UConfig regs, offset: %u, count %u, %s\n", offset, len,
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gnm::mmio::registerName(decltype(uConfig)::kMmioOffset + offset));
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std::memcpy(reinterpret_cast<std::uint32_t *>(&uConfig) + offset, data,
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sizeof(std::uint32_t) * len);
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std::memcpy(reinterpret_cast<std::uint32_t *>(&uConfig) + offset,
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const_cast<std::uint32_t *>(data), sizeof(std::uint32_t) * len);
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// for (std::size_t i = 0; i < len; ++i) {
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// std::fprintf(
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// stderr, "writing to %s value %x\n",
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@ -1528,9 +1667,9 @@ bool GraphicsPipe::setContextReg(Ring &ring) {
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for (std::size_t i = 0; i < len; ++i) {
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auto id = decltype(context)::kMmioOffset + offset + i;
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if (auto regName = gnm::mmio::registerName(id)) {
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std::println(stderr, "writing to {} value {:x}", regName, data[i]);
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std::println(stderr, "writing to {} value {:x}", regName, uint32_t(data[i]));
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} else {
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std::println(stderr, "writing to {:x} value {:x}", id, data[i]);
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std::println(stderr, "writing to {:x} value {:x}", id, uint32_t(data[i]));
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}
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}
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}
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@ -1539,8 +1678,8 @@ bool GraphicsPipe::setContextReg(Ring &ring) {
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"out of Context regs, offset: %u, count %u, %s\n", offset, len,
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gnm::mmio::registerName(decltype(context)::kMmioOffset + offset));
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std::memcpy(reinterpret_cast<std::uint32_t *>(&context) + offset, data,
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sizeof(std::uint32_t) * len);
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std::memcpy(reinterpret_cast<std::uint32_t *>(&context) + offset,
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const_cast<std::uint32_t *>(data), sizeof(std::uint32_t) * len);
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// for (std::size_t i = 0; i < len; ++i) {
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// std::fprintf(
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@ -1687,8 +1826,9 @@ void CommandPipe::processRing(Ring &ring) {
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rx::die("cmd pipe: unexpected pm4 packet type %u, ring %u, header %u, rptr "
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"%p, wptr "
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"%p, base %p",
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type, ring.indirectLevel, header, ring.rptr, ring.wptr, ring.base);
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"%p, base %p, end %p",
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type, ring.indirectLevel, header, ring.rptr, ring.wptr, ring.base,
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ring.base + ring.size);
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}
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}
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@ -15,8 +15,8 @@ struct Ring {
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std::uint32_t *doorbell{};
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std::uint32_t *base{};
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std::uint64_t size{};
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std::uint32_t *rptr{};
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std::uint32_t *wptr{};
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volatile std::uint32_t *volatile rptr{};
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volatile std::uint32_t *volatile wptr{};
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std::uint32_t *rptrReportLocation{};
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static Ring createFromRange(int vmId, std::uint32_t *base, std::uint64_t size,
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@ -70,6 +70,7 @@ struct ComputePipe {
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bool writeData(Ring &ring);
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bool indirectBuffer(Ring &ring);
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bool acquireMem(Ring &ring);
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bool dmaData(Ring &ring);
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bool unknownPacket(Ring &ring);
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bool handleNop(Ring &ring);
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