Initial Linux Aarch64 support

* Update asmjit dependency (aarch64 branch)
* Disable USE_DISCORD_RPC by default
* Dump some JIT objects in rpcs3 cache dir
* Add SIGILL handler for all platforms
* Fix resetting zeroing denormals in thread pool
* Refactor most v128:: utils into global gv_** functions
* Refactor PPU interpreter (incomplete), remove "precise"
* - Instruction specializations with multiple accuracy flags
* - Adjust calling convention for speed
* - Removed precise/fast setting, replaced with static
* - Started refactoring interpreters for building at runtime JIT
*   (I got tired of poor compiler optimizations)
* - Expose some accuracy settings (SAT, NJ, VNAN, FPCC)
* - Add exec_bytes PPU thread variable (akin to cycle count)
* PPU LLVM: fix VCTUXS+VCTSXS instruction NaN results
* SPU interpreter: remove "precise" for now (extremely non-portable)
* - As with PPU, settings changed to static/dynamic for interpreters.
* - Precise options will be implemented later
* Fix termination after fatal error dialog

rpcs3/util/atomic.cpp

@@ -35,6 +35,7 @@ namespace utils
 
 #include "asm.hpp"
 #include "endian.hpp"
+#include "tsc.hpp"
 
 // Total number of entries.
 static constexpr usz s_hashtable_size = 1u << 17;
@@ -804,17 +805,9 @@ namespace
 	};
 }
 
-#ifdef _MSC_VER
-extern "C" u64 __rdtsc();
-#endif
-
 u64 utils::get_unique_tsc()
 {
-#ifdef _MSC_VER
-	const u64 stamp0 = __rdtsc();
-#else
-    const u64 stamp0 = __builtin_ia32_rdtsc();
-#endif
+	const u64 stamp0 = utils::get_tsc();
 
 	return s_min_tsc.atomic_op([&](u64& tsc)
 	{