mirror of
https://github.com/RPCSX/rpcsx.git
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ARMv7: branch instrs fixed, new instructions
BIC_IMM, BIC_REG, RSB_IMM, LDR_LIT, STRB_REG, STRH_REG Fixed initial stack size
This commit is contained in:
Nekotekina
parent
c267ca2584
commit
5225ca8fc2
9 changed files with 367 additions and 105 deletions
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@ -228,9 +228,9 @@ namespace ARMv7_instrs
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}
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}
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u32 ThumbExpandImm(ARMv7Context& context, u32 imm12)
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u32 ThumbExpandImm(u32 imm12)
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{
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bool carry = context.APSR.C;
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bool carry;
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return ThumbExpandImm_C(imm12, carry, carry);
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}
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@ -418,7 +418,7 @@ void ARMv7_instrs::ADD_IMM(ARMv7Context& context, const ARMv7Code code, const AR
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d = (code.data & 0xf00) >> 8;
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n = (code.data & 0xf0000) >> 16;
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set_flags = (code.data & 0x100000);
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imm32 = ThumbExpandImm(context, (code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff));
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imm32 = ThumbExpandImm((code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff));
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reject(d == 15 && set_flags, "CMN (immediate)");
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reject(n == 13, "ADD (SP plus immediate)");
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@ -567,7 +567,7 @@ void ARMv7_instrs::ADD_SPI(ARMv7Context& context, const ARMv7Code code, const AR
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cond = context.ITSTATE.advance();
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d = (code.data & 0xf00) >> 8;
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set_flags = (code.data & 0x100000);
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imm32 = ThumbExpandImm(context, (code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff));
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imm32 = ThumbExpandImm((code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff));
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reject(d == 15 && set_flags, "CMN (immediate)");
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reject(d == 15, "UNPREDICTABLE");
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@ -770,14 +770,14 @@ void ARMv7_instrs::ASR_REG(ARMv7Context& context, const ARMv7Code code, const AR
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void ARMv7_instrs::B(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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{
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u32 cond, jump;
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u32 cond, imm32;
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switch (type)
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{
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case T1:
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{
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cond = (code.data >> 8) & 0xf;
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jump = 4 + sign<9, u32>((code.data & 0xff) << 1);
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imm32 = sign<9, u32>((code.data & 0xff) << 1);
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reject(cond == 14, "UNDEFINED");
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reject(cond == 15, "SVC");
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@ -787,7 +787,7 @@ void ARMv7_instrs::B(ARMv7Context& context, const ARMv7Code code, const ARMv7_en
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case T2:
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{
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cond = context.ITSTATE.advance();
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jump = 4 + sign<12, u32>((code.data & 0x7ff) << 1);
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imm32 = sign<12, u32>((code.data & 0x7ff) << 1);
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reject(context.ITSTATE, "UNPREDICTABLE");
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break;
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@ -799,7 +799,7 @@ void ARMv7_instrs::B(ARMv7Context& context, const ARMv7Code code, const ARMv7_en
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const u32 s = (code.data >> 26) & 0x1;
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const u32 j1 = (code.data >> 13) & 0x1;
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const u32 j2 = (code.data >> 11) & 0x1;
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jump = 4 + sign<21, u32>(s << 20 | j2 << 19 | j1 << 18 | (code.data & 0x3f0000) >> 4 | (code.data & 0x7ff) << 1);
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imm32 = sign<21, u32>(s << 20 | j2 << 19 | j1 << 18 | (code.data & 0x3f0000) >> 4 | (code.data & 0x7ff) << 1);
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}
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reject(cond >= 14, "Related encodings");
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@ -813,7 +813,7 @@ void ARMv7_instrs::B(ARMv7Context& context, const ARMv7Code code, const ARMv7_en
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const u32 s = (code.data >> 26) & 0x1;
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const u32 i1 = (code.data >> 13) & 0x1 ^ s ^ 1;
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const u32 i2 = (code.data >> 11) & 0x1 ^ s ^ 1;
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jump = 4 + sign<25, u32>(s << 24 | i2 << 23 | i1 << 22 | (code.data & 0x3ff0000) >> 4 | (code.data & 0x7ff) << 1);
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imm32 = sign<25, u32>(s << 24 | i2 << 23 | i1 << 22 | (code.data & 0x3ff0000) >> 4 | (code.data & 0x7ff) << 1);
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}
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reject(context.ITSTATE, "UNPREDICTABLE");
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@ -822,7 +822,7 @@ void ARMv7_instrs::B(ARMv7Context& context, const ARMv7Code code, const ARMv7_en
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case A1:
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{
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cond = code.data >> 28;
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jump = 1 + 4 + sign<26, u32>((code.data & 0xffffff) << 2);
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imm32 = sign<26, u32>((code.data & 0xffffff) << 2);
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break;
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}
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default: throw __FUNCTION__;
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@ -830,8 +830,7 @@ void ARMv7_instrs::B(ARMv7Context& context, const ARMv7Code code, const ARMv7_en
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if (ConditionPassed(context, cond))
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{
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//LOG_NOTICE(ARMv7, "Branch to 0x%x (cond=0x%x)", context.thread.PC + jump, cond);
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context.thread.SetBranch(context.thread.PC + jump);
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context.thread.SetBranch(context.read_pc() + imm32);
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}
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}
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@ -857,20 +856,86 @@ void ARMv7_instrs::BFI(ARMv7Context& context, const ARMv7Code code, const ARMv7_
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void ARMv7_instrs::BIC_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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{
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bool set_flags, carry = context.APSR.C;
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u32 cond, d, n, imm32;
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switch (type)
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{
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case T1:
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{
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cond = context.ITSTATE.advance();
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d = (code.data & 0xf00) >> 8;
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n = (code.data & 0xf0000) >> 16;
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set_flags = (code.data & 0x100000);
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imm32 = ThumbExpandImm_C((code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff), carry, carry);
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reject(d == 13 || d == 15 || n == 13 || n == 15, "UNPREDICTABLE");
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break;
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}
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case A1: throw __FUNCTION__;
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default: throw __FUNCTION__;
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}
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if (ConditionPassed(context, cond))
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{
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const u32 result = context.read_gpr(n) & ~imm32;
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context.write_gpr(d, result);
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if (set_flags)
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{
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context.APSR.N = result >> 31;
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context.APSR.Z = result == 0;
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context.APSR.C = carry;
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}
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}
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}
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void ARMv7_instrs::BIC_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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{
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bool set_flags = !context.ITSTATE;
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u32 cond, d, n, m, shift_t, shift_n;
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switch (type)
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{
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case T1:
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{
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cond = context.ITSTATE.advance();
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d = n = (code.data & 0x7);
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m = (code.data & 0x38) >> 3;
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shift_t = SRType_LSL;
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shift_n = 0;
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break;
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}
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case T2:
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{
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cond = context.ITSTATE.advance();
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d = (code.data & 0xf00) >> 8;
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n = (code.data & 0xf0000) >> 16;
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m = (code.data & 0xf);
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set_flags = (code.data & 0x100000);
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shift_t = DecodeImmShift((code.data & 0x30) >> 4, (code.data & 0x7000) >> 10 | (code.data & 0xc0) >> 6, &shift_n);
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reject(d == 13 || d == 15 || n == 13 || n == 15 || m == 13 || m == 15, "UNPREDICTABLE");
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break;
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}
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case A1: throw __FUNCTION__;
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default: throw __FUNCTION__;
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}
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if (ConditionPassed(context, cond))
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{
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bool carry;
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const u32 shifted = Shift_C(context.read_gpr(m), shift_t, shift_n, context.APSR.C, carry);
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const u32 result = context.read_gpr(n) & ~shifted;
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context.write_gpr(d, result);
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if (set_flags)
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{
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context.APSR.N = result >> 31;
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context.APSR.Z = result == 0;
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context.APSR.C = carry;
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}
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}
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}
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void ARMv7_instrs::BIC_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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@ -895,19 +960,18 @@ void ARMv7_instrs::BKPT(ARMv7Context& context, const ARMv7Code code, const ARMv7
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void ARMv7_instrs::BL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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{
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u32 cond, imm32, newLR;
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u32 cond, imm32;
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switch (type)
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{
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case T1:
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{
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cond = context.ITSTATE.advance();
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newLR = (context.thread.PC + 4) | 1;
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{
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const u32 s = (code.data >> 26) & 0x1;
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const u32 i1 = (code.data >> 13) & 0x1 ^ s ^ 1;
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const u32 i2 = (code.data >> 11) & 0x1 ^ s ^ 1;
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imm32 = 4 + sign<25, u32>(s << 24 | i2 << 23 | i1 << 22 | (code.data & 0x3ff0000) >> 4 | (code.data & 0x7ff) << 1);
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imm32 = sign<25, u32>(s << 24 | i2 << 23 | i1 << 22 | (code.data & 0x3ff0000) >> 4 | (code.data & 0x7ff) << 1);
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}
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reject(context.ITSTATE, "UNPREDICTABLE");
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@ -916,8 +980,7 @@ void ARMv7_instrs::BL(ARMv7Context& context, const ARMv7Code code, const ARMv7_e
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case A1:
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{
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cond = code.data >> 28;
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newLR = (context.thread.PC + 4) - 4;
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imm32 = 4 + sign<26, u32>((code.data & 0xffffff) << 2);
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imm32 = sign<26, u32>((code.data & 0xffffff) << 2);
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break;
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}
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default: throw __FUNCTION__;
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@ -925,8 +988,16 @@ void ARMv7_instrs::BL(ARMv7Context& context, const ARMv7Code code, const ARMv7_e
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if (ConditionPassed(context, cond))
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{
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context.LR = newLR;
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context.thread.SetBranch(context.thread.PC + imm32);
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if (context.ISET == ARM)
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{
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context.LR = context.read_pc() - 4;
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context.thread.SetBranch((context.read_pc() & ~3) + imm32);
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}
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else
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{
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context.LR = context.read_pc() | 1;
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context.thread.SetBranch(context.read_pc() + imm32);
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}
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}
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}
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@ -939,7 +1010,7 @@ void ARMv7_instrs::BLX(ARMv7Context& context, const ARMv7Code code, const ARMv7_
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case T1:
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{
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cond = context.ITSTATE.advance();
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newLR = (context.thread.PC + 2) | 1; // ???
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newLR = (context.thread.PC + 2) | 1;
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{
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const u32 m = (code.data >> 3) & 0xf;
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reject(m == 15, "UNPREDICTABLE");
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@ -957,7 +1028,7 @@ void ARMv7_instrs::BLX(ARMv7Context& context, const ARMv7Code code, const ARMv7_
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const u32 s = (code.data >> 26) & 0x1;
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const u32 i1 = (code.data >> 13) & 0x1 ^ s ^ 1;
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const u32 i2 = (code.data >> 11) & 0x1 ^ s ^ 1;
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target = (context.thread.PC + 4 & ~3) + sign<25, u32>(s << 24 | i2 << 23 | i1 << 22 | (code.data & 0x3ff0000) >> 4 | (code.data & 0x7ff) << 1);
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target = ~3 & context.thread.PC + 4 + sign<25, u32>(s << 24 | i2 << 23 | i1 << 22 | (code.data & 0x3ff0000) >> 4 | (code.data & 0x7ff) << 1);
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}
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reject(context.ITSTATE, "UNPREDICTABLE");
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@ -966,15 +1037,15 @@ void ARMv7_instrs::BLX(ARMv7Context& context, const ARMv7Code code, const ARMv7_
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case A1:
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{
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cond = code.data >> 28;
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newLR = (context.thread.PC + 4) - 4;
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newLR = context.thread.PC + 4;
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target = context.read_gpr(code.data & 0xf);
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break;
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}
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case A2:
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{
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cond = 0xe; // always true
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newLR = (context.thread.PC + 4) - 4;
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target = (context.thread.PC + 4 | 1) + sign<25, u32>((code.data & 0xffffff) << 2 | (code.data & 0x1000000) >> 23);
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newLR = context.thread.PC + 4;
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target = 1 | context.thread.PC + 8 + sign<25, u32>((code.data & 0xffffff) << 2 | (code.data & 0x1000000) >> 23);
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break;
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}
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default: throw __FUNCTION__;
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@ -1038,7 +1109,7 @@ void ARMv7_instrs::CB_Z(ARMv7Context& context, const ARMv7Code code, const ARMv7
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if ((context.read_gpr(n) == 0) ^ nonzero)
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{
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context.thread.SetBranch(context.thread.PC + 2 + imm32);
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context.thread.SetBranch(context.read_pc() + imm32);
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}
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}
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@ -1115,7 +1186,7 @@ void ARMv7_instrs::CMP_IMM(ARMv7Context& context, const ARMv7Code code, const AR
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{
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cond = context.ITSTATE.advance();
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n = (code.data & 0xf0000) >> 16;
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imm32 = ThumbExpandImm(context, (code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff));
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imm32 = ThumbExpandImm((code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff));
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reject(n == 15, "UNPREDICTABLE");
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break;
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@ -1127,11 +1198,14 @@ void ARMv7_instrs::CMP_IMM(ARMv7Context& context, const ARMv7Code code, const AR
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if (ConditionPassed(context, cond))
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{
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bool carry, overflow;
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const u32 res = AddWithCarry(context.read_gpr(n), ~imm32, true, carry, overflow);
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const u32 n_value = context.read_gpr(n);
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const u32 res = AddWithCarry(n_value, ~imm32, true, carry, overflow);
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context.APSR.N = res >> 31;
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context.APSR.Z = res == 0;
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context.APSR.C = carry;
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context.APSR.V = overflow;
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//LOG_NOTICE(ARMv7, "CMP: r%d=0x%08x <> 0x%08x, res=0x%08x", n, n_value, imm32, res);
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}
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}
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@ -1369,11 +1443,40 @@ void ARMv7_instrs::LDR_IMM(ARMv7Context& context, const ARMv7Code code, const AR
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void ARMv7_instrs::LDR_LIT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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{
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u32 cond, t, imm32;
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bool add;
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switch (type)
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{
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case T1:
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{
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cond = context.ITSTATE.advance();
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t = (code.data & 0x700) >> 8;
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imm32 = (code.data & 0xff) << 2;
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add = true;
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break;
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}
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case T2:
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{
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cond = context.ITSTATE.advance();
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t = (code.data & 0xf000) >> 12;
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imm32 = (code.data & 0xfff);
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add = (code.data & 0x800000);
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reject(t == 15 && context.ITSTATE, "UNPREDICTABLE");
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break;
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}
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case A1: throw __FUNCTION__;
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default: throw __FUNCTION__;
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}
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if (ConditionPassed(context, cond))
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{
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const u32 base = context.read_pc() & ~3;
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const u32 addr = add ? base + imm32 : base - imm32;
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const u32 data = vm::psv::read32(addr);
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context.write_gpr(t, data);
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}
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}
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void ARMv7_instrs::LDR_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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@ -2544,11 +2647,48 @@ void ARMv7_instrs::RRX(ARMv7Context& context, const ARMv7Code code, const ARMv7_
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void ARMv7_instrs::RSB_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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{
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bool set_flags = !context.ITSTATE;
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u32 cond, d, n, imm32;
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switch (type)
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{
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case T1:
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{
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cond = context.ITSTATE.advance();
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d = (code.data & 0x7);
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n = (code.data & 0x38) >> 3;
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imm32 = 0;
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break;
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}
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case T2:
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{
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cond = context.ITSTATE.advance();
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d = (code.data & 0xf00) >> 8;
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n = (code.data & 0xf0000) >> 16;
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set_flags = (code.data & 0x100000);
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imm32 = ThumbExpandImm((code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff));
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reject(d == 13 || d == 15 || n == 13 || n == 15, "UNPREDICTABLE");
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break;
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}
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case A1: throw __FUNCTION__;
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default: throw __FUNCTION__;
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}
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if (ConditionPassed(context, cond))
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{
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bool carry, overflow;
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const u32 result = AddWithCarry(~context.read_gpr(n), imm32, true, carry, overflow);
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context.write_gpr(d, result);
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if (set_flags)
|
||||
{
|
||||
context.APSR.N = result >> 31;
|
||||
context.APSR.Z = result == 0;
|
||||
context.APSR.C = carry;
|
||||
context.APSR.V = overflow;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void ARMv7_instrs::RSB_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
|
||||
|
|
@ -3167,11 +3307,57 @@ void ARMv7_instrs::STRB_IMM(ARMv7Context& context, const ARMv7Code code, const A
|
|||
|
||||
void ARMv7_instrs::STRB_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
|
||||
{
|
||||
u32 cond, t, n, m, shift_t, shift_n;
|
||||
bool index, add, wback;
|
||||
|
||||
switch (type)
|
||||
{
|
||||
case T1:
|
||||
{
|
||||
cond = context.ITSTATE.advance();
|
||||
t = (code.data & 0x7);
|
||||
n = (code.data & 0x38) >> 3;
|
||||
m = (code.data & 0x1c0) >> 6;
|
||||
index = true;
|
||||
add = true;
|
||||
wback = false;
|
||||
shift_t = SRType_LSL;
|
||||
shift_n = 0;
|
||||
break;
|
||||
}
|
||||
case T2:
|
||||
{
|
||||
cond = context.ITSTATE.advance();
|
||||
t = (code.data & 0xf000) >> 12;
|
||||
n = (code.data & 0xf0000) >> 16;
|
||||
m = (code.data & 0xf);
|
||||
index = true;
|
||||
add = true;
|
||||
wback = false;
|
||||
shift_t = SRType_LSL;
|
||||
shift_n = (code.data & 0x30) >> 4;
|
||||
|
||||
reject(n == 15, "UNDEFINED");
|
||||
reject(t == 13 || t == 15 || m == 13 || m == 15, "UNPREDICTABLE");
|
||||
break;
|
||||
}
|
||||
case A1: throw __FUNCTION__;
|
||||
default: throw __FUNCTION__;
|
||||
}
|
||||
|
||||
if (ConditionPassed(context, cond))
|
||||
{
|
||||
const u32 offset = Shift(context.read_gpr(m), shift_t, shift_n, context.APSR.C);
|
||||
const u32 offset_addr = add ? context.read_gpr(n) + offset : context.read_gpr(n) - offset;
|
||||
const u32 addr = index ? offset_addr : context.read_gpr(n);
|
||||
|
||||
vm::psv::write8(addr, (u8)context.read_gpr(t));
|
||||
|
||||
if (wback)
|
||||
{
|
||||
context.write_gpr(n, offset_addr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -3205,11 +3391,57 @@ void ARMv7_instrs::STRH_IMM(ARMv7Context& context, const ARMv7Code code, const A
|
|||
|
||||
void ARMv7_instrs::STRH_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
|
||||
{
|
||||
u32 cond, t, n, m, shift_t, shift_n;
|
||||
bool index, add, wback;
|
||||
|
||||
switch (type)
|
||||
{
|
||||
case T1:
|
||||
{
|
||||
cond = context.ITSTATE.advance();
|
||||
t = (code.data & 0x7);
|
||||
n = (code.data & 0x38) >> 3;
|
||||
m = (code.data & 0x1c0) >> 6;
|
||||
index = true;
|
||||
add = true;
|
||||
wback = false;
|
||||
shift_t = SRType_LSL;
|
||||
shift_n = 0;
|
||||
break;
|
||||
}
|
||||
case T2:
|
||||
{
|
||||
cond = context.ITSTATE.advance();
|
||||
t = (code.data & 0xf000) >> 12;
|
||||
n = (code.data & 0xf0000) >> 16;
|
||||
m = (code.data & 0xf);
|
||||
index = true;
|
||||
add = true;
|
||||
wback = false;
|
||||
shift_t = SRType_LSL;
|
||||
shift_n = (code.data & 0x30) >> 4;
|
||||
|
||||
reject(n == 15, "UNDEFINED");
|
||||
reject(t == 13 || t == 15 || m == 13 || m == 15, "UNPREDICTABLE");
|
||||
break;
|
||||
}
|
||||
case A1: throw __FUNCTION__;
|
||||
default: throw __FUNCTION__;
|
||||
}
|
||||
|
||||
if (ConditionPassed(context, cond))
|
||||
{
|
||||
const u32 offset = Shift(context.read_gpr(m), shift_t, shift_n, context.APSR.C);
|
||||
const u32 offset_addr = add ? context.read_gpr(n) + offset : context.read_gpr(n) - offset;
|
||||
const u32 addr = index ? offset_addr : context.read_gpr(n);
|
||||
|
||||
vm::psv::write16(addr, (u16)context.read_gpr(t));
|
||||
|
||||
if (wback)
|
||||
{
|
||||
context.write_gpr(n, offset_addr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -3302,7 +3534,7 @@ void ARMv7_instrs::SUB_IMM(ARMv7Context& context, const ARMv7Code code, const AR
|
|||
d = (code.data & 0xf00) >> 8;
|
||||
n = (code.data & 0xf0000) >> 16;
|
||||
set_flags = (code.data & 0x100000);
|
||||
imm32 = ThumbExpandImm(context, (code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff));
|
||||
imm32 = ThumbExpandImm((code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff));
|
||||
|
||||
reject(d == 15 && set_flags, "CMP (immediate)");
|
||||
reject(n == 13, "SUB (SP minus immediate)");
|
||||
|
|
@ -3429,7 +3661,7 @@ void ARMv7_instrs::SUB_SPI(ARMv7Context& context, const ARMv7Code code, const AR
|
|||
cond = context.ITSTATE.advance();
|
||||
d = (code.data & 0xf00) >> 8;
|
||||
set_flags = (code.data & 0x100000);
|
||||
imm32 = ThumbExpandImm(context, (code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff));
|
||||
imm32 = ThumbExpandImm((code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff));
|
||||
|
||||
reject(d == 15 && set_flags, "CMP (immediate)");
|
||||
reject(d == 15, "UNPREDICTABLE");
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue