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https://github.com/RPCSX/rpcsx.git
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Merge xfloat options
This commit is contained in:
Megamouse
Elad Ashkenazi
parent
e6009794ee
commit
343ba8733b
7 changed files with 70 additions and 62 deletions
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@ -5316,7 +5316,7 @@ public:
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if (src > 0x40000)
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{
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// Use the xfloat hint to create 256-bit (4x double) PHI
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llvm::Type* type = g_cfg.core.spu_accurate_xfloat && bb.reg_maybe_xf[i] ? get_type<f64[4]>() : get_reg_type(i);
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llvm::Type* type = g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::accurate && bb.reg_maybe_xf[i] ? get_type<f64[4]>() : get_reg_type(i);
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const auto _phi = m_ir->CreatePHI(type, ::size32(bb.preds), fmt::format("phi0x%05x_r%u", baddr, i));
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m_block->phi[i] = _phi;
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@ -8876,7 +8876,7 @@ public:
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void FREST(spu_opcode_t op)
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{
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// TODO
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if (g_cfg.core.spu_accurate_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::accurate)
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{
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const auto a = get_vr<f32[4]>(op.ra);
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const auto mask_ov = sext<s32[4]>(bitcast<s32[4]>(fabs(a)) > splat<s32[4]>(0x7e7fffff));
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@ -8885,7 +8885,7 @@ public:
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return;
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}
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if (g_cfg.core.spu_approx_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::approximate)
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{
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register_intrinsic("spu_frest", [&](llvm::CallInst* ci)
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{
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@ -8918,13 +8918,13 @@ public:
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void FRSQEST(spu_opcode_t op)
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{
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// TODO
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if (g_cfg.core.spu_accurate_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::accurate)
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{
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set_vr(op.rt, fsplat<f64[4]>(1.0) / fsqrt(fabs(get_vr<f64[4]>(op.ra))));
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return;
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}
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if (g_cfg.core.spu_approx_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::approximate)
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{
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register_intrinsic("spu_frsqest", [&](llvm::CallInst* ci)
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{
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@ -8956,7 +8956,7 @@ public:
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void FCGT(spu_opcode_t op)
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{
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if (g_cfg.core.spu_accurate_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::accurate)
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{
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set_vr(op.rt, sext<s32[4]>(fcmp_ord(get_vr<f64[4]>(op.ra) > get_vr<f64[4]>(op.rb))));
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return;
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@ -9003,7 +9003,7 @@ public:
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return eval(sext<s32[4]>(bitcast<s32[4]>(a) > bitcast<s32[4]>(b)));
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}
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if (g_cfg.core.spu_approx_xfloat || g_cfg.core.spu_relaxed_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::approximate || g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::relaxed)
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{
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const auto ai = eval(bitcast<s32[4]>(a));
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const auto bi = eval(bitcast<s32[4]>(b));
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@ -9034,7 +9034,7 @@ public:
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void FCMGT(spu_opcode_t op)
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{
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if (g_cfg.core.spu_accurate_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::accurate)
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{
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set_vr(op.rt, sext<s32[4]>(fcmp_ord(fabs(get_vr<f64[4]>(op.ra)) > fabs(get_vr<f64[4]>(op.rb)))));
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return;
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@ -9080,7 +9080,7 @@ public:
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return eval(sext<s32[4]>(mai > mbi));
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}
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if (g_cfg.core.spu_approx_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::approximate)
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{
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return eval(sext<s32[4]>(fcmp_uno(ma > mb) & (mai > mbi)));
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}
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@ -9101,7 +9101,7 @@ public:
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void FA(spu_opcode_t op)
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{
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if (g_cfg.core.spu_accurate_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::accurate)
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{
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set_vr(op.rt, get_vr<f64[4]>(op.ra) + get_vr<f64[4]>(op.rb));
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return;
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@ -9126,7 +9126,7 @@ public:
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void FS(spu_opcode_t op)
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{
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if (g_cfg.core.spu_accurate_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::accurate)
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{
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set_vr(op.rt, get_vr<f64[4]>(op.ra) - get_vr<f64[4]>(op.rb));
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return;
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@ -9137,7 +9137,7 @@ public:
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const auto a = value<f32[4]>(ci->getOperand(0));
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const auto b = value<f32[4]>(ci->getOperand(1));
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if (g_cfg.core.spu_approx_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::approximate)
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{
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const auto bc = clamp_smax(b); // for #4478
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return eval(a - bc);
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@ -9159,7 +9159,7 @@ public:
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void FM(spu_opcode_t op)
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{
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if (g_cfg.core.spu_accurate_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::accurate)
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{
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set_vr(op.rt, get_vr<f64[4]>(op.ra) * get_vr<f64[4]>(op.rb));
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return;
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@ -9170,7 +9170,7 @@ public:
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const auto a = value<f32[4]>(ci->getOperand(0));
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const auto b = value<f32[4]>(ci->getOperand(1));
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if (g_cfg.core.spu_approx_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::approximate)
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{
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if (a.value == b.value)
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{
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@ -9206,7 +9206,7 @@ public:
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void FESD(spu_opcode_t op)
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{
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if (g_cfg.core.spu_accurate_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::accurate)
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{
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const auto r = zshuffle(get_vr<f64[4]>(op.ra), 1, 3);
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const auto d = bitcast<s64[2]>(r);
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@ -9236,7 +9236,7 @@ public:
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void FRDS(spu_opcode_t op)
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{
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if (g_cfg.core.spu_accurate_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::accurate)
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{
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const auto r = get_vr<f64[2]>(op.ra);
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const auto d = bitcast<s64[2]>(r);
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@ -9267,7 +9267,7 @@ public:
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void FCEQ(spu_opcode_t op)
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{
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if (g_cfg.core.spu_accurate_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::accurate)
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{
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set_vr(op.rt, sext<s32[4]>(fcmp_ord(get_vr<f64[4]>(op.ra) == get_vr<f64[4]>(op.rb))));
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return;
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@ -9320,7 +9320,7 @@ public:
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return eval(sext<s32[4]>(bitcast<s32[4]>(a) == bitcast<s32[4]>(b)));
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}
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if (g_cfg.core.spu_approx_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::approximate)
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{
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return eval(sext<s32[4]>(fcmp_ord(a == b)) | sext<s32[4]>(bitcast<s32[4]>(a) == bitcast<s32[4]>(b)));
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}
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@ -9341,7 +9341,7 @@ public:
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void FCMEQ(spu_opcode_t op)
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{
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if (g_cfg.core.spu_accurate_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::accurate)
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{
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set_vr(op.rt, sext<s32[4]>(fcmp_ord(fabs(get_vr<f64[4]>(op.ra)) == fabs(get_vr<f64[4]>(op.rb)))));
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return;
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@ -9397,7 +9397,7 @@ public:
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return eval(sext<s32[4]>(bitcast<s32[4]>(fa) == bitcast<s32[4]>(fb)));
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}
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if (g_cfg.core.spu_approx_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::approximate)
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{
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return eval(sext<s32[4]>(fcmp_ord(fa == fb)) | sext<s32[4]>(bitcast<s32[4]>(fa) == bitcast<s32[4]>(fb)));
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}
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@ -9490,7 +9490,7 @@ public:
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void FNMS(spu_opcode_t op)
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{
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// See FMA.
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if (g_cfg.core.spu_accurate_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::accurate)
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{
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const auto [a, b, c] = get_vrs<f64[4]>(op.ra, op.rb, op.rc);
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set_vr(op.rt4, fmuladd(-a, b, c));
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@ -9503,7 +9503,7 @@ public:
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const auto b = value<f32[4]>(ci->getOperand(1));
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const auto c = value<f32[4]>(ci->getOperand(2));
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if (g_cfg.core.spu_approx_xfloat || g_cfg.core.spu_relaxed_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::approximate || g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::relaxed)
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{
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return fma32x4(eval(-clamp_smax(a)), clamp_smax(b), c);
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}
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@ -9525,7 +9525,7 @@ public:
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void FMA(spu_opcode_t op)
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{
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// Hardware FMA produces the same result as multiple + add on the limited double range (xfloat).
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if (g_cfg.core.spu_accurate_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::accurate)
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{
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const auto [a, b, c] = get_vrs<f64[4]>(op.ra, op.rb, op.rc);
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set_vr(op.rt4, fmuladd(a, b, c));
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@ -9538,7 +9538,7 @@ public:
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const auto b = value<f32[4]>(ci->getOperand(1));
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const auto c = value<f32[4]>(ci->getOperand(2));
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if (g_cfg.core.spu_approx_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::approximate)
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{
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const auto ma = sext<s32[4]>(fcmp_uno(a != fsplat<f32[4]>(0.)));
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const auto mb = sext<s32[4]>(fcmp_uno(b != fsplat<f32[4]>(0.)));
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@ -9599,7 +9599,7 @@ public:
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void FMS(spu_opcode_t op)
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{
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// See FMA.
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if (g_cfg.core.spu_accurate_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::accurate)
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{
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const auto [a, b, c] = get_vrs<f64[4]>(op.ra, op.rb, op.rc);
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set_vr(op.rt4, fmuladd(a, b, -c));
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@ -9612,7 +9612,7 @@ public:
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const auto b = value<f32[4]>(ci->getOperand(1));
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const auto c = value<f32[4]>(ci->getOperand(2));
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if (g_cfg.core.spu_approx_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::approximate)
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{
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return fma32x4(clamp_smax(a), clamp_smax(b), eval(-c));
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}
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@ -9646,7 +9646,7 @@ public:
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void FI(spu_opcode_t op)
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{
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// TODO
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if (g_cfg.core.spu_accurate_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::accurate)
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{
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set_vr(op.rt, get_vr<f64[4]>(op.rb));
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// const auto [a, b] = get_vrs<f64[4]>(op.ra, op.rb);
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@ -9674,7 +9674,7 @@ public:
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return bitcast<f32[4]>((b & 0xff800000u) | (bitcast<u32[4]>(fpcast<f32[4]>(bnew)) & ~0xff800000u)); // Inject old sign and exponent
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});
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if (g_cfg.core.spu_approx_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::approximate)
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{
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register_intrinsic("spu_re", [&](llvm::CallInst* ci)
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{
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@ -9733,7 +9733,7 @@ public:
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void CFLTS(spu_opcode_t op)
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{
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if (g_cfg.core.spu_accurate_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::accurate)
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{
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value_t<f64[4]> a = get_vr<f64[4]>(op.ra);
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value_t<f64[4]> s;
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@ -9807,7 +9807,7 @@ public:
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void CFLTU(spu_opcode_t op)
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{
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if (g_cfg.core.spu_accurate_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::accurate)
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{
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value_t<f64[4]> a = get_vr<f64[4]>(op.ra);
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value_t<f64[4]> s;
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@ -9890,7 +9890,7 @@ public:
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void CSFLT(spu_opcode_t op)
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{
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if (g_cfg.core.spu_accurate_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::accurate)
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{
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value_t<s32[4]> a = get_vr<s32[4]>(op.ra);
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value_t<f64[4]> r;
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@ -9930,7 +9930,7 @@ public:
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void CUFLT(spu_opcode_t op)
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{
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if (g_cfg.core.spu_accurate_xfloat)
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if (g_cfg.core.spu_xfloat_accuracy == xfloat_accuracy::accurate)
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{
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value_t<s32[4]> a = get_vr<s32[4]>(op.ra);
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value_t<f64[4]> r;
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