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SPU/PPU: Implement Atomic Cache Line Stores

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This commit is contained in:
Eladash 2020-09-25 17:29:25 +03:00 • committed by Ivan
parent 9baef8c705
commit 09cddc84be
9 changed files with 156 additions and 79 deletions
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12
rpcs3/Emu/Cell/PPUTranslator.cpp
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@ -3502,8 +3502,16 @@ void PPUTranslator::ICBI(ppu_opcode_t op)
void PPUTranslator::DCBZ(ppu_opcode_t op)
{
const auto ptr = GetMemory(m_ir->CreateAnd(op.ra ? m_ir->CreateAdd(GetGpr(op.ra), GetGpr(op.rb)) : GetGpr(op.rb), -128), GetType<u8>());
Call(GetType<void>(), "llvm.memset.p0i8.i32", ptr, m_ir->getInt8(0), m_ir->getInt32(128), m_ir->getTrue());
const auto addr = m_ir->CreateAnd(op.ra ? m_ir->CreateAdd(GetGpr(op.ra), GetGpr(op.rb)) : GetGpr(op.rb), -128);
if (g_cfg.core.accurate_cache_line_stores)
{
Call(GetType<void>(), "__dcbz", addr);
}
else
{
Call(GetType<void>(), "llvm.memset.p0i8.i32", GetMemory(addr, GetType<u8>()), m_ir->getInt8(0), m_ir->getInt32(128), m_ir->getTrue());
}
}
void PPUTranslator::LWZ(ppu_opcode_t op)