2013-08-03 11:40:03 +02:00
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#pragma once
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2017-02-17 20:35:57 +01:00
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enum MFC : u8
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2013-08-03 11:40:03 +02:00
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{
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2014-04-04 15:25:38 +02:00
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MFC_PUT_CMD = 0x20, MFC_PUTB_CMD = 0x21, MFC_PUTF_CMD = 0x22,
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2015-03-02 03:10:41 +01:00
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MFC_PUTS_CMD = 0x28, MFC_PUTBS_CMD = 0x29, MFC_PUTFS_CMD = 0x2a,
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2014-04-04 15:25:38 +02:00
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MFC_PUTR_CMD = 0x30, MFC_PUTRB_CMD = 0x31, MFC_PUTRF_CMD = 0x32,
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MFC_GET_CMD = 0x40, MFC_GETB_CMD = 0x41, MFC_GETF_CMD = 0x42,
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2015-03-02 03:10:41 +01:00
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MFC_GETS_CMD = 0x48, MFC_GETBS_CMD = 0x49, MFC_GETFS_CMD = 0x4a,
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2014-04-04 15:25:38 +02:00
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MFC_PUTL_CMD = 0x24, MFC_PUTLB_CMD = 0x25, MFC_PUTLF_CMD = 0x26,
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MFC_PUTRL_CMD = 0x34, MFC_PUTRLB_CMD = 0x35, MFC_PUTRLF_CMD = 0x36,
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MFC_GETL_CMD = 0x44, MFC_GETLB_CMD = 0x45, MFC_GETLF_CMD = 0x46,
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2013-12-10 23:58:11 +01:00
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MFC_GETLLAR_CMD = 0xD0,
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MFC_PUTLLC_CMD = 0xB4,
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MFC_PUTLLUC_CMD = 0xB0,
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MFC_PUTQLLUC_CMD = 0xB8,
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2014-03-15 22:33:19 +01:00
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2014-04-04 15:25:38 +02:00
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MFC_SNDSIG_CMD = 0xA0, MFC_SNDSIGB_CMD = 0xA1, MFC_SNDSIGF_CMD = 0xA2,
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2013-12-10 23:58:11 +01:00
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MFC_BARRIER_CMD = 0xC0,
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MFC_EIEIO_CMD = 0xC8,
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MFC_SYNC_CMD = 0xCC,
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MFC_BARRIER_MASK = 0x01,
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MFC_FENCE_MASK = 0x02,
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2014-03-15 16:43:14 +01:00
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MFC_LIST_MASK = 0x04,
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2015-03-02 03:10:41 +01:00
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MFC_START_MASK = 0x08,
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2014-03-15 22:33:19 +01:00
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MFC_RESULT_MASK = 0x10, // ???
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2013-08-03 11:40:03 +02:00
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};
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2014-01-10 02:30:59 +01:00
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// Atomic Status Update
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2015-03-02 03:10:41 +01:00
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enum : u32
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2014-01-10 02:30:59 +01:00
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{
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MFC_PUTLLC_SUCCESS = 0,
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2015-03-02 03:10:41 +01:00
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MFC_PUTLLC_FAILURE = 1, // reservation was lost
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2014-01-10 02:30:59 +01:00
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MFC_PUTLLUC_SUCCESS = 2,
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MFC_GETLLAR_SUCCESS = 4,
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};
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2015-01-29 15:50:34 +01:00
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// MFC Write Tag Status Update Request Channel (ch23) operations
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2015-03-02 03:10:41 +01:00
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enum : u32
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2015-01-29 15:50:34 +01:00
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{
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MFC_TAG_UPDATE_IMMEDIATE = 0,
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MFC_TAG_UPDATE_ANY = 1,
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MFC_TAG_UPDATE_ALL = 2,
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};
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2015-03-02 03:10:41 +01:00
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enum : u32
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2013-08-03 11:40:03 +02:00
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{
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2014-04-04 15:25:38 +02:00
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MFC_PPU_DMA_CMD_ENQUEUE_SUCCESSFUL = 0x00,
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MFC_PPU_DMA_CMD_SEQUENCE_ERROR = 0x01,
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MFC_PPU_DMA_QUEUE_FULL = 0x02,
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2013-08-03 11:40:03 +02:00
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};
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2015-03-02 03:10:41 +01:00
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enum : u32
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{
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MFC_PROXY_COMMAND_QUEUE_EMPTY_FLAG = 0x80000000,
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};
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enum : u32
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2013-08-03 11:40:03 +02:00
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{
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2014-04-04 15:25:38 +02:00
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MFC_PPU_MAX_QUEUE_SPACE = 0x08,
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MFC_SPU_MAX_QUEUE_SPACE = 0x10,
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2013-08-03 11:40:03 +02:00
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};
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2017-01-25 00:22:19 +01:00
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enum : u32
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{
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MFC_DMA_TAG_STATUS_UPDATE_EVENT = 0x00000001,
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MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT = 0x00000002,
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MFC_DMA_QUEUE_VACANCY_EVENT = 0x00000008,
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MFC_SPU_MAILBOX_WRITTEN_EVENT = 0x00000010,
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MFC_DECREMENTER_EVENT = 0x00000020,
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MFC_PU_INT_MAILBOX_AVAIL_EVENT = 0x00000040,
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MFC_PU_MAILBOX_AVAIL_EVENT = 0x00000080,
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MFC_SIGNAL_2_EVENT = 0x00000100,
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MFC_SIGNAL_1_EVENT = 0x00000200,
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MFC_LLR_LOST_EVENT = 0x00000400,
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MFC_PRIV_ATTN_EVENT = 0x00000800,
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2018-03-24 17:21:50 +01:00
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MFC_MULTISOURCE_SYNC_EVENT = 0x00001000,
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2017-01-25 00:22:19 +01:00
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};
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2017-02-17 20:35:57 +01:00
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struct alignas(16) spu_mfc_cmd
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{
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MFC cmd;
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u8 tag;
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u16 size;
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u32 lsa;
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u32 eal;
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u32 eah;
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};
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