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unicorn/qemu/target
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Richard Henderson e4a7a089f0 target/arm: Mask CPSR_J when Jazelle is not enabled 
The J bit signals Jazelle mode, and so of course is RES0
when the feature is not enabled.

Backports commit f062d1447f2a80e7a5f593b8cb5ac7cab5e16eb0 from qemu
2020-03-21 17:17:50 -04:00
..
arm target/arm: Mask CPSR_J when Jazelle is not enabled 2020-03-21 17:17:50 -04:00
i386 target/i386: Add the 'model-id' for Skylake -v3 CPU models 2020-03-21 12:27:24 -04:00
m68k m68k: Fix regression causing Single-Step via GDB/RSP to not single step 2020-03-21 12:15:08 -04:00
mips target/arm: fix TCG leak for fcvt half->double 2020-03-21 13:14:47 -04:00
riscv target/riscv: update mstatus.SD when FS is set dirty 2020-03-21 12:22:56 -04:00
sparc target/sparc: sun4u Invert Endian TTE bit 2020-01-07 19:21:30 -05:00