Stefan Hajnoczi d2f3a6c0d5 target/arm: add cortex-m0 CPU model ... Define a "cortex-m0" ARMv6-M CPU model. Most of the register reset values set by other CPU models are not relevant for the cut-down ARMv6-M architecture. Backports commit 191776b96a381b5d2b8d3f90c1c02b3e4779e5f7 from qemu		2018-08-17 14:01:00 -04:00
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arm	target/arm: add cortex-m0 CPU model	2018-08-17 14:01:00 -04:00
i386	i386: implement MSR_SMI_COUNT for TCG	2018-08-02 21:27:08 -04:00
m68k	target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn	2018-06-15 11:40:18 -04:00
mips	target/mips: Fix data type for offset	2018-07-03 01:01:09 -04:00
sparc	tcg: Pass tb and index to tcg_gen_exit_tb separately	2018-06-07 11:56:32 -04:00