Yifei Jiang c50f8c9d93 target/riscv: Fix the bug of HLVX/HLV/HSV ... We found that the hypervisor virtual-machine load and store instructions, included HLVX/HLV/HSV, couldn't access guest userspace memory. In the riscv-privileged spec, HLVX/HLV/HSV is defined as follow: "As usual when V=1, two-stage address translation is applied, and the HS-level sstatus.SUM is ignored." But get_physical_address() doesn't ignore sstatus.SUM, when HLVX/HLV/HSV accesses guest userspace memory. So this patch fixes it. Backports c63ca4ff7f81116c26984973052991ff0bd7caec		2021-03-08 15:16:06 -05:00
..
arm	qemu/atomic.h: rename atomic_ to qatomic_	2021-03-08 14:34:35 -05:00
i386	qemu/atomic.h: rename atomic_ to qatomic_	2021-03-08 14:34:35 -05:00
m68k	m68k: Fix build	2021-03-05 08:29:53 -05:00
mips	mips: Fix build	2021-03-05 08:51:51 -05:00
riscv	target/riscv: Fix the bug of HLVX/HLV/HSV	2021-03-08 15:16:06 -05:00
sparc	sparc: Fix build	2021-03-05 08:54:43 -05:00