Bastian Koppelmann c0f036578c target/riscv: Fix manually parsed 16 bit insn ... during the refactor to decodetree we removed the manual decoding that is necessary for c.jal/c.addiw and removed the translation of c.flw/c.ld and c.fsw/c.sd. This reintroduces the manual parsing and the omited implementation. Backports commit f330433b3633647b047cfa418c2ca4d18fda69c7 from qemu		2019-03-19 05:44:58 -04:00
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arm	target/arm: Check access permission to ADDVL/ADDPL/RDVL	2019-03-19 05:42:59 -04:00
i386	i386: extended the cpuid_level when Intel PT is enabled	2019-03-11 16:40:23 -04:00
m68k	target/m68k: Correct instruction emulation	2019-02-28 19:21:49 -05:00
mips	target/mips: Restore Qemu's organization of CPU definitions	2019-03-08 01:40:50 -05:00
riscv	target/riscv: Fix manually parsed 16 bit insn	2019-03-19 05:44:58 -04:00
sparc	target: Resolve repeated typedef warnings	2019-01-22 20:27:35 -05:00