Wanpeng Li b41364fdc5 i386: Enable IA32_MISC_ENABLE MWAIT bit when exposing mwait/monitor ... The CPUID.01H:ECX[bit 3] ought to mirror the value of the MSR IA32_MISC_ENABLE MWAIT bit and as userspace has control of them both, it is userspace's job to configure both bits to match on the initial setup. Backports commit 4cfd7bab3f5564f6c1a23b06f73d5aa2f957cd16 from qemu		2019-06-04 13:17:43 -04:00
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arm	target/arm: Fix vector operation segfault	2019-05-24 18:02:32 -04:00
i386	i386: Enable IA32_MISC_ENABLE MWAIT bit when exposing mwait/monitor	2019-06-04 13:17:43 -04:00
m68k	target/m68k: Optimize rotate_x() using extract_i32()	2019-05-17 12:07:07 -04:00
mips	target/mips: Improve performance of certain MSA instructions	2019-06-03 11:21:05 -04:00
riscv	target/riscv: Only flush TLB if SATP.ASID changes	2019-05-28 19:22:51 -04:00
sparc	tcg: Use CPUClass::tlb_fill in cputlb.c	2019-05-16 17:35:37 -04:00