Richard Henderson a62b4e5def target/riscv: Split RVC32 and RVC64 insns into separate files ... This eliminates all functions in insn_trans/trans_rvc.inc.c, so the entire file can be removed. Backports commit 0e68e240a9bd3b44a91cd6012f0e2bf2a43b9fe2 from qemu		2019-05-28 19:00:23 -04:00
..
trans_privileged.inc.c	RISC-V: fix single stepping over ret and other branching instructions	2019-05-28 18:35:07 -04:00
trans_rva.inc.c	target/riscv: Convert RV64A insns to decodetree	2019-03-18 16:27:53 -04:00
trans_rvd.inc.c	target/riscv: Convert RV64D insns to decodetree	2019-03-18 16:57:16 -04:00
trans_rvf.inc.c	target/riscv: Convert RV64F insns to decodetree	2019-03-18 16:43:17 -04:00
trans_rvi.inc.c	target/riscv: Use pattern groups in insn16.decode	2019-05-28 18:55:28 -04:00
trans_rvm.inc.c	target/riscv: Zero extend the inputs of divuw and remuw	2019-03-26 20:38:17 -04:00