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5e97271942
New CPU models mostly inherit features from ancestor Skylake, while addin new features: UMIP, New Instructions ( PCONIFIG (server only), WBNOINVD, AVX512_VBMI2, GFNI, AVX512_VNNI, VPCLMULQDQ, VAES, AVX512_BITALG), Intel PT and 5-level paging (Server only). As well as IA32_PRED_CMD, SSBD support for speculative execution side channel mitigations. Note: For 5-level paging, Guest physical address width can be configured, with parameter "phys-bits". Unless explicitly specified, we still use its default value, even for Icelake-Server cpu model. At present, hold on expose IA32_ARCH_CAPABILITIES to guest, as 1) This MSR actually presents more than 1 'feature', maintainers are considering expanding current features presentation of only CPUIDs to MSR bits; 2) a reasonable default value for MSR_IA32_ARCH_CAPABILITIES needs to settled first. These 2 are actully beyond Icelake CPU model itself but fundamental. So split these work apart and do it later. https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00774.html https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00796.html Backports commit 8a11c62da9146dd89aee98947e6bd831e65a970d from qemu |
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| .. | ||
| arch_memory_mapping.c | ||
| bpt_helper.c | ||
| cc_helper.c | ||
| cc_helper_template.h | ||
| cpu-qom.h | ||
| cpu.c | ||
| cpu.h | ||
| excp_helper.c | ||
| fpu_helper.c | ||
| helper.c | ||
| helper.h | ||
| int_helper.c | ||
| Makefile.objs | ||
| mem_helper.c | ||
| misc_helper.c | ||
| mpx_helper.c | ||
| ops_sse.h | ||
| ops_sse_header.h | ||
| seg_helper.c | ||
| shift_helper_template.h | ||
| smm_helper.c | ||
| svm.h | ||
| svm_helper.c | ||
| TODO | ||
| topology.h | ||
| translate.c | ||
| unicorn.c | ||
| unicorn.h | ||