Peter Maydell 4dc69f4b26 target/arm: Correct MPU trace handling of write vs execute ... Correct off-by-one bug in the PSMAv7 MPU tracing where it would print a write access as "reading", an insn fetch as "writing", and a read access as "execute". Since we have an MMUAccessType enum now, we can make the code clearer in the process by using that rather than the raw 0/1/2 values. Backports commit 709e4407add7acacc593cb6cdac026558c9a8fb6 from qemu		2018-03-04 01:13:19 -05:00
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arm	target/arm: Correct MPU trace handling of write vs execute	2018-03-04 01:13:19 -05:00
i386	tcg: Pass generic CPUState to gen_intermediate_code()	2018-03-03 23:34:18 -05:00
m68k	tcg: Pass generic CPUState to gen_intermediate_code()	2018-03-03 23:34:18 -05:00
mips	target/mips: Enable CP0_EBase.WG on MIPS64 CPUs	2018-03-04 01:09:47 -05:00
sparc	tcg: Pass generic CPUState to gen_intermediate_code()	2018-03-03 23:34:18 -05:00