Alistair Francis 2ed6459e98 target/riscv: Add the mcountinhibit CSR ... 1.11 defines mcountinhibit, which has the same numeric CSR value as mucounteren from 1.09.1 but has different semantics. This patch enables the CSR for 1.11-based targets, which is trivial to implement because the counters in QEMU never tick (legal according to the spec). Backports commit 747a43e818dc36bd50ef98c2b11a7c31ceb810fa from qemu		2019-08-08 17:04:52 -04:00
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arm	target/arm: Declare some M-profile functions publicly	2019-08-08 15:37:01 -04:00
i386	target/i386: define a new MSR based feature word - FEAT_CORE_CAPABILITY	2019-06-25 18:59:52 -05:00
m68k	m68k comments break patch submission due to being incorrectly formatted	2019-08-08 14:26:45 -04:00
mips	target/mips: Correct helper for MSA FCLASS.<W|D> instructions	2019-08-08 16:30:15 -04:00
riscv	target/riscv: Add the mcountinhibit CSR	2019-08-08 17:04:52 -04:00
sparc	cpu: Introduce CPUNegativeOffsetState	2019-06-13 15:08:25 -04:00