Peter Maydell 28fcb58c69 target/arm: Implement HCR.VI and VF ... The HCR_EL2 VI and VF bits are supposed to track whether there is a pending virtual IRQ or virtual FIQ. For QEMU we store the pending VIRQ/VFIQ status in cs->interrupt_request, so this means: * if the register is read we must get these bit values from cs->interrupt_request * if the register is written then we must write the bit values back into cs->interrupt_request Backports commit 8a0fc3a29fc2315325400c738f807d0d4ae0ab7f from qemu		2018-11-10 09:23:21 -05:00
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arm	target/arm: Implement HCR.VI and VF	2018-11-10 09:23:21 -05:00
i386	target/i386: Convert to HAVE_CMPXCHG128	2018-10-23 15:21:03 -04:00
m68k	Removes accessible assert	2018-10-06 05:02:20 -04:00
mips	target/mips: Add opcodes for nanoMIPS EVA instructions	2018-10-23 14:33:08 -04:00
sparc	Sparc increase ttl number	2018-10-06 04:55:52 -04:00