Bastian Koppelmann 1024ceb4df target/riscv: Convert RV64I load/store insns to decodetree ... this splits the 64-bit only instructions into its own decode file such that we generate the decoder for these instructions only for the RISC-V 64 bit target. Backports commit 7e45a682edc32ba90d6955215f062210531b835b from qemu		2019-03-18 16:02:16 -04:00
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arm	Add ARM MSP, PSP and CONTROL register access (#1071)	2019-03-08 02:24:49 -05:00
i386	i386: extended the cpuid_level when Intel PT is enabled	2019-03-11 16:40:23 -04:00
m68k	target/m68k: Correct instruction emulation	2019-02-28 19:21:49 -05:00
mips	target/mips: Restore Qemu's organization of CPU definitions	2019-03-08 01:40:50 -05:00
riscv	target/riscv: Convert RV64I load/store insns to decodetree	2019-03-18 16:02:16 -04:00
sparc	target: Resolve repeated typedef warnings	2019-01-22 20:27:35 -05:00