Alistair Francis 1001f0ba1f target/riscv: Correctly implement TSR trap ... As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't correctly handling illegal instructions based on the value of MSTATUS_TSR and the current privledge level. This patch fixes the issue raised in the bug by raising an illegal instruction if TSR is set and we are in S-Mode. Backports commit ed5abf46b3c414ef58e647145f19b3966700b206 from qemu		2020-04-30 06:19:49 -04:00
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arm	target/arm: Disable clean_data_tbi for system mode	2020-04-30 06:18:31 -04:00
i386	target/i386: check for empty register in FXAM	2020-03-21 19:43:24 -04:00
m68k	m68k: Fix regression causing Single-Step via GDB/RSP to not single step	2020-03-21 12:15:08 -04:00
mips	target/arm: fix TCG leak for fcvt half->double	2020-03-21 13:14:47 -04:00
riscv	target/riscv: Correctly implement TSR trap	2020-04-30 06:19:49 -04:00
sparc	target/sparc: sun4u Invert Endian TTE bit	2020-01-07 19:21:30 -05:00