Peter Maydell 08b70267d0 target/arm: Implement VFP fp16 VMOV between gp and halfprec registers ... Implement the VFP fp16 variant of VMOV that transfers a 16-bit value between a general purpose register and a VFP register. Note that Rt == 15 is UNPREDICTABLE; since this insn is v8 and later only we have no need to replicate the old "updates CPSR.NZCV" behaviour that the singleprec version of this insn does Backports commit 46a4b854525cb9f34a611f6ada6cdff1eab0ac2d		2021-03-01 16:26:34 -05:00
..
arm	target/arm: Implement VFP fp16 VMOV between gp and halfprec registers	2021-03-01 16:26:34 -05:00
i386	target/i386: floatx80: avoid compound literals in static initializers	2021-02-25 23:38:54 -05:00
m68k	target/m68k: consolidate physical translation offset into get_physical_address()	2021-02-25 23:13:48 -05:00
mips	target/mips: Support variable page size	2020-06-14 21:09:51 -04:00
riscv	target/riscv: vector single-width integer multiply instructions	2021-02-26 10:46:26 -05:00
sparc	softfloat: Name compare relation enum	2020-05-21 18:08:52 -04:00