Alistair Francis 009a52dd13 target/arm: Correct exclusive store cmpxchg memop mask ... When we perform the atomic_cmpxchg operation we want to perform the operation on a pair of 32-bit registers. Previously we were just passing the register size in which was set to MO_32. This would result in the high register to be ignored. To fix this issue we hardcode the size to be 64-bits long when operating on 32-bit pairs. Backports commit 955fd0ad5d610f62ba2f4ce46a872bf50434dcf8 from qemu		2018-03-04 01:43:55 -05:00
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arm	target/arm: Correct exclusive store cmpxchg memop mask	2018-03-04 01:43:55 -05:00
i386	target/i386: set rip_offset for some SSE4.1 instructions	2018-03-04 01:41:43 -05:00
m68k	tcg: Pass generic CPUState to gen_intermediate_code()	2018-03-03 23:34:18 -05:00
mips	target/mips: Fix RDHWR CC with icount	2018-03-04 01:35:25 -05:00
sparc	tcg: Pass generic CPUState to gen_intermediate_code()	2018-03-03 23:34:18 -05:00